Abstract: Line shortening and other defects in integrated circuits are measured by imprinting accuracy determinative patterns in the scribe lines or die margins of the mask field. The patterns are ideally formed in the general nature of the usual box in a box configuration with one of the boxes being specially configured to include a series of lines and spaces having narrow widths comparable to the width of the lines to be formed in the integrated circuit. The use of the narrow lines provides the box in a box configuration with the same line shortening that the circuit feature will itself experience. Small spaces between the lines permit the standard measuring equipment to locate at the ends of the lines.

Abstract: In accordance with the preferred embodiment of the present invention, a logic cell library is built. Within the logic cell library a timing model for a first logic cell is generated. In order to generate the timing model a number of indices which specify input ramp for the first logic cell is selected. Also, a number of indices which specify output load for the first logic cell is selected. Also selected are a minimum value for the input ramp and a maximum value for the input ramp. A maximum output load for the timing model is calculated. This is done by calculating, for every input transition in the logic cell which causes an output transition, an intermediate value to be an output load value which results in the first logic cell producing an output signal to the first logic cell which has the maximum value for the input ramp when an input signal to the logic cell has the minimum value for the input ramp. The maximum output load is chosen to be a minimum of the calculated intermediate values.

Abstract: An antifuse structure and method for making the antifuse structure having a doped antifuse layer is disclosed. The doped antifuse layer is preferably deposited over a lower electrode. A barrier layer may then be formed over the doped antifuse layer and an upper electrode may subsequently be deposited over the barrier layer. The method of depositing the doped antifuse layer includes: (a) providing a chemical vapor deposition reactor having a support chuck for supporting a partially fabricated silicon wafer; (b) powering up the chemical vapor deposition reactor and heating the partially fabricated silicon wafer; (c) selecting a dopant species for the antifuse layer (e.g, n-type or p-type); (d) introducing a gaseous mixture of a silane compound and the selected dopant species into the chemical vapor deposition reactor with the aid of a neutral species; and (e) depositing the antifuse layer over the lower electrode.

Abstract: Secure operations within an integrated circuit are protected. In order to perform the protection a plurality of single event upset detectors are distributed within the integrated circuit. The single event upset detectors include bit-registers. Each of the plurality of the single event upset detectors is monitored for a single event upset. When a single event upset in any of the single event upset detectors is detected, an error condition is indicated.

Abstract: A focus evaluation technique for photolithography equipment is disclosed. This technique includes providing a substrate having a photoresist coating for treatment by the equipment. The equipment is activated to focus a first part of a image on a region of the surface and defocus a second part of the image relative to the region. The region is tilted relative to an image plane defined by the equipment. This activation is repeated for each of a number of spaced-apart regions along the surface. The substrate is processed to provide a pattern for each of the regions corresponding to the first and second parts. The equipment is characterized from the pattern for each of the regions. This characterization may result from inspection of the pattern relative to reference marks provided for each region. Focus information for the equipment which accounts for lens heating may be determined from this inspection.

Abstract: A method for preparing a semiconductor substrate and a polysilicon gate for subsequent silicide formation. In one embodiment, the present invention performs an oxide etch to remove oxide from source and drain diffusion regions of the semiconductor substrate and from the top surface of the polysilicon gate. Next, the present invention subjects the semiconductor substrate and the polysilicon gate to an ashing environment. In the present invention, the ashing environment is comprised of H.sub.2 O vapor, and a gaseous fluorocarbon or a fluorinated hydrocarbon gas. In so doing, contaminants introduced into the source and drain diffusion regions of the semiconductor substrate and into the top surface of the polysilicon gate during the oxide etch are removed. Next, the present invention performs a semiconductor wafer surface clean step. The semiconductor wafer surface clean step provides a semiconductor wafer surface which is substantially similar to a virgin silicon surface.

Abstract: The present invention relates to a system and a method for reducing access times for retrieving audio samples. The system uses a wave table cache. The wave table cache allows devices such as a Digital Signal Processor (DSP) to retrieve audio samples in a linear fashion from the wave table cache at a rate much faster than individually fetching the required portions of the audio sample from the main memory of the system. The DSP may then use the audio samples to generate signals to create sounds based on the audio samples.

Abstract: The invention relates to a computer implemented process for fixing hold time violations in hierarchical designs of electronic circuits. The process comprises the steps of:1) synthesizing a RTL-HDL type description of the circuit to form a synthesized design,2) synthesizing a clock tree and adding it to the synthesized design produced in step 1,3) optimizing the synthesized design resulting from step 2, and fixing upper-bounded timing constraints by using a real clock timing (latency and skew) and worst case conditions,4) fixing lower-bounded timing violations in the optimized synthesized design resulting from step 3, using a real clock timing, using best case conditions,5) re-fixing possible upper-bounded timing constraints newly created and possible upper-bounded timing constraints increased in step 4,6) fixing post-layout upper-bounded timing violations.

Abstract: Within a single integrated circuit, a bus operates in accordance with a bus protocol. The bus protocol includes a first control signal which, when not implemented within a single integrated circuit, is implemented using a pull-up resistor and tri-state gates within functional blocks attached to the bus. A first functional block includes a first input line for receiving an input component of the first control signal, and includes first logic means for generating a first output component of the first control signal. A second functional block includes a second input line for receiving the input component of the first control signal, and includes second logic means for generating a second output component of the first control signal. A logic block includes first logic for generating the input component of the first control signal. The first logic utilizes the first output component and the second output component to generate the input component of the first control signal.

Abstract: Versatility of access to a register set within a direct memory access (DMA) controller is increased. The DMA controller controls direct memory access transfers to and from a main memory. When a first control field in a configuration register has a first value, normal operating access is provided to a register set within the DMA controller. The register set provides control and status of the direct memory access transfers to and from the main memory. When the first control field in the configuration register has a second value special access is provided to the register set. The special access allows storage and restoration of a state of a DMA transfer.

Abstract: A digital to analog converter (DAC) offset autocalibration system in a digital synthesizer integrated circuit. The present invention includes a DAC coupled to a filter. The input of the DAC accepts digital values for conversion to an analog signal. The output of the DAC is coupled to the input of the filter. The filter smoothes the analog signal received from the DAC. A switch is coupled to the filter output to receive the analog signal. A comparator is coupled to the switch. The input of the comparator receives the analog signal from the filter output via the switch. An autocalibration control circuit is coupled to the output of the comparator, to the switch, and to the DAC. The autocalibration control circuit is adapted to input a value to the DAC in order to determine an offset correction from the output of the comparator and adjust the analog signal using the offset correction.

Abstract: An apparatus and method for minimizing bus traffic by combining write operations is disclosed. The present invention detects the occurrence of consecutive byte updates to a common 32-bit block. This is accomplished by using comparators to examine the addresses of consecutive write operations. If it is determined that the consecutive write operations are indeed to a common 32-bit block, they are combined. The address of the next write operation is also, similarly checked. All of the writes into that particular block are combined in a write combine register. The contents of this register is then transferred to a write buffer. When bus access is granted, the combined byte updates stored in the write buffer are issued in a single memory write cycle to the bus, thereby minimizing the number of write cycles actually required to transfer the data.

Abstract: A method and implementing system includes transmitting a sampled and digitized source analog signal which is sampled for transmission at a rate of FT, to a receiving device and converting the received signal by a first sample rate converter circuit which is effective to multiply the sample rate FT by a first factor "N". The converted signal is then processed by a receiver sampler circuit and applied to a second sample rate converter circuit operating at a rate of a receiver frequency FR. The second sample rate converter circuit is effective to divide the processed signal by a second factor "M". The signal is then processed by a digital to analog converter and filtered to filter out the spurious components and provide a reproduction of the source analog signal.

Abstract: A fixture for use with a wire pull tester that tests the strength of a bond between an electrical contact of a semiconductor device and a wire affixed to the electrical contact. The fixture comprises a device support, a mounting surface provided on the device support, and a port provided at the mounting surface. The device support may include a height adjustment mechanism. The mounting surface may be configured to engage a surface of the semiconductor device and includes a port with which an air pressure differential is produced to maintain engagement between the mounting surface and the semiconductor device surface.

Abstract: The present invention is a micro-electromechanical voltage shifter. According to one embodiment, the voltage shifter of the present invention comprises a capacitor and micro-electromechanical means for changing a capacitance of the capacitor. The capacitor is initially charged and then electrically isolated. When the capacitance is altered, potential difference across the capacitor is shifted accordingly. In one embodiment of the present invention, the micro-electromechanical means includes a gear wheel driven by a micro-motor. The gear wheel preferably includes a plurality of teeth protruding along a circumference of the gear wheel. Further, the gear wheel is positioned next to the capacitor and configured to move the teeth into and out of a gap between the capacitor plates. As the teeth is preferably made of dielectric material, the voltage across the capacitor is changed as a tooth enters or leaves the gap. In another embodiment, the teeth may be made of a conducting material.

Abstract: The asynchronous timing generator is comprised of a clock signal generator that generates a master clock signal. The master clock signal is used by a master clock counter to generate a bit clock. The master clock counter divides the master clock signal's frequency down to a lower frequency. Control signal information is extracted from the data stream's slot-framing to control the use of a predefined count value to a variable counter. The variable counter uses this lower frequency clock signal to generate the sub-bit count clock signal and slot bit numbers. These signals are generated in response to the control signals, coupled to the timer, indicating the different fields of the slot used to resynchronize data recovery in the received stream. In a preferred embodiment, the asynchronous timing generator is used in a communications transceiver device to permit resynchronization of received communications data.

Abstract: The present invention comprises a smart retry system for a PCI (peripheral component interconnect) agent in a PCI bus system. The system of the present invention includes an initiator PCI agent and a retry delay register coupled to the initiator PCI agent. The initiator PCI agent is adapted to couple to a PCI bus to communicate with a target PCI agent, via the PCI bus, by initiating a data transaction. The retry delay register is coupled to the PCI agent and the PCI bus. The retry delay register is adapted to receive a delay input via the PCI bus. The delay input describes a latency period of the target PCI agent, wherein the latency period is the amount of the delay. The retry delay register couples the delay input to the initiator PCI agent such that the initiator PCI agent initiates a retry at the expiration of the latency period of the target PCI agent in order to efficiently execute an access to the target PCI agent.

Abstract: A shallow trench isolation structure and method for forming such structure. In one embodiment, the semiconductor device isolating structure of the present invention includes a trench formed into a semiconductor substrate. A cross-section of the trench has a first sidewall sloping inwardly towards the center of a substantially planar bottom surface, and a second sidewall sloping inwardly towards the center of the substantially planar bottom surface. Additionally, a cross section of the trench has a first rounded bottom trench corner at an interface of the first sidewall and the substantially planar bottom surface, and a second rounded bottom trench corner at an interface of the second sidewall and the substantially planar bottom surface.

Abstract: A method of removing an inorganic antireflective coating from a semiconductor substrate and a method of forming an integrated circuit (IC) are provided. In the former method, a sacrificial layer is formed over a semiconductor substrate, the layer being selectively removable from the substrate and compatible with photolithography. An inorganic antireflective coating such as SiON is then formed over the sacrificial layer. Thereafter, the sacrificial layer is removed from the substrate to lift the coating off the substrate. Preferred materials for the sacrificial layer include TiN, tetraethyl orthosilicate-based silicon oxide, spin-on-glass (SOG) such as hydrogen silsesquioxane and methyl silsesquioxane, and porous polymeric materials. In the latter method, a patterned layer of photoresist material is formed over the anitreflective coating.

Abstract: Disclosed is a semiconductor fuse structure having a low power programming threshold and anti-reverse engineering characteristics. The fuse structure includes a substrate having a field oxide region. A polysilicon strip that has an increased dopant concentration region lies over the field oxide region. The fuse structure further includes a silicided metallization layer having first and second regions lying over the polysilicon strip. The first region has a first thickness, and the second region has a second thickness that is less than the first thickness and is positioned substantially over the increased dopant concentration region of the polysilicon strip. Preferably, the first region of the silicided metallization layer has a first side and a second side located on opposite sides of the second region, and the resulting fuse structure is substantially rectangular in shape. Therefore, the semiconductor fuse structure can be programmed by breaking the second region.