Patents Assigned to Walsin Advanced Electronics Ltd.
  • Patent number: 6762118
    Abstract: An integrated circuit package structure having an array of metal pegs connected by printed circuit lines. The package includes a die pad having a die positioned above and an area array distribution of external metal pegs surrounding the die. The package also contains a plurality of internal metal pegs that surround the die. These internal pegs are electrically connected to the bonding pads on the die via conductive medium. The die pad, the die, the conductive medium and the internal pegs are all enclosed by an insulating material. The bottom side of the die pad is exposed while the external metal pegs are electrically connected to various internal metal pegs using printed circuit lines. Furthermore, an electroplate layer is also formed on the end face of each metal peg.
    Type: Grant
    Filed: February 25, 2002
    Date of Patent: July 13, 2004
    Assignee: Walsin Advanced Electronics Ltd.
    Inventors: Wen-Chun Liu, Chien-Hung Lai
  • Publication number: 20030224542
    Abstract: A method for making multi-chip packages and single-chip packages simultaneously and structures thereof are provided. The method comprises the steps of chip-attaching, electrically connecting, encapsulating and electrically testing, all the step are executed on a package substrate with channel holes. The package substrate is selectively cut so as to form multi-chip packages and single-chip packages simultaneously. Each semiconductor package has a plurality of coplanar wiring substrates defined by the channel holes and selective cutting lines. A space between two adjacent wiring substrates is formed from corresponding channel hole and is filled with the isolating encapsulant so as to perform cushioning effect for reducing thermal stress and to improve the structure strength of the package assembly.
    Type: Application
    Filed: May 29, 2002
    Publication date: December 4, 2003
    Applicant: Walsin Advanced Electronics LTD
    Inventor: Wen-Chun Liu
  • Patent number: 6650005
    Abstract: A micro BGA package comprises a die, a wiring board, a plurality of metal bonding wires, a plurality of solder balls, and a package body. The wiring board has a die-attaching surface, a surface-mounting surface with solder balls, and lateral surfaces between the die-attaching surface and the surface-mounting surface. The package body has a fastener covering and extending around the lateral surfaces of the wiring board for improving the bonding strength between wiring board and die and avoiding delamination. Preferably, the wiring board has a plurality of support bars for supporting the wiring board during molding.
    Type: Grant
    Filed: May 29, 2002
    Date of Patent: November 18, 2003
    Assignee: Walsin Advanced Electronics LTD
    Inventors: Chia-Yu Hung, Chun-Jen Su, Chien-Hung Lai
  • Publication number: 20030100174
    Abstract: A process for making a ball grid array semiconductor package comprises the steps of: providing a substrate, dispensing adhesive, attaching dice(s) on the substrate, wire bonding, and implanting solder balls. The adhesive with a predetermined viscosity is coated on the adhesive area of the substrate by dispensing or potting to form a specific pattern for die-attaching. The adhesive is easily controlled to avoid covering the bonding pads on the active surface of the die, so that the yield of the semiconductor package is improved without increasing the extra cost. Also, the reliability of the semiconductor package is increased and the manufacturing cost is reduced.
    Type: Application
    Filed: November 28, 2001
    Publication date: May 29, 2003
    Applicant: Walsin Advanced Electronics LTD
    Inventors: Jansen Chiu, Taurus Chao
  • Patent number: 6521485
    Abstract: A method for manufacturing a wafer level chip size package and the method comprises the steps of: securing wafer to a partly etched lead frame, drilling blind hole and filling conductive material after packaging the lead frame to electrically connect the lead frame and the wafer, thus providing inner electrical connection of the wafer after packaging.
    Type: Grant
    Filed: January 17, 2001
    Date of Patent: February 18, 2003
    Assignee: Walsin Advanced Electronics LTD
    Inventors: Spencer Su, James Lai, Lin Chien-Tsun, Captain Chen, Allen Chen, C.S. Yang, Chang Chao-Chia, Kevin Hsia
  • Publication number: 20030006055
    Abstract: A semiconductor package for fixed surface mounting is disclosed, such as QFN, SON. The package includes a die, an encapsulant body sealing the die, a die pad supporting the die, and a plurality of leads electrically connecting with the die. The surface of die pad exposing outside the encapsulant body has grooves formed for improving the surface mounting to a printed circuit board.
    Type: Application
    Filed: July 5, 2001
    Publication date: January 9, 2003
    Applicant: Walsin Advanced Electronics LTD
    Inventors: Lai Chien-Hung, Lin Chien-Tsun, Chang Chao-Chia
  • Publication number: 20030001250
    Abstract: An optical device with a tape carrier package is provided for low cost packaging and better stability. The optical device comprises: an optical sensor chip having a plurality of electrodes on its sensible surface; a flexible circuit board having an upside surface, an underside surface and a window; a plurality of metal circuits formed on the flexible circuit board and each of them having an inner lead extending into the window for bonding with the corresponding electrode; a base having a recession which is corresponding to the window and located under the underside surface of the flexible circuit board, and having a surrounding dam which extends onto the upside surface of the flexible circuit boars; and a transparent cover fixed attached to the surrounding dam for sealing the optical sensor chip.
    Type: Application
    Filed: June 27, 2001
    Publication date: January 2, 2003
    Applicant: Walsin Advanced Electronics LTD
    Inventors: Lai Chien-Hung, Lin Hsin-Cheng, Peng Bing-Yen
  • Publication number: 20020190366
    Abstract: A micro BGA package comprises a die, a wiring board, a plurality of metal bonding wires, a plurality of solder balls, and a package body. The wiring board has a die-attaching surface, a surface-mounting surface with solder balls, and lateral surfaces between the die-attaching surface and the surface-mounting surface. The package body has a fastener covering and extending around the lateral surfaces of the wiring board for improving the bonding strength between wiring board and die and avoiding delamination. Preferably, the wiring board has a plurality of support bars for supporting the wiring board during molding.
    Type: Application
    Filed: May 29, 2002
    Publication date: December 19, 2002
    Applicant: Walsin Advanced Electronics LTD
    Inventors: Chia-Yu Hung, Chun-Jen Su, Chien-Hung Lai
  • Publication number: 20020182773
    Abstract: A method for bonding inner leads of lead frame to substrate includes the steps of: (a) providing a substrate, the substrate having a plurality of connection pads formed on the electrical bonding surface of the substrate; (b) providing a lead frame with a dam tape adhered on of the inner leads of the lead frame; (c) thermally compressing the inner leads of lead frame onto the substrate, wherein a solder material is formed between the inner end and the corresponding connection pad of the substrate and the solder material is limited by the dam tape during inner lead bonding, so that there is stable electrical and mechanical connection between inner leads and the substrate.
    Type: Application
    Filed: June 4, 2001
    Publication date: December 5, 2002
    Applicant: Walsin Advanced Electronics LTD
    Inventors: Chun-Jen Su, Chien-Hung Lai, Chien-Tsun Lin, Chao-Chia Chang
  • Patent number: 6486564
    Abstract: An improved heat dissipation module for BGA IC's is a thin metal module used for heat dissipation in an encapsulated IC device. It has an annular base with several supports extending from its inner rim upwards to support a top plate. At least one protruding annular ring is provided on the top surface of the top plate. This design can ensure the top plate and a mold match during the capsulation process, avoid the glue overflow problem, and increase its total dissipation area to facilitate heat dissipation.
    Type: Grant
    Filed: August 15, 2001
    Date of Patent: November 26, 2002
    Assignee: Walsin Advanced Electronics Ltd.
    Inventors: Wen-Chun Liu, Yi-Hsiang Pan, Kuo-Yuan Lee
  • Publication number: 20020173074
    Abstract: A method for underfilling bonding gap between flip-chip and circuit substrate is disclosed. A chip is mounted on a circuit substrate with flip-chip configuration. The circuit substrate has a top surface, a bottom surface, and a plurality of via holes. Some of the via holes are formed to be air vents passing through the top surface and the bottom surface. So that the underfill material flows into the gap between flip-chip and circuit substrate until jamming or blocking the said air vents rapidly while underfilling.
    Type: Application
    Filed: May 16, 2001
    Publication date: November 21, 2002
    Applicant: Walsin Advanced Electronics LTD
    Inventors: Su Chun-Jen, Lai Chien-Hung, Lin Chien-Tsun, Chang Chao-Chia
  • Publication number: 20020140113
    Abstract: A semiconductor die package has a lead frame, a die attached to the lead frame and an encapsulant enclosing the lead frame and the die. The distance between the top outside face of the encapsulant and the frame is substantially equal to the distance between the bottom outside face of the encapsulant and the die, and the distance between the top outside face of the encapsulant and the frame is substantially two and half times the distance between the bottom outside face of the encapsulant and the lead frame. Consequently, the different thickness of different encapsulant portions achieves an optimum balance during curing that effectively reduces the deformation of the encapsulant. In addition, the encapsulant can be completely formed by an injection process, and no crack will form in the encapsulant.
    Type: Application
    Filed: March 27, 2001
    Publication date: October 3, 2002
    Applicant: WALSIN ADVANCED ELECTRONICS LTD.
    Inventors: Wen-Chun Liu, Yung-Chao Jen, Ming-Feng Wu
  • Patent number: 6459162
    Abstract: A semiconductor die package has a lead frame, a die attached to the lead frame and an encapsulant enclosing the lead frame and the die. The distance between the top outside face of the encapsulant and the frame is substantially equal to the distance between the bottom outside face of the encapsulant and the die, and the distance between the top outside face of the encapsulant and the frame is substantially two and half times the distance between the bottom outside face of the encapsulant and the lead frame. Consequently, the different thickness of different encapsulant portions achieves an optimum balance during curing that effectively reduces the deformation of the encapsulant. In addition, the encapsulant can be completely formed by an injection process, and no crack will form in the encapsulant.
    Type: Grant
    Filed: March 27, 2001
    Date of Patent: October 1, 2002
    Assignee: Walsin Advanced Electronics Ltd.
    Inventors: Wen-Chun Liu, Yung-Chao Jen, Ming-Feng Wu
  • Patent number: 6459148
    Abstract: A QFN semiconductor package comprises a semiconductor die, a lead frame, bonding wires and a molding compound. The die has an upward topside with a plurality of bonding pads. The lead frame consists of a plurality of inner leads, wherein each inner lead is divided into the front finger portion, the middle protruding portion and the rare connecting portion. The front finger portion is the position of the inner lead to which a bonding wire wire-bonds from the bonding pad of the die. The rare connecting portion is for the electrical out-connection of the package. The middle protruding portion is at height level higher than the front finger portion and the rare connecting portion. The bonding wires electrically connect the bonding pads of the die with the front finger portions of inner leads by means of wire-bonding.
    Type: Grant
    Filed: November 13, 2000
    Date of Patent: October 1, 2002
    Assignee: Walsin Advanced Electronics LTD
    Inventors: Su Chun-Jen, Lin Chien-Tsun, Chang Chao-Chia, Su Yu-Hsien, Tseng Ming-Hui
  • Patent number: 6437429
    Abstract: A semiconductor package is disclosed, such as QFN, SON. The semiconductor package includes a die, a package body for protection of a die, and a plurality of leads. A metal pad formed by some partial downside surface of each lead is located on a downside surface of the package body with coplanarity. Each lead has a cutting surface exposed on a corresponding lateral surface of the package body. The cutting surface has an interval with the plane of forming the metal pads by means of selectively self-etching the leads or stamping to bend the leads in order to avoid forming a cutting sharp edge in the brim of the metal pad after cutting.
    Type: Grant
    Filed: May 11, 2001
    Date of Patent: August 20, 2002
    Assignee: Walsin Advanced Electronics Ltd
    Inventors: Chun-Jen Su, Chien-Hung Lai, Chien-Tsun Lin, Chao-Chia Chang, Yu-Hsien Su, Ming-Hui Tseng
  • Publication number: 20020094601
    Abstract: A method for manufacturing a wafer level chip size package and the method comprises the steps of: securing wafer to a partly etched lead frame, drilling blind hole and filling conductive material after packaging the lead frame to electrically connect the lead frame and the wafer, thus providing inner electrical connection of the wafer after packaging.
    Type: Application
    Filed: January 17, 2001
    Publication date: July 18, 2002
    Applicant: Walsin Advanced Electronics LTD
    Inventors: Spencer Su, James Lai, Lin Chien-Tsun, Captain Chen, Allen Chen, C.S. Yang, Chang Chao-Chia, Kevin Hsia
  • Publication number: 20020094683
    Abstract: A method for manufacturing a chip size package comprises the steps of: providing a chip having a plurality of bonding pads on its active surface; providing a metal board consisting of the upper layer and the lower layer, wherein, a chip carrier, corresponding to said least chip, being formed on the surface of the upper layer of the said metal board; selectively etching the upper layer of the metal board to form a plurality of redistribution conductive circuits supported by the lower layer of the metal board; securing the chip to the chip carrier of the upper layer of the metal board, and electrically connecting to the conductive circuits; providing a package body (or underfill) in between the chip and the upper layer of the metal board; and, removing the lower layer of the metal board. Thus, package manufactured by applying present invention has ability of securing more electrodes and thinner thickness.
    Type: Application
    Filed: January 17, 2001
    Publication date: July 18, 2002
    Applicant: Walsin Advanced Electronics LTD
    Inventors: Spencer Su, James Lai, Lin Chien-Tsun, Captain Chen, Allen Chen, C.S. Yang, Chang Chao-Chia, Kevin Hsia
  • Patent number: 6385049
    Abstract: A multi-board BGA package comprises a chip, a plurality of circuit boards, a plurality of metal bonding wires, a plurality of solder balls, and a package body. The circuit boards are formed on a same plane. Between adjacent circuit boards there is a galley for passing through metal bonding wires to connect chip with circuit board and molding package body easily. The plurality of circuit boards together hold the chip so as to reduce thermal stress caused by CTE mismatch.
    Type: Grant
    Filed: July 5, 2001
    Date of Patent: May 7, 2002
    Assignee: Walsin Advanced Electronics LTD
    Inventors: Hung Chia-Yu, Su Chun-Jen, Lai Chien-Hung
  • Patent number: 6380624
    Abstract: A stacked integrated circuit structure, in which main package bodies of a plurality of integrated circuits are stacked on each other. Connections between leads of the stacked integrated circuits are made by means of a stacking substrate. Therein, each of two surfaces of the stacking substrate has a plurality of terminals electrically connected to corresponding terminals. The stacking substrate includes a plurality of through vias as well, which connect to the corresponding terminals of the two surfaces. For two stacked integrated circuits, a hole can be defined in the stacking substrate, which housed the main package body of one of the two stacked integrated circuits, or by means of a plurality of separated substrates arranged around the perimeter of the main package body of one of the two stacked integrated circuits, so that the thickness of the stacked integrated circuits can be reduced.
    Type: Grant
    Filed: October 10, 2000
    Date of Patent: April 30, 2002
    Assignee: Walsin Advanced Electronics Ltd.
    Inventor: Chia-Yu Hung
  • Patent number: 6380062
    Abstract: A method for forming ball grid array package. The ball grid array package has internal trace lines and exposed metal pegs. A metal substrate is provided. Electroplated layers are formed over metal peg regions and a die pad region on the surface of the metal substrate. A layer of substrate material at the top surface of the metal substrate is removed so that thickness of the metal substrate is reduced. Hence, trace lines, die pad and internal metal pegs are formed. A die is attached to the die pad and electrical connections from the die to the internal metal pegs are made. A molding process is carried out to enclose the die, the die pad and the internal metal pegs on one side of the metal substrate with plastic material. The lower surface of the metal substrate is etched to form external metal pegs while exposing the mold material and the bottom surface of the die pad. The internal metal pegs and the external metal pegs are interconnected via the trace lines.
    Type: Grant
    Filed: March 9, 2001
    Date of Patent: April 30, 2002
    Assignee: Walsin Advanced Electronics Ltd.
    Inventor: Wen-Chun Liu