Patents Assigned to Wandel & Goltermann
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Patent number: 5590116Abstract: A plurality of digital transmission network analyzers are arranged to analyze and compare the appearance of a data packet on the plurality of ports of a network. Each analyzer has its own internal clock for time stamping of data packets in addition to other internal timing purposes. In order to synchronize the time stamping of the packet as it appears to each analyzer at a each different port, the clock outputs of the several analyzers are connected together; and a controlling CPU commands one of the analyzers to supply the master clock to the others. That master analyzer then commands the other analyzers to disable or disconnect their own clocks, thereby all of the analyzers involved in a given test are under timing control of the clock of the master analyzer. Packet headers and time stamps are transmitted between analyzers for comparison, analysis, and reporting to the controlling CPU.Type: GrantFiled: February 9, 1995Date of Patent: December 31, 1996Assignee: Wandel & Goltermann Technologies, Inc.Inventor: Jing Zhang
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Patent number: 5541862Abstract: In order to test the functional and parametric characteristics of a unit without overloading a host computer, the host computer downloads a testing program to a plurality of digital signal processor modules which do all of the functional environmental emulation data generation and analysis of the data received from the unit under test. A reconfigurable application interface module is also programmed at the same time as the digital signal processor modules and is thus configured to accept basic emulation data generated by the digital signal processor modules and convert those data to the data environment that the unit under test is expected to experience in use. The application interface module also converts the data received from the unit under test into a format that the digital signal processor modules can analyze, the results of which analysis are made available to the host computer.Type: GrantFiled: April 28, 1994Date of Patent: July 30, 1996Assignee: Wandel & Goltermann ATE Systems Ltd.Inventors: Randall G. Bright, Peter H. Jansen, Vijay K. Nagaraj
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Patent number: 5535193Abstract: A plurality of digital transmission network analyzers are arranged to analyze and compare the appearance of a data packet on the plurality of ports of a network. Each analyzer has its own internal clock for time stamping of data packets in addition to other internal timing purposes. In order to synchronize the time stamping of the packet as it appears to each analyzer at a each different port, the clock outputs of the several analyzers are connected together; and a controlling CPU commands one of the analyzers to supply the master clock to the others. That master analyzer then commands the other analyzers to disable or disconnect their own clocks, thereby all of the analyzers involved in a given test are under timing control of the clock of the master analyzer. Packet headers and time stamps are transmitted between analyzers for comparison, analysis, and reporting to the controlling CPU.Type: GrantFiled: February 9, 1995Date of Patent: July 9, 1996Assignee: Wandel & Goltermann Technologies, Inc.Inventors: Jing Zhang, Kenneth R. Gramley
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Patent number: 5519645Abstract: A method for data or measured value averaging and compression for measuring instruments, particularly for spectral analyzers, in which in successive measuring runs with respect to measuring intervals minimum and maximum values and their precise position are determined and used for averaging taking account of the values determined at the same locations during further measuring runs. By means of a measured value or data determination dependent on the position of the fixed minimum and maximum values, it is ensured that an effective noise averaging and a reliable detection of narrow pulses are made possible.Type: GrantFiled: November 19, 1993Date of Patent: May 21, 1996Assignee: Wandel & Goltermann GmbH & Co. Elektronische MesstechnikInventor: Rolf Bohley
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Patent number: 5446621Abstract: On a printed circuit board or module card (20) of a standard size for a particular type of system, one or more different, smaller circuit cards or sub-modules (50) can be selectively mounted on the module card so as to utilize a maximum of its area. The module card has openings or holes (30) therein so as to provide component clearance and thus prevent the thickness of the module card from reducing the maximum permissible height of the components that can be mounted on the sub-modules. In order to minimize the amount of module card area devoted to interconnecting to the sub-modules, the sub-modules plug into the module card as the sub-module is moved in a direction perpendicular to the plane of the module card rather than in a direction parallel to the plane of the module card. Circuit wiring and switching (FIG.Type: GrantFiled: April 28, 1994Date of Patent: August 29, 1995Assignee: Wandel & Goltermann ATE Systems Ltd.Inventors: Peter H. Jansen, Viral K. H. Chokshi
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Patent number: 5444806Abstract: An adaptor (1) can be releasably connected to a fixed plug portion (13 or 21). The fixed plug portion is, with that, for example a component in a measuring device for taking measurements on differing optical fibers. The adaptor is provided with a sleeve (3) in which various transferable plug portions can be temporarily inserted. The sleeve has an axially parallel slot (6) for accommodating a rotational security device on an initial category of fixed plug portions (21). Additionally, the sleeve also has at least one further recess (4, 4, 5) on its outer casing for accommodation of the rotational security device (19, 19', 20) of a second category of fixed plug portions (13). In this way, an interface between adaptor (1) and fixed plug portion (13, 21) is created, which indeed enables combination with an adaptor equipped in the same way, although an adaptor without an additional recess is only able to be placed on one of the two categories.Type: GrantFiled: September 23, 1994Date of Patent: August 22, 1995Assignees: Diamond SA, Wandel & Goltermann GmbH & Co.Inventors: Silverio de Marchi, Thomas Muhl
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Patent number: 5430746Abstract: A method of and a circuit arrangement for detecting synchronization of two word sequences between a measurement signal and a reference signal. The signals are applied to an exclusive OR-gate comparator whose output produces an error signal which is compared with an error signal shifted by one period. This comparison is effected by an exclusive OR-gate and in the case of coincidence, indicating that the measurement and reference signals are phase-shifted, a new synchronization is enabled. The output of the exclusive OR-gate is an error signal which is time-shifted in a shift register and multiplexer so that the time shifted bit sequence is compared with the bit sequence of the first error signal in a second exclusive OR-gate which is connected to an AND-gate for detecting coincidence and generating a further synchronization signal which is processed through counters, another AND-gate and a flip-flop to produce the synchronization signal which is applied to the reference pattern generated.Type: GrantFiled: November 8, 1993Date of Patent: July 4, 1995Assignee: Wandel & Goltermann GmbH & Co. Elektronische MesstechnikInventor: Gunter Renz
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Patent number: 5307031Abstract: An adjustable impedance-correcting delay line adapted to form a standard line for providing an adjustable group delay time for measurement purposes or the like in which a plurality of different delay networks including coaxial segments of different lengths with or without damping compensating amplifiers can be selectively connected in the cascade or shunted. A bridge circuit can be provided with fundamental damping and delay time for bridging with the standard delay line where difference measurements are of interest.Type: GrantFiled: September 2, 1992Date of Patent: April 26, 1994Assignee: Wandel & Goltermann GmbH & Co. Elektronische MesstechnikInventor: Rudolf Dick
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Patent number: 5166514Abstract: An optical plug connector for an optical measuring device between an internal light waveguide optical fiber and an external light waveguide optical fiber maintains a distance d between the ends of the fibers which is greater than the coherence length of the light to be transmitted through the coupling. In this manner, in spite of the presence of the air gap, interference phenomena are avoided.Type: GrantFiled: March 8, 1991Date of Patent: November 24, 1992Assignee: Wandel & Goltermann GmbH & Co.Inventor: Wolfgang Schmid
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Patent number: 5163057Abstract: A method of and a circuit for detecting a cell loss and/or a cell insertion in cell structured signals traversing a cell oriented transmission module. A bit comparison is effected between a test signal sequence formed as a cell header and an information signal sequence filling the remainder of the cell and the bit comparison can detect the leading or lagging by a bit. When this bit comparison is, in addition, continuous; a cell loss or cell insertion is determined.Type: GrantFiled: April 17, 1990Date of Patent: November 10, 1992Assignee: Wandel & Goltermann GmbH & Co.Inventor: Wolfgang Grupp
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Patent number: 5120943Abstract: An electronic measuring instrument capable of receiving control signals for setting same, is set by a bar-code reader through an encoder and processor utilizing setting instructions printed in bar-code form, so that the instruction set is accurately transferred to the microprocessor generating the control signals.Type: GrantFiled: June 18, 1990Date of Patent: June 9, 1992Assignee: Wandel & Goltermann GmbH & Co.Inventor: Reiner Benz
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Patent number: 4996699Abstract: A frequency divider circuit, especially for use in frequency synthesizers, in which the frequency divider is provided with whole-number division factors, permits intergrator, differentiator and/or phase accumulations to be used to generate the successive values of the division factor which average, over time to allow fractional frequency division.Type: GrantFiled: July 11, 1989Date of Patent: February 26, 1991Assignee: Wandel & Goltermann GmbH & Co.Inventor: Georg Rudolph
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Patent number: 4986621Abstract: An optical head having a photoelectric converter at one end and a socket for a light guide plug at the opposite end, has a spring loaded apertured diaphragm adapted to press lightly against the front end of the plug when it is inserted into the socket. The diaphragm has a cylindrical aperture at its side turned toward the plug and an opening defined by a frustoconical surface widening in the direction of the converter. This surface and the rear wall of the diaphragm can be provided with a light absorbent coating or the surface can be reflective and the rear wall provided with a light absorbent coating.Type: GrantFiled: August 15, 1989Date of Patent: January 22, 1991Assignee: Wandel & Goltermann GmbH & Co.Inventor: Gustav Gamerdinger
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Patent number: 4884180Abstract: A dc converter for supplying an electronic device in which a feed voltage is summed with an additional voltage generated by rectification and wherein pulse-width control is provided at the primary side of the converter transformer. According to the invention, the additional voltage is generated by rectification in the same manner as the main output voltage is generated, i.e. the rectifier circuit outputting the additional voltage is similar to that outputting the output voltage.Type: GrantFiled: November 18, 1988Date of Patent: November 28, 1989Assignee: Wandel & Goltermann GmbH & Co.Inventor: Gunther Hoffmann
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Patent number: 4733395Abstract: For imitating periodic signals occurring in digital transmission systems during some operating conditions in view of the multiplex structure a word generator is proposed which includes a read-only memory from which during a test signal cycle only 4116 permutations are successively read out of a total of 65,536 possible word sizes and permutations of e.g. a 16-bit word. The remaining 61,420 permutations are generated by shifting bit-by-bit the entire packet of continuous signals so that in case of a fixed 16 bit pattern the packet starts at a different bit position during each successive cycle and after 16 cycles all 16 bit positions occur as begin state. The shift is caused by a framing bit sequence which determines the test signal cycle and whose length is aliquant to n=16.Type: GrantFiled: April 15, 1986Date of Patent: March 22, 1988Assignee: Wandel & Goltermann GmbH & Co.Inventors: Hans-Joachim Gelbrich, Erwin Lehmann
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Patent number: 4514705Abstract: A variable-frequency main oscillator of digitally tunable high output frequency f.sub.A is controlled by the integrated output voltage of a phase discriminator receiving on the one hand a relatively low comparison frequency and on the other hand a matching feedback frequency stepped down from output frequency f.sub.A by frequency division or by heterodyning with an auxiliary frequency f.sub.H of the same order of magnitude from an ancillary oscillator, a difference frequency f.sub.D =f.sub.A -f.sub.H is fed to a frequency discriminator delivering a corrective voltage, independent of that emitted by the phase discriminator through a filter network, to the control input of the main oscillator. A pair of frequency selectors varying the feedback frequency and/or the comparison frequency enable the output frequency f.sub.A to be adjusted in coarse and fine tuning steps, the coarse adjustments being also applied to the auxiliary frequency f.sub.H to limit the excursions of the difference frequency f.sub.D.Type: GrantFiled: December 8, 1981Date of Patent: April 30, 1985Assignee: Wandel & Goltermann GmbH & Co. KGInventor: Peter Harzer
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Patent number: 4428076Abstract: In order to evaluate the fidelity of a transmission line or other test object, a pseudorandom bit pattern is fed to the input end of that test object and is compared bit by bit with the pattern exiting at its output end. Since independent transmission errors are considered particularly relevant for this evaluation, in contrast to consequential errors following an initial error within a predetermined number of bit cycles, an error pulse emitted by the bit comparator causes the blocking of further error pulses for a selected time interval. The blocking may be effected by a retriggerable monoflop of adjustable off-normal period or by a presettable down counter.Type: GrantFiled: December 14, 1981Date of Patent: January 24, 1984Assignee: Wandel & Goltermann GmbH & Co.Inventor: Eberhard Schuon
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Patent number: 4370617Abstract: In order to extract from a digital signal a train of sync pulses faithfully reproducing any phase jitter to which that signal is subjected, a pulse generator with a cadence equal to the reciprocal of the mean bit period is interrupted and restarted by a pulse shaper such as a monoflop in response to each incoming "1" bit. The pulse generator may comprise a second monoflop, triggerable by the first monoflop and provided with a feedback loop including a third monoflop which is inhibited by the first one in the presence of a "1" bit, or a free-running oscillator working into a frequency divider in the form of a pulse counter which is reset by the pulse shaper while the latter inhibits the oscillator.Type: GrantFiled: August 15, 1980Date of Patent: January 25, 1983Assignee: Wandel & Goltermann GmbH & Co.Inventor: Dieter Brandt
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Patent number: 4325024Abstract: An incoming a-c signal, whose amplitude is to be measured, successively passes through several decadic attenuator stages settable by respective cascaded decadic stages of a reversible counter. The attenuated signal is rectified and its voltage, or the RMS value thereof obtained from a squarer, gives rise to a calibration current, opposed by a constant reference current, for charging a capacitor of a current/frequency converter with a resulting current corresponding to their difference. Two threshold detectors in that converter, responding to a capacitor charge of either polarity beyond a predetermined limit, trigger a monoflop which fully or partly discharges the capacitor and steps the counter forward or backward as determined by a polarity sensor connected across the capacitor. A retriggerable second monoflop, responsive to the trailing edge of each stepping pulse, enables the second-lowest counter stage to be stepped out of turn when these pulses follow one another at high rate.Type: GrantFiled: July 11, 1980Date of Patent: April 13, 1982Assignee: Wandel & Goltermann GmbH & Co.Inventors: Karl-Heinz Heidenreich, Helmut Wachtelborn
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Patent number: 4287469Abstract: A test object, such as a communication path used for data transmission, is examined by applying to its input a measuring signal M consisting of several simultaneously or sequentially generated test frequencies which may be harmonically interrelated, extracting from the output of the test object a distorted version E of the measuring signal, locally generating a compensation signal K with frequency components matching respective test frequencies, and subtracting the two signals E and K from each other to obtain a residual signal R=E-K. The compensation signal K is produced by one or more local oscillators and as many frequency converters under the control of regenerating circuitry which locks each of its components in phase and amplitude to the corresponding test frequency. Regeneration takes place in a different frequency range to which the residual signal R is transposed and from which the compensation signal K is retransposed with the aid of a locally generated carrier.Type: GrantFiled: June 12, 1979Date of Patent: September 1, 1981Assignee: Wandel & GoltermannInventor: Peter Harzer