Abstract: An external disk drive assembly includes a molded plastic base; a sheet metal frame latched to the base; a power supply housing, a disk drive housing, and a disk drive controller card affixed to the frame; a forced air cooling fan mounted in a molded receptacle on the base; a cover removably secured to the base; and thin sheet metal plates inside the cover and base to provide electrical grounding and EMI and RFI shielding. The receptacle has oppositely-facing U-shaped walls matching the outer configuration of the fan housing. The sheet metal base has a retaining flange for extending over the fan housing. During assembly, the fan housing is simply dropped into the receptacle so the outer walls of the receptacle locate the fan housing relative to the base and frame. The frame is then latched to the base which locates the retaining flange over the top of the fan housing.

Abstract: A circuit for providing precise delays includes a phase-locked loop driven by a reference frequency source such as a crystal oscillator and including a variable delay circuit. The output of the oscillator is applied to the delay circuit and the non-delayed and delayed signals are compared in a phase comparator. An error signal representative of phase error is developed and applied to vary the amount of delay until the phase error is eliminated. A precise delay referenced to the oscillator frequency is therefore achieved.

Abstract: The invention provides a method and architecture for reading data from a track on a data disk with no latency in initiation of the data transfer due to sector alignment. Sector identification bytes are compared for track identification while sector number is written for storage in a table lookup with a buffer address for storage of the data.

Abstract: A pick and place machine having an electronic component feed device wherein the feed device feeds electronic components to various pick up locations with such high positional accurracy that alignment jaws on the pick up head are not necessary. Elevated tracks run parallel to a printed circuit board conveyor belt. These elevated tracks support an arm which in turn supports the electronic component pick up head. The feed device is positioned under the elevated tracks so that an operator can replenish the supply of electronic components in the feed device without reaching over the tract.

Abstract: A Schmitt trigger having first and second complementary switches is biased to exhibit hysteresis, switching at a high threshold level when the input signal increases, and switching at a low threshold level when the input decreases. The source driver for the Schmitt trigger is coupled to the input of at least one of the complementary switches by transition circuitry, such that the signal level representing one binary value is shifted closer to the level of the power supply voltage corresponding to such binary value without changing the logical value of the signal from the source driver. In one embodiment, the first inverter is a MOS transistor, the threshold level of which is set by a bias voltage applied to the gate of another MOS transistor. The second inverter is a pair of complementary CMOS transistors. In another embodiment, the first inverter also comprises a pair of complementary CMOS transistors. The threshold level is set by selecting the W/L ratio of the CMOS transistors of the first inverter.

Abstract: The invention provides a circuit for selecting a first clock, disabling a second or additional clocks and positively enabling the selected first clock only after the second or additional clocks no longer provide signal to the circuit.

Abstract: An integrated circuit chip is fabricated with an operational active device and a nearly-identical, exemplary active device. The exemplary device is connected in series with a current reference element so that current flow through the reference element will be substantially duplicated in the exemplary device. A difference amplifier senses the output voltage of the exemplary device; compares it to a provided reference voltage; and generates a gate biasing level at the gate of the exemplary device to force the output voltage of the exemplary device substantially equal to the reference voltage. The biasing level at the gate of the exemplary device is duplicated at the gate of the operational device thereby creating a condition wherein the output current of the operational device will be a substantially precise replica of the current flow through the reference element when the reference voltage is duplicated across the output of the operational device.

Abstract: A phase locked loop system having a non-linear voltage controlled oscillator (VCO) is provided with a variable gain charge pump. The charge pump supplies a pump current to an integrating network which transforms the pump current into a frequency-modulating input voltage. The frequency-modulating input voltage is applied to an input of the VCO. The frequency-modulating input voltage is also coupled to a gain control input of the variable gain charge pump so that the magnitude of the pump current will be a function of the absolute value of the frequency-modulating voltage.A substantially constant loop gain may be obtained in the phase locked loop system by arranging the gain function of the variable gain charge pump in counterposed relation to the slope of a VCO transfer function defining the nonlinear relation between the frequency-modulating input voltage of the VCO and the output frequency of the VCO.

Abstract: A circuit is provided for realizing multiple precision resistor elements on an integrated circuit by sensing a reference resistor. The circuit contains a first current source which passes a first current through a reference resistor located either on or off of the integrated circuit to generate a reference voltage. The reference voltage is applied to the inverting input of a precision high gain operational amplifier. A second current source is connected to the drain of a first MOS transistor operating in its ohmic region. The second current source is also connected to the non-inverting input of the high gain operational amplifier. The output of the operational amplifier is electrically connected to the gate of the first and second MOS transistors. In operation, a precision resistance is developed across the second MOS transistor which is equal to or some determinable multiple of the resistance of the reference precision resistor located on or off chip.

Abstract: The invention provides a circuit for use with a standard bidirectional databus having an active current device providing a first logic level in combination with a selectably jumpered passive resistance device providing a second logic level, the active element responsive to an enable signal whereby tristating the bus write drivers and reading the bus will sense a configuration determined by selection of the jumper.

Abstract: A Schmitt trigger circuit with independently biased threshold sections includes a drive disabling switch for blocking one of the threshold sections from driving a logic node toward a predetermined logic state. The drive disabling switch is selectively operated so that unidirectional sensitivity to the crossing of a threshold level belonging to its corresponding one threshold section is obtained.

Abstract: An integrated circuit chip mounting and packaging assembly is described. The assembly comprises a spreader having one or more chips centrally mounted thereon. A plurality of leads are disposed outward of the integrated circuit chip on the same side of the spreader as the chip. When fully assembled, the spreader is positioned, chip side down, over a cavity in a printed circuit board-like substrate. The cavity is ringed with connectors which contact the spreader leads and appropriately connect the integrated circuit chip to other electronic components mounted on the substrate.

Abstract: Disclosed is an improved logic circuit employing dynamic CMOS logic and having alternating logic employing first and second conductivity type transistors, respectively, separated by clocked inverters. The circuit employs a single clock signal to synchronize the dynamic logic operations of said logic gates and, along with a second, complement clock signal, said clocked inverters. Precharge transistors of each conductivity type are slowed slightly with respect to logic transistors, and the complement clock signal is delayed slightly with respect to the clock signal, thereby providing racefree logic operations. An implementation in a PLA is disclosed employing two logic planes for implementing arbitrary logic equations on input logic signals. The first logic plane and second logic plane are evaluated on separate phases of a complement clock signal and are separted by a clocked latch/inverter for providing correct logic evaluation between the logic planes.

Abstract: A method and apparatus are described for precisely centering the leads of surface mountable electronic components on the pads of a printed circuit board. The method includes coating the pads with solder, placing the leads of the components on the solder coated pads, melting the solder and vibrating the leads relative to the pads while the solder is molten, so that the surface tension of the molten solder centers the leads on the pads. The molten solder is then cooled until it resolidifies.

Abstract: A pick and place machine having an electronic component feed device is described. The feed device feeds electronic components to various pick up locations with such high positional accuracy that alignment jaws on the pick up head are not necessary. Elevated tracks run parallel to a printed circuit board conveyor belt. These elevated tracks support an arm which in turn supports the electronic component pick up head. The feed device is positioned under the elevated tracks so that an operator can replenish the supply of electronic components in the feed device without reaching over the tract.

Abstract: An integrated system for use in a disk drive system for the implementation of write precompensation for recording of data and read window margining for accelerated testing of the disk drive. Both functions are provided by a common delay-line circuitry. The output of the delay line circuit is applied to both window shifting and write precompensation. An on-board read detection error analysis can be performed after installation of the drive in a computer system in its final configuration. Actual read error tolerance based on the overall system in its actual operating condition can thus be obtained. Enhanced data recovery techniques are also facilitated.

Abstract: A digital data separator operates to separate data pulses from clock pulses in MFM encoded signals read from a magnetic disk system. The data separator includes a digital phase-locked loop system incorporating a variable length shift register which functions as a variable oscillator and programmed state machines which control the operation of the shift register and provides filtering functions. The state machines filter high frequency noise components from the incoming data signals and enables the system to accurately track frequency variations in the data stream while providing high tolerance to high frequency noise.

Abstract: A flip-flop circuit is provided for use in a phase-locked loop circuit, the flip-flop having two signal paths for selecting a VCO output during velocity lock and phase lock. The two signal paths comprise identical environments and therefore eliminate the phase step exhibited by prior art designs in shifting between velocity lock and phase lock. The circuit is also useful in any application where a clock to output delay of a flip-flop connected for normal operation, must have its propagation delay matched to a circuit which simply delays a signal by the same amount.

Abstract: A charge pump implemented in a CMOS monolithic circuit provides a precise output charging current source or current sink with fast switching characteristics. Each of two CMOS output transistors is connected via a transmission gate to a transistor having a constant current flow through it. An MOS capacitor is connected to the gates of the constant current transistors. When a transmission gate is closed, the respective output transistor is coupled to the constant current transistor in a current mirror configuration. The output transistor is quickly switched on to cause a step change in output current.