Abstract: A field effect transistor device formed on an integrated circuit chip substrate and driven by the on-chip voltages having a well region formed in the substrate, and source and drain regions one of which is formed in the well region. The well region has a lower doping concentration than the source and drain regions and is of the same conductivity type. The well region provides a reduced electric field gradient at the source/substrate or drain/substrate junction and significantly increases the breakdown resistance of the device to DC voltages higher than the on-chip voltages. An input/output protection circuit employing the field effect transistor coupled in series between an integrated circuit output pad and the active devices on the chip providing ability to withstand coupling of the pad to a relatively high DC voltages.

Abstract: An automatic monitor sensing graphics controller for use with a computer and a display monitor. The display monitor has a specific capability. The controller, mounted within the computer, comprises a plurality of signal lines, a buffer device connected to both the signal lines and the computer, a connector device connected to both the signal lines and the display monitor, and an automatic monitor sensing unit connected to the signal lines for sensing and determining the capability of the display monitor.

Abstract: An electrostatic discharge protection circuit for an integrated circuit employing a segmented field effect buffer transistor between the input/output pad and the active devices on the integrated cicuit. An extended resistive structure is configured in series with the segmented buffer transistor and the input/output electrical contact pad. The extended resistive structure is integrally formed with the individual segments of the buffer FET. The resistive structure may be implemented as an extended n well structure adjacent the FET segments. In a first resistance mode during normal circuit operations, the extended resistive structure has a low resistance value and introduces virtually no additional load to the input/output buffer circuitry. In a second mode of operation during ESD discharge, the resistive structure has a second significantly higher resistance which reduces current values during the ESD event thereby protecting the buffer circuit.

Abstract: A polymer film interconnect forms an electrical interconnect between a first pattern of electrical conductors on a first electrical component and a second pattern of electrical conductors on a second electrical component. The polymer film interconnect includes a thin, flexible, self-supporting dielectric polymeric film having a pattern of spaced apart thru-holes containing separate quantities of an electrically conductive bonding material capable of heat bonding to the first electrical conductors adjacent the first surface of the film and to the second conductors adjacent the second surface of the film. This provides a plurality of discrete electrically isolated conductive paths from the first pattern of electrical conductors through the film to the second pattern of electrical conductors on the opposite side of the film.

Abstract: A high frequency clock signal synthesizer circuit employs a single fixed reference clock signal to generate one or more variable frequency clock signals. A phase comparator and a variable count counter generate a control signal from the reference clock and circuit output and provide it to a voltage controlled oscillator. High frequency stability of the voltage controlled oscillator is provided by a ring oscillator with a control signal response which is linear even at high frequencies. The ring oscillator employs an odd number of inverting delay stages coupled in series in a ring configuration, each delay stage having an input, an output, an inverter coupled to the input and a controllable current source buffering the switching transistors of the inverter from the output. A bias circuit controls the current of the current source and thereby controls the delay of each delay stage and thus the frequency of the ring oscillator.

Abstract: A phase locked loop system having a non-linear voltage controlled oscillator (VCO) is provided with a variable gain charge pump. The charge pump supplies a pump current to an integrating network which transforms the pump current into a frequency-modulating input voltage. The frequency-modulating input voltage is applied to an input of the VCO. The frequency-modulating input voltage is also coupled to a gain control input of the variable gain charge pump so that the magnitude of the pump current will be a function of the absolute value of the frequency-modulating voltage.A substantially constant loop gain may be obtained in the phase locked loop system by arranging the gain function of the variable gain charge pump in counterposed relation to the slope of a VCO transfer function defining the nonlinear relation between the frequency-modulating input voltage of the VCO and the output frequency of the VCO.

Abstract: A circuit is provided for control and data transfer between a standard data storage device interface and one of a choice of several host computers. Parallel transition memories in conjunction with a buffer memory under common control of a buffer manager increase the transfer efficiency between the data storage unit and the host computer. Selectable register banks provide interface compatibility with multiple host computers for implementation of the invention.

Abstract: The combination of a rotating data storage disk and a pulse detector for generating an output pulse synchronized with clock pulses. The detector has a beginning of input pulse sensor for pulses derived from the disk, a timing circuit responsive to the sensing of the beginning of one of the input pulses for generating an output pulse of substantially constant pulse width and synchronized with clock pulses. A pulse presence sensor inhibits the timing circuit from generating another output pulse for any such detected input pulse, until after the sensed input pulse terminates.

Abstract: A comparator which is used to compare two analog voltages and provide a single ended output comprises three CMOS differential amplifiers. The use of three differential amplifiers provides improved matching of input capacitance, and a reduction in propagation delay over prior art use of a single differential amplifier. The comparator may be adopted for use in certain CMOS processes to extend the maximum operating voltage by limiting the internal node voltages otherwise subject to damage from impact ionization. An alternative embodiment is disclosed for comparing two analog voltages that are outside the power supply voltage range.

Abstract: Access to a buffer memory is provided by a controller architecture and method employing an arbiter state machine for control of data transfer between multiple external peripheral devices and the dynamic random access memory buffer. Data transfer channels for each peripheral device include a first-in, first-out sub-buffer. Each data transfer channel communicates transfer requests to the arbiter when data is present in the FIFO. When data transfer to or from the FIFO nears an overrun or underrun condition, the data channel issues an urgent request to the arbiter state machine. The arbiter state machine prioritizes data transfer requests for enabling transfer between the buffer memory and data channels. Once a data transfer is in process it continues uninterrupted unless an urgent request is received from another device. In addition, the invention includes a refresh circuit for the dynamic RAM incorporating similar request and urgent request signals provided to the arbiter state machine for resolution.

Abstract: A plated plastic castellated interconnect comprises a substrate made from a molded polymeric material and having top and bottom surfaces with a plurality of separate mutually spaced apart castellations integrally molded to the substrate and projecting from the bottom surface of the substrate. A plurality of separate spaced apart recessed regions may be molded in an edge of the substrate and aligned with the castellations. A plurality of metal conductors are plated to the substrate as separate conductive circuit traces, so that each circuit trace extends continuously from the top surface, along the surface of a corresponding recess and to a common plane on a respective castellation at the bottom of the substrate. The plated metal castellations are arranged for soldering or gluing to contacts on a printed circuit board for electrical connection to an electrical component such as an IC chip connected to the circuit traces on the substrate.

Abstract: A circuit embodied in a single integrated circuit, which is connected through an asynchronous communication bus to a primary bus master and a permanent bus slave, cooperates with the master and slave in a multi-master transfer of a block of data having a leading sub-block of data followed by a trailing sub-block of data. The slave operates in accord with request/acknowledge protocol by applying at least one request signal to a conductor of the bus and responding to each of a consecutive sequence of acknowledge signals on a second conductor of the bus from the master in communication of each of a consecutive sequence of concurrently-applied parallel-by-bit data carried by multiple other conductors that define a data bus portion of the communication bus.

Abstract: A one-shot state machine circuit, preferably implemented exclusively with CMOS transistors, converts long state changes to pulses or one-shots with a fixed duration. A short signal stage to eliminate responses to short glitch signals and a majority gate inside an input state provide the one-shots in response to valid input signals. An output stage mediates conflicting signals from the short signal stage and the majority gate.

Abstract: An electrostatic discharge protection circuit employing an extended resistive structure having bimodal resistance characteristics in series with an input/output buffer circuit and an input/output electrical contact pad on an integrated circuit. The extended resistive structure is integrally formed with the device or devices in the buffer circuit most susceptible to damage due to ESD breakdown effects. In a first resistance mode during normal circuit operations, the resistor has a low resistance value and introduces virtually no additional load to the input/output buffer circuitry. In a second mode of operation during ESD discharge, the resistor has a second significantly higher resistance which reduces current values during the ESD event thereby protecting the buffer circuit. Thick oxide snap-back device is also employed to provide a parallel ESD discharge path with low power dissipation.

Abstract: A stability-compensated, integrated-circuit operational amplifier has an open-loop gain versus frequency characteristic which provides stable and accurate closed-loop operation in numerous overall circuits including a CMOS circuit for producing a precision current as a reference to a digital-to-analog converter. The operational amplifier comprises an inverting node and a non-inverting node, and CMOS circuitry defining two differential amplifiers. Each differential amplifier is connected to the inverting node and the non-inverting node. The first differential amplifier has an output node, and produces on the output node an output potential that defines an output signal having a magnitude that is a function of the magnitude of the difference between a first potential at the inverting node and a second potential at the non-inverting node. The second differential amplifier is also connected to the inverting node and the non-inverting node. The second differential amplifier produces a compensation signal.

Abstract: The invention provides a method and circuit for control of intelligent or integrated disk drives whereby a single computer address port may be used for control of two intelligent disk drives. The circuit requires only a single jumper connection for definition of the drive address. Tristate drivers on all output circuits from the disk drive controller to the host computer are disabled when the drive is not selected.

Abstract: A DAC embodied in a CMOS integrated circuit converts a multi-bit digital signal to an analog-current signal. A higher-order portion of the digital signal, e.g., the most significant 5 bits of a byte, are decoded separately from the lower-order portion, e.g., the 3 least significant bits. The DAC includes circuitry for producing a first bias voltage, a first set of current sources each biased by the first bias voltage to produce a switchable current having a unit magnitude, and switching circuitry controlled by the decoded lower-order portion to cause a selected number of the unit-magnitude currents to contribute to the analog-current signal.

Abstract: A method for controlling a programmable source of a plurality of string of clock signals, a program is stored with a plurality of different indications of desired frequencies, each indication corresponding to one of the strings of clock signals. The frequency of each of a plurality of oscillator is controlled by the memory content of a separate memory for each oscillator. The content of each memory is adjusted in accordance with the actual frequency of each string, the frequency indicated by the corresponding indication of a desired frequency and a reference.

Abstract: The transient noise generated at the output drivers of an integrated circuit chip is reduced by maintaining an increasing ramp shaped current through each output driver during the entire transition interval between binary states of a capacitive load. A capacitor fed by a fixed current source is connected across the input of each output driver stage. The fixed current source and capacitor are so selected as to generate across the input of each output driver stage a linear ramp shaped control voltage that regulates the charging/discharging current through the output driver stage and package inductance in the described manner. A specially designed bias circuit reduces the sensitivity of the resulting transient noise to process variations and operating conditions. A feedback connection from the package inductance to the bias control circuit for the fixed current source adjusts the fixed current inversely with the transient noise.

Abstract: The present invention provides an architecture for sampling incoming asynchronous data pulses and providing synchronous output pulses having a constant pulse width. The invention has an input stage comprising a toggling flip-flop receiving the asynchronous pulses on the clock input. The complementary output of the flip-flop is provided to a dual path synchronizer stage followed by a dual path one-shot stage to terminate the synchronized pulse.