Abstract: A data storage device includes a number of blocks in multiple dies and a controller configured to perform operations. A method of controlling the data storage device includes: translating logical addresses to physical addresses; activating one or more dies; writing data to one or more blocks; determining the number of write operations performed on the storage device; facilitating determination of a lifetime of the storage device based on a number of blocks, a particular number of write operations, and a maximum number of write operations per block; providing the number of write operations that have been performed to a host to facilitate determination of an amount of a fee, where providing the number of write operations facilitates tracking a percentage of the lifetime of the storage device.

Abstract: A data storage device includes a controller and a memory die. The controller includes a host interface and a memory interface. A method includes receiving a message from a host device via the host interface. The message indicates that the host device is to perform a first adjustment process associated with the host interface. The method further includes performing a second adjustment process associated with the memory interface in response to receiving the message indicating that the host device is to perform the first adjustment process.

Abstract: The disclosure relates to quality of service (QOS) features for a router. The router may determine whether a congestion level of a first interface of the set of network interfaces exceeds a threshold level. Responsive to the congestion level exceeding the threshold level, the router activates a traffic analyzer configured to identify a first session that is present in the data traffic and inserts a set of packets that are part of the first session into a first queue of the set of queues via an expedited communications path over a bus. The router also forwards the set of packets in accordance with the desired quality of service.

Abstract: Dynamic modification of health metrics for data blocks in non-volatile storage media based on erase operation loop counts. In one implementation, a method includes iteratively erasing a block of non-volatile storage media until a count of non-erasable bits satisfies criteria comprising an allowable non-erasable bits parameter, and determining that a number of iterations needed to erase the block exceeds a threshold number of iterations. The method further includes, in response to the number of iterations exceeding the threshold number of iterations, increasing the allowable non-erasable bits parameter for a subsequent erasure of the block.

Abstract: Systems and methods for host system memory translation are disclosed. The memory system may send a logical-to-physical address translation table to the host system. Thereafter, the host system may send commands that include a logical address and a physical address (with the host system using the logical-to-physical address translation table previously sent to generate the physical address). After sending the table to the host system, the memory system may monitor changes in the table, and record these changes in an update table. The memory system may use the update table in determining whether to accept or reject the physical address sent from the host system in processing the host system command. In response to determining to reject the physical address, the memory system may internally generate the physical address using the logical address sent from the host system and a logical-to-physical address translation table resident in the memory system.

Abstract: A data storage device involves inner surfaces of sidewalls of a second cover overlapping with and adhesively bonded with the outer surfaces of sidewalls of an enclosure base having an uppermost top surface, where the second cover or an underlying first cover are removably adhered to the uppermost top surface of the base. The removable adhesive bond may comprise a pressure-sensitive adhesive, which can provide for reworkability during the manufacturing and testing process. The second cover-to-base sidewall bond may form a hermetic seal between the second cover and the base. Hence, a thinner base sidewall adjacent to the recording disks is enabled, leaving more space available for larger-diameter recording disks within a standard form factor, hermetically-sealed storage device, which may be filled with a lighter-than-air gas.

Abstract: The present disclosure generally relates to an electronic circuit and method of operating thereof to back up write cache data on DDR memory in data storage devices during an emergency power off (EPO). The method involves using a power management integrated circuit (PMIC), a combo driver and one MOSFET for regulator output. The method involves detecting a voltage value that is below a predetermined threshold value, retracting a write head away from a hard disk drive (HDD), backing up data, and then resetting the HDD after the backup is complete. The backing up and retraction may occur in parallel or in sequence. The method utilizes the spindle back-electromotive force (BEMF) power to have sufficient power to make the backup. If the power from the spindle BEMF is too low, then the retraction is suspended and a high impedance is present to lighten the load until the BEMF recovers before the power on reset. As such, the back-up data is not reset and volatized by a lack of power.

Abstract: The present disclosure generally relates to a method for intelligent device initiated SAS Phy PM. Using device internal phy characteristics and future phy usage queue, the device determines optimal SAS Phy PM usage based on a predetermined configuration preference of power versus performance. The device achieves optimal SAS Phy PM Usage by implementing a state machine to manage phy PM states and transitions between the PM states. The device state machine includes capabilities to proactively initiate transitions to partial or slumber PM states, start early wake-up from partial or slumber PM states to mask the associated latency impacts of exiting partial or slumber PM states, and selectively reject host requests to enter a partial or slumber PM state.

Abstract: The subject technology provides for managing a data storage system. Commands are identified into as a first command type or a second command type. The commands identified as the first command type are assigned to a first queue, and the commands identified as the second command type are assigned to a second queue. After the commands from the first queue and the commands from the second queue are processed based on a scheduling ratio over a predetermined period of time, a write amplification factor, number of host read commands, and number of host write commands during the predetermined period of time are determined. The scheduling ratio is updated based on the write amplification, the number of host read commands, the number of host write commands, and a predetermined scheduling ratio factor. Subsequent commands are processed from the first queue and the second queue based on the updated scheduling ratio.

Abstract: A storage system and method for adaptive scheduling of background operations are provided. In one embodiment, after a storage system completes a host operation in the memory, the storage system remains in a high power mode for a period of time, after which the storage system enters a low-power mode. The storage system estimates whether there will be enough time to perform a background operation in the memory during the period of time without the background operation being interrupted by another host operation. In response to estimating that there will be enough time to perform the background operation in the memory without the background operation being interrupted by another host operation, the storage system performs the background operation in the memory.

Abstract: Apparatuses, systems, and methods are disclosed for data availability during temporary inaccessibility of a memory region for memory. An apparatus may include a plurality of memory elements and a controller. A controller may be configured to identify a portion of memory of a plurality of memory elements such that data stored in a portion of memory is temporarily inaccessible and other data stored in other portions of memory in the plurality of memory elements is accessible. A controller may be configured to reconstruct data stored in a portion of memory from other data stored in other portions of memory. A controller may be configured to provide reconstructed data while a portion of an array is temporarily inaccessible.

Abstract: Apparatus, systems, methods, and computer program products for buffering storage device data in a host memory buffer (HMB) are presented. A non-volatile memory and a controller are in communication with a non-volatile memory. A controller is configured to receive an input/output (I/O) operation including data. A controller is configured to transmit at least a portion of data to an HMB of a host device separate from a non-volatile memory and a controller for storage until a trigger event occurs.

Abstract: In an on-chip copy process, performed by a storage device, data is copied from a plurality of Single Level Cell (SLC) blocks of non-volatile three-dimensional memory (e.g., 3D flash memory) in a respective memory die to a Multilevel Cell (MLC) block of the same memory die. A copy of source data from a respective SLC block is interleaved with a copy of source data from one or more other SLC blocks in the memory die to produce interleaved source data. Each source data copy that is interleaved is rotated by an offset assigned to the respective SLC block from which the source data is copied, and each respective SLC block in the plurality of SLC blocks is assigned a distinct offset. Each distinct set of the interleaved source data is written to a distinct respective MLC page of the MLC block.

Abstract: Apparatuses, systems, methods, and computer program products for streamed program commands with periodic garbage collection are disclosed. A controller is configured to set up a data path between the controller and a memory device to initialize an open mode. A controller is configured to perform a plurality of program operations on a memory device in an open mode using a same set up data path. A controller is configured to, in response to exiting an open mode, perform a garbage collection operation on a memory device.

Abstract: The present disclosure generally relates to data storage devices, and more specifically, to a magnetic media drive employing a magnetic recording head. The head includes a trailing shield, a main pole, a MAMR stack disposed between the trailing shield and the main pole, side shields surrounding at least a portion of the main pole, and a structure disposed between the side shields and the main pole at a media facing surface (WS). The structure is fabricated from a material that is thermally conductive and electrically insulating/dissipative. The material has a thermal conductivity of at least 50 W/(m*K) and an electrical resistivity of at least 105 ?*m. The structure helps dissipate joule heating generated from either the main pole or the MAMR stack into surrounding area without electrical shunting, leading to reduced heating or break-down induced failures.

Abstract: An error management system for a data storage device can generate soft-decision log-likelihood ratios (LLRs) using multiple reads of memory locations. Bit patterns provided by multiple reads of reference memory locations can be counted and used to generate probability data that is used to generate possible LLR values for decoding target pages. Possible LLR values are stored in one or more look-up tables.

Abstract: Methods and systems for decoding raw data may include determining a sequence of a plurality of read-level voltages based on previous decoding data and executing a multi-stage decoding operation to decode raw data read from the plurality of memory cells using the determined sequence of the plurality of read-level voltages. Decoded data is returned from the multi-stage decoding operation upon completion of the multi-stage decoding operation and the previous decoding data is updated based on results of the multi-stage decoding operation.

Abstract: A reliability cover that is disposed over at least one of an integrated circuit package and a Si die of the integrated circuit package is disclosed. The integrated circuit package is mountable to a printed circuit board via a plurality of solder balls. The reliability cover is configured to reduce a difference in a coefficient of thermal expansion between the integrated circuit package and the printed circuit board, and between the Si die and a substrate of the integrated circuit package by a threshold value.

Abstract: A method of indirection replay for a flash storage system includes writing data, in a host stream, to blocksets of the flash storage system. The host blocksets are assigned a major sequence number incremented from the most recently closed host blockset. The method includes writing an indirection journal to each host blockset which are associated with the assigned major sequence number. The method includes writing data, in a garbage collection (GC) stream, to other blocksets of the flash storage system. The GC blocksets are assigned a major sequence number, based on the most recently closed host blockset, and a minor sequence number, incremented from the most recently closed GC blockset. The method includes writing an indirection journal to each GC blockset which are associated with the assigned major and minor sequence numbers. The indirection table is constructed by replaying the journals of the blocksets in order of major sequence and minor sequence numbers.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for seed generation. An apparatus includes a memory element. An apparatus includes a scrambler component. A scrambler component includes a random seed generation circuit that generates a random seed. A scrambler component includes a deterministic seed generation circuit that generates a deterministic seed based on a physical address of a memory element for storing data. A scrambler component includes a computation circuit that forms a computed seed based on a random seed and a deterministic seed. Data is scrambled using a computed seed before data is stored.