Abstract: A memory system may include a volatile memory that is configured to store an address data structure that includes a plurality of logical-to-physical address entries. The address data structure may be stored across a plurality of bank groups of the volatile memory. A controller may be configured to store consecutive logical-to-physical address entries across different bank groups. In turn, during read and write operations for data sets associated with consecutive logical addresses, read requests for physical addresses where the data sets are stored may be sent to multiple bank groups and processed by the multiple banks in parallel.

Abstract: A microwave-assisted magnetic recording (MAMR) write head has a spin-torque oscillator (STO) and a ferromagnetic compensation layer between the write pole and trailing shield. The compensation layer is separated from the free layer by a nonmagnetic barrier layer that prevents spin-polarized electrons from the free layer from reaching the compensation layer. The compensation layer may be located between the write pole and the free layer. Electrons become spin-polarized by the compensation layer and are reflected back from the write pole across a nonmagnetic spacer layer. This causes the magnetization of the compensation layer to flip and become antiparallel to the magnetization of the free layer. The compensation layer thus generates a DC offset field that compensates for the negative effect of the DC shunting field from the free layer.

Abstract: Methods and systems for improving the reliability of stored data in the presence of cross-temperature variation are described. To reduce the number of data errors caused by cross-temperature variation, two or more sensing passes may be performed corresponding with two or more different sensing times. The amount of shifting in the memory cell threshold voltages may be determined on a per-bit basis or on a cell-by-cell basis based on the sensing operations performed during the two or more sensing passes. The stored data states may be assigned based on the amount of shifting in the memory cell threshold voltages during the two or more sensing passes and the type of cross-temperature variation present (e.g., whether the memory cells were programmed at a temperature above 65 degrees Celsius and read back at a temperature below 25 degrees Celsius).

Abstract: A system and method improve the performance of non-volatile memory storage by offloading parity computations to facilitate high speed data transfers, including direct memory access (DMA) transfers, between a remote host and a non-volatile memory based storage system, such as a flash memory based data storage device (e.g., SSD). In conjunction with writing to non-volatile memory storage, a stripe map is used to target a selected data storage device for parity generation. All data of a stripe is transmitted to the selected data storage device to generate the parity and the generated parity is propagated from the selected data storage device to other data storage devices in the stripe. The data for the stripe may also be propagated from the selected data storage device to the other data storage devices in the stripe.

Abstract: An apparatus includes a controller die and a group of dies that communicate with each other via a transmission line. Less than all of the dies of the group includes a respective on-die termination resistance circuit coupled to the transmission line. In some embodiments, one of the dies that includes an on-die termination resistance circuit is an end die of the group. In particular embodiments, the end die is the only die of the group that includes an on-die termination resistance circuit coupled to the transmission line. Transmission frequencies or data rates may be increased without degrading signal quality by removing capacitance associated with on-die termination resistance circuits from at least one of the dies of the group.

Abstract: Technology is disclosed herein for aborting a tail portion of a command queue in a storage device. In one aspect, one or more control circuits of a storage system are configured to abort tasks at a tail end of a command queue in response to receiving a task tail abort command. However, tasks at the head end of the command queue may still be executed. Thus, the head end of the command queue need not be rebuilt after the task tail abort command is performed. Therefore, considerable time is saved by not having to rebuild the head end of the command queue. Note that the task tail abort command may be received while the storage system is in a sequential command execution mode, in which tasks are executed in the order of their respective task identifiers.

Abstract: The present disclosure describes technologies and techniques for use with a data storage controller (such as a non-volatile memory (NVM) controller) to implement self-trimming of media data. In illustrative examples, an NVM controller stores a stream of video data in a NAND storage device, such as video obtained by a security camera. The controller also stores time stamps corresponding to portions of the video data. The controller then periodically (or during idle times) scans the stored information to identify video data that has exceeded a maximum data lifetime, such as data older than one week. Such data is deemed to be old/expired and is trimmed by the controller (by, e.g., marking corresponding entries in an allocation table as deleted or invalid). In this manner, the controller performs self-trimming of older video data to, for example, limit write amplification. NVMe examples are provided.

Abstract: The present disclosure generally relates to limiting bandwidth in storage devices. One or more bandwidth quality of services levels may be selected and associated with commands according to service level agreements, which may prioritize some commands over others. A storage device fetches and executes one or more the commands. Each of the commands is associated with a bandwidth quality of service level. After executing the commands and transferring the data to a host device, the storage device may delay writing a completion entry corresponding to the executed commands to a completion queue based on the associated bandwidth quality of service level of the commands. The device may then delay revealing the completion entry by delaying updating a completion queue head pointer. The device may further delay sending an interrupt signal to the host device based on the associated bandwidth quality of service level of the commands.

Abstract: Embodiments disclosed herein generally relate to a HAMR head. The HAMR head includes a main pole, a waveguide and a NFT disposed between the main pole and the waveguide. The NFT includes an antenna, and the antenna includes a first portion and a second portion. The second portion may be made of a material having a higher melting point than the material of the first portion. Having the second portion helps reduce the temperature rise of the NFT and reduce the laser power applied to the NFT.

Abstract: Methods, systems, and media for decoding data are described. A sequence of read-level voltages for decoding operations may be determined based on a trend of decoding success indicators, including a first decoding success indicator and a second decoding success indicator. The first decoding success indicator is obtained from a more recent successful decoding operation. The first one of the sequence may be set to a read-level voltage of the first decoding success indicator. If the read-level voltage of the first decoding success indicator is less than a read-level voltage of the second decoding success indicator, then the trend is decreasing, and the second one of the sequence may be set to a read-level voltage less than that of the first one of the sequence. After executing one or more decoding operations, the decoding success indicators may be updated based on the read-level voltage of the current successful decoding operation.

Abstract: A memory system configured to decode a data set may pause a convergence process to update reliability metric values. The memory system may utilize a positive feedback system that updates the reliability metric values by analyzing current a posteriori reliability metric values to calculate average estimated reliability characteristic values associated with a memory error model. The updates to the reliability metric values may provide increased error correction capability and faster decoding.

Abstract: A semiconductor device is disclosed including an integrated memory module. The integrated memory module may include a pair of semiconductor die, which together, operate as a single, integrated flash memory. In one example, the first die may include the memory cell array and the second die may include the logic circuit such as CMOS integrated circuits. In one example, the second die may be flip-chip bonded to the first die. The flip-chip bond pads on the first and second dies may be made small, with a small pitch, to allow a large number of electrical interconnections between the first and second semiconductor dies.

Abstract: Apparatuses, systems, and methods are disclosed for read threshold adjustment using reference data for non-volatile memory. An apparatus may include an array of non-volatile memory cells and a controller. A controller may be configured to write a predetermined reference data pattern to a region of an array. A controller may be configured to read reference data from a region. A controller may be configured to set one or more read thresholds based on identifying differences between reference data and a predetermined reference data pattern.

Abstract: A data storage device is disclosed comprising a head actuated over the disk. A first notch filter is calibrated at a first temperature, and a second notch filter is computed for a second temperature based on the first notch filter and a first delta temperature between the first temperature and the second temperature. The second notch filter is computed by transforming a continuous-time transfer function of the first notch filter adjusted by the first delta temperature into a discrete-time transfer function of the second notch filter.

Abstract: A method of forming a magnetic head includes forming a read sensor stripe, depositing an electronic lapping guide (ELG) layer over the substrate in an ELG region, forming a backside edge of a read sensor by patterning the read sensor stripe in a first patterning step, forming a backside insulator layer and a rear bias magnetic material portion over the backside edge of the read sensor, forming a backside edge of an ELG by patterning the ELG layer in the ELG region in a second patterning step, simultaneously forming a front side edge of the read sensor and a front side edge of the ELG, and lapping the read sensor and the ELG to provide an air bearing surface of a read sensor. The physical stripe height offset can be determined for each flash field by correlating device conductance and ELG conductance.

Abstract: The present disclosure relates to methods and systems for implementing redundancy in memory controllers. The disclosed systems and methods utilize a row of memory blocks, such that each memory block in the row is associated with an independent media unit. Failures of the media units are not correlated, and therefore, a failure in one unit does not affect the data stored in the other units. Parity information associated with the data stored in the memory blocks is stored in a separate memory block. If the data in a single memory block has been corrupted, the data stored in the remaining memory blocks and the parity information is used to retrieve the corrupted data.

Abstract: Disclosed herein are circuits, architectures, and methods that provide for the control of a data storage device write head's trailing shield and main pole potential with respect to the disk using circuitry that is integrated with circuitry used to bias a spin torque oscillator (STO) apparatus. Various embodiments include slider connections with STO bias circuitry that resides in a read/write integrated circuit, which has a programmable circuit that generates a bias current with overshoot (bias kicks). Also disclosed are circuits that may be incorporated into a slider to mitigate radio-frequency interference.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for redundant array of independent disks (RAID) stripe physical placement. An apparatus includes a plurality of memory die comprising physical pages for storing data. An apparatus includes a control circuit that assigns addresses to a plurality of data stripes, wherein the control circuit assigns the addresses to the plurality of data stripes by: assigning stripe pages of a data stripe of the plurality of data stripes to different memory die of a plurality of memory die; and assigning adjacent stripe pages of the data stripe to different page numbers.

Abstract: Example tiered storage systems, storage devices, and methods provide tier configuration for routing of data commands by peer storage devices. Each tiered storage device is configured to communicate with a plurality of peer storage devices with storage device identifiers. Each storage device is assigned to a performance tier in a tier configuration that determines which host data tier should be stored in the storage media of the storage device, the local performance tier for the storage device. If the local performance tier of the storage device does not match the host data tier for a data command or stored data element when the storage device determines the host data tier, the storage device selectively forwards the host data to another peer storage device with the performance tier that matches the host data tier.

Abstract: An electrical feed-through involves a laminate structure having alternating insulator and metal layers with electrically conductive through-holes formed therethrough, by which a lower connector pad is electrically connected with a corresponding upper connector pad, and wherein the number of through-holes is less than the number of connector pads on either side. Thus, the chain of clearances associated with the through-holes on the inner metal layer(s) is reduced, which provides more leak resistant metal material within the metal layer(s), while maintaining suitable electrical performance and avoiding disruption of existing manufacturing. Such a feed-through may be used at an interface between a hermetically-sealed internal environment, such as in a lighter-than-air gas filled data storage device, and the external environment.