Patents Assigned to Western Digital Technology, Inc.
  • Patent number: 12046256
    Abstract: Various illustrative aspects are directed to a data storage device, comprising one or more disks; an actuator mechanism configured to position one or more heads proximate to a corresponding disk surface of the one or more disks; and one or more processing devices. The one or more processing devices comprise read/write circuitry which comprises an asynchronous demodulation module. The asynchronous demodulation module is configured to receive demodulated null burst signals based on the selected head reading servo burst fields of the corresponding disk surface; and output, based on the demodulated null burst signals, a radial position signal, indicative of a radial position of the selected head.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: July 23, 2024
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Satoshi Yamamoto
  • Patent number: 12046265
    Abstract: Various illustrative aspects are directed to a data storage device, comprising one or more disks; an actuator mechanism configured to position one or more heads proximate to a corresponding disk surface of the one or more disks; and one or more processing devices. The one or more processing devices are configured to: select a sector on the corresponding disk surface to which to write data, wherein the sector is selected in accordance with a data erosion mitigation pattern; and output, while the head is positioned proximate to a preceding sector that precedes the selected sector, a laser pre-bias current to a laser-generating component of the head, wherein the laser pre-bias current is sufficient to induce significant data erosion on the preceding sector.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: July 23, 2024
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Guoxiao Guo, Erhard S. Schreck, William B. Boyle, Kei Yasuna
  • Patent number: 12046257
    Abstract: An exclusive operation approach, in the context of background activity processes among multiple LUNs corresponding to a multi-actuator hard disk drive, can avoid related power peaks by controlling background operations so that they are not permitted to run concurrently across different LUNs. Managing the progress of one or more background activities such as background media scan (BMS) for each LUN, including aligning the progress of the background activity among multiple LUNs, can reduce power consumption of a multi-actuator drive.
    Type: Grant
    Filed: July 21, 2023
    Date of Patent: July 23, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Toshiroh Unoki, Ryoji Fukuhisa, Hisatoshi Iwata, Jun Yoshida
  • Patent number: 12045473
    Abstract: A data storage device and method for prediction-based improved power-loss handling. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to predict a probability of an ungraceful shutdown of the data storage device; determine whether the probability is greater than a threshold; and in response to determining that the probability is greater than the threshold, reduce a risk of data loss that would occur in response to the ungraceful shutdown of the data storage device. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
    Type: Grant
    Filed: June 14, 2022
    Date of Patent: July 23, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ariel Navon, Shay Benisty, Judah Gamliel Hahn
  • Patent number: 12046266
    Abstract: Various illustrative aspects are directed to a data storage device, comprising one or more disks; an actuator mechanism configured to position one or more heads proximate to a corresponding disk surface of the one or more disks; and one or more processing devices. The one or more processing devices are configured to apply a pre-bias current to the assistive energy emitter at a first value while the selected head is positioned proximate to one or more spiral patterns on the corresponding disk surface. The one or more processing devices are further configured to apply the pre-bias current to the assistive energy emitter at a boosted value while the selected head is not positioned proximate to the one or more spiral patterns, wherein the boosted value is greater than the first value.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: July 23, 2024
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Guoxiao Guo, Dan Wang, Yun Hong, Xiaokun Chew
  • Publication number: 20240243101
    Abstract: A stacked chip scale semiconductor device includes one or more semiconductor die stacks. Each semiconductor die stack may include a pair of semiconductor dies. A first of the pair of semiconductor dies may be provided with a pattern of contact pads distributed across its major surface configured to be flip chip bonded to a host device. A second of the pair of semiconductor dies may include a row of contact pads. The first semiconductor die may be bonded on top of the second semiconductor die in an offset, stepped configuration so that the row of contact pads of the second semiconductor die is left exposed. Like channels of contact pads on the first and second semiconductor dies may then be electrically coupled by additive manufacturing or conductive trace printing.
    Type: Application
    Filed: July 17, 2023
    Publication date: July 18, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Chee Seng Wong, Yoong Tatt Chin, Wei Chiat Teng
  • Patent number: 12040031
    Abstract: A memory die assembly, comprising a non-volatile memory structure, performs autonomous testing of the memory die assembly by repeatedly performing a group of tests for multiple cycles such that the group of tests includes programming, erasing and reading the non-volatile memory structure. Failure events from the tests are recorded by storing error data for each recorded failure event including a location in the non-volatile memory structure of the failure event, a type of test that failed and a cycle during which the failure event occurred.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: July 16, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Liang Li, Yan Li, Wenkai Liu
  • Patent number: 12040001
    Abstract: The present disclosure relates to pretreating a magnetic recording head assembly for magnetic media drive. The magnetic recording head assembly comprises a slider having a media facing surface (MFS), a top surface disposed opposite the MFS, a trailing edge surface disposed adjacent to the top surface, and an optical grating disposed on the trailing edge surface. A vertical cavity surface emitting laser (VCSEL) device is mounted to the trailing edge surface of the slider. The VCSEL device is aligned with the optical grating. A magnetic recording head comprising a waveguide and a near field transducer (NFT) coupled to the waveguide is disposed on the trailing edge surface of the slider. The VCSEL device is capable of emitting a plurality of lasers that are phase coherent on to the optical grating. The optical grating is capable of directing the emitted lasers about 90 degrees to the waveguide.
    Type: Grant
    Filed: August 3, 2023
    Date of Patent: July 16, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventor: Barry C. Stipe
  • Patent number: 12039198
    Abstract: The present disclosure generally relates to an efficient manner of fetching data for write commands. The data can be fetched prior to classification, which is a fetch before mode. The data can alternatively be fetched after classification, which is a fetch after mode. When the data is fetched after classification, the write commands are aggregated until sufficient data associated with any command is split between memory devices. When in fetch before mode, the data should properly align such that data associated with any command is not split between memory devices. Efficiently toggling between the fetch before and fetch after modes will shape how writes are performed without impacting latency and bandwidth without significantly increasing write buffer memory size.
    Type: Grant
    Filed: May 20, 2022
    Date of Patent: July 16, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amir Segev, Shay Benisty
  • Patent number: 12039202
    Abstract: A programming order of memory dies of a metablock is typically fixed. However, in some storage architectures, this may cause performance bottlenecks. As such, the programming order of the memory dies may be altered to reduce or eliminate performance bottlenecks.
    Type: Grant
    Filed: September 16, 2022
    Date of Patent: July 16, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amit Sharma, Abhinandan Venugopal
  • Patent number: 12038797
    Abstract: Various devices, such as storage devices or storage systems are configured to avoid ungraceful shutdowns utilizing recycled power. Storage devices typically generate heat during normal operations. Energy recycling modules disposed on various components of the storage device recycle this heat. This recycled heat can be captured and converted into electricity that can be stored for later discharge and use. These energy recycling modules can be a series of semiconductors that utilize various natural effects to convert heat applied on one side of the module into electricity that can be delivered to various power storing components. The stored power can be utilized in the event of a sudden power loss in order to power one or more components necessary to perform a graceful shutdown. In this way, even when power is totally cut off from the storage device, there is enough stored recycled electricity that an ungraceful shutdown can be avoided.
    Type: Grant
    Filed: May 17, 2022
    Date of Patent: July 16, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Cono J. Sammarco, Gurjit Chadha
  • Patent number: 12038853
    Abstract: The present disclosure generally relates to reducing link-up time between an upstream device and a downstream device. Rather than re-coordinating the link between devices each time, knowledge gained from a previous link-up is used to speed up the link-up. Typically, when both the upstream device and the downstream device have not changed, then the coefficient values for downstream port (DSP) transmission (Tx) equilibrium (EQ) that resulted in a desired bit error rate (BER) should not have changed either. Hence, rather than exchanging coefficients, the previous values can be reused with confidence eliminating the need to exchange coefficients. In so doing, the link-up process is much faster and system resources are not wasted on unnecessary coefficient exchanges.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: July 16, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventor: Shuli Shmaya
  • Patent number: 12040114
    Abstract: The present disclosure generally relates to magnetoresistive (MR) devices. The MR device comprises a synthetic antiferromagnetic (SAF) layer that increases stability to magnetic fields, and in turn, results in lower magnetic noise of the device. The MR device comprises a first ferromagnetic (FM1) layer and a second ferromagnetic (FM2) layer, in between which is an SAF spacer of RuAl alloy having a B2 crystalline structure with (001) texture, meaning that the (001) plane is parallel to the surface of MR device substrate. The first ferromagnetic (FM1) layer and a part of the second ferromagnetic (FM2) layer also have the (001) texture. An amorphous layer in a second ferromagnetic (FM2) layer can reset the growth texture of the MR device to a (111) texture in order to promote the growth of an antiferromagnetic (AF) pinning layer.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: July 16, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Susumu Okamura, James Mac Freitag, Yuankai Zheng, Brian R. York
  • Patent number: 12038844
    Abstract: A method and apparatus for cache management and eviction polices using unsupervised reinforcement learning schemes is disclosed.
    Type: Grant
    Filed: January 31, 2023
    Date of Patent: July 16, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Opher Lieber, Ariel Navon, Alexander Bazarsky, Shay Benisty
  • Patent number: 12039173
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a read command to read data from the memory device or a write command to write data to the memory device from a host device, determine whether a bottleneck exists in a data/control path between the host device and the memory device, wherein the bottleneck exists in an input queue corresponding to a hardware module of a plurality of hardware modules, and execute a bottleneck release operation when the bottleneck exists in the data/control path between the host device and the memory device, wherein the bottleneck release operation is dependent on whether the bottleneck exists in the input queue. The bottleneck release operation includes changing a clock of the hardware module, moving the command to a different hardware module configured to process the command, and combinations thereof.
    Type: Grant
    Filed: October 3, 2022
    Date of Patent: July 16, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventor: Refael Ben-Rubi
  • Publication number: 20240232068
    Abstract: A data storage device and method for race-based data access in a multiple host memory buffer system are provided. In one embodiment, the data storage device stores data in a plurality of host memory buffers in the host instead of in just the host memory buffer usually associated with the data. To read the data, the data storage device sends read commands to all of the host memory buffers. That way, even if some of the host memory buffers are busy, the data can be returned from another one of the host memory buffers. In future reads in similar workloads, a read command can be sent to the host memory buffer that returned the data. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
    Type: Application
    Filed: July 18, 2023
    Publication date: July 11, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Shay Benisty, Ariel Navon
  • Publication number: 20240232070
    Abstract: An AON module on a storage device periodically obtains the temperatures of the storage device and memory device. A controller uses the temperatures obtained by the AON module to determine a calculated temperature. The controller determines when the calculated temperature is above a thermal threshold and causes the storage device to enter the thermal sleep state where normal operations on the storage device are suspended. In the thermal sleep state, power to the AON module is maintained and the power to other components is modified. The AON module starts a cool-off timer and after a cool-off time expires, the AON module causes power to at least one component on the storage device to be turned on to determine whether the temperature of the storage device is below a first thermal throttling threshold and to cause the storage device to resume normal operations.
    Type: Application
    Filed: September 25, 2023
    Publication date: July 11, 2024
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: NITIN JAIN, SRIKANTH PEDDAYYAVANDLA
  • Publication number: 20240231639
    Abstract: A data storage device and method for reducing read disturbs when reading redundantly-stored data are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The memory is configured to redundantly store a plurality of copies of data, wherein the plurality of copies of the data comprise a primary copy of the data and at least one secondary copy of the data. The controller is configured to randomly select one of the plurality of copies of the data instead of selecting the primary copy of the data as a default; and read, from the memory, the randomly-selected one of the plurality of copies of the data. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
    Type: Application
    Filed: July 12, 2023
    Publication date: July 11, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Eran Moshe, Gadi Vishne
  • Publication number: 20240232032
    Abstract: A non-volatile memory device that performs stream temperature interleave monitoring includes a plurality of regions of non-volatile memory and a controller. The controller is configured to monitor different access frequencies for data received by the non-volatile memory device. The controller is configured to determine interleave metrics indicating amounts of data of different access frequencies stored by each of the plurality of regions of non-volatile memory. The controller is configured to perform a subsequent action for the non-volatile memory device based on the determined interleave metrics.
    Type: Application
    Filed: August 11, 2023
    Publication date: July 11, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: LIAT HOD, OMER GILAD, RAFI PAZ, EINAV ZILBERSTEIN, EYAL SOBOL, JUDAH GAMLIEL HAHN
  • Publication number: 20240233759
    Abstract: The present disclosure is generally related to a magnetic recording device comprising a magnetic recording head. The magnetic recording head comprises a main pole (MP), a shield, and a spintronic device disposed between the MP and the shield. The spintronic device comprises a MP notch disposed on the MP, a first spin torque layer (STL), a second STL, a spin kill layer disposed between the first and second STLs, and a shield notch. The spin kill layer prevents spin torque from being transferred between the first STL and the second STL. In a forward stack where electrons flow from the MP to the shield, the MP notch comprises FeCr and the shield notch comprises CoFe. In a reverse stack where electrons flow from the shield to the MP, the MP notch comprises CoFe and the shield notch comprises FeCr.
    Type: Application
    Filed: July 25, 2023
    Publication date: July 11, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Muhammad ASIF BASHIR, Alexander GONCHAROV, Yaguang WEI