Patents Assigned to Western Digital Technology, Inc.
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Patent number: 12100432Abstract: Various illustrative aspects are directed to a data storage device, comprising one or more disks; an actuator mechanism configured to position one or more heads proximate to a corresponding disk surface of a corresponding disk of the one or more disks; and one or more processing devices. The one or more processing devices are configured to: determine a plurality of readings of an energy sensor output from an energy sensor disposed on the selected head during a rotation of the corresponding disk; determine an average of the readings of the energy sensor output; and use the average of the readings of the energy sensor output as a control parameter for controlling a fly height of the selected head.Type: GrantFiled: August 11, 2023Date of Patent: September 24, 2024Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Aiko Sakoguchi, Masaru Furukawa, Kenji Tasaka
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Patent number: 12100422Abstract: Various illustrative aspects are directed to a data storage device comprising a plurality of disks and actuator assemblies, each actuator assembly comprising one or more preamplifiers and one or more heads actuated over one of the plurality of disks, wherein each of the one or more heads comprises a read element and a write element. The data storage device further comprises a System on Chip (SoC) comprising one or more processing devices, a first and a second transmission line path between the SoC and a first and a second actuator assembly, respectively, where the first and the second transmission line path intersect at a matched point compensation (MPC), and wherein the one or more processing devices are configured to transmit write data to, or receive read data from, at least one preamplifier of the plurality of actuator assemblies.Type: GrantFiled: August 10, 2023Date of Patent: September 24, 2024Assignee: Western Digital Technologies, Inc.Inventors: Daniel Oh, John T. Contreras
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Publication number: 20240312482Abstract: The present disclosure generally relates to a tape head and a tape head drive including a tape head. The tape head comprises at least one same gap verify (SGV) module comprising a plurality of write transducer and read transducer pairs. Each write transducer is coupled to writer bonding pads via writer leads, and each read transducer is coupled to reading bonding pads via reader leads. An isolation shield is disposed between the write transducer and read transducer such that the isolation shield is disposed between each writer lead and each reader lead. The isolation shield acts as a Faraday cage to reduce cross-talk between the write and read transducers. The SGV module is configured to write data to a tape using the write transducers and read verify the data written on the tape using the read transducers such that the write transducers and read transducers are concurrently operable.Type: ApplicationFiled: July 28, 2023Publication date: September 19, 2024Applicant: Western Digital Technologies, Inc.Inventors: David J. SEAGLE, Robert G. BISKEBORN
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Publication number: 20240312808Abstract: An integrated die ejector for separating a die from a wafer, the die ejector includes an ejector mechanism that includes an ejector pin. There is an ejector base coupled to the ejector pin and configured to couple the integrated die ejector to a die attach ejector machine. There is a pepper pot at least partially surrounding the ejector mechanism and ejector base and a sleeve coupled thereto and positioned between the ejector mechanism and pepper pot. The sleeve and pepper pot define an upper and lower motion limit of the ejector base and retain the ejector mechanism within the pepper pot such that the integrated die ejector may be coupled to and decoupled from the die attach ejector machine as a single unit to reduce installation time.Type: ApplicationFiled: August 3, 2023Publication date: September 19, 2024Applicant: Western Digital Technologies, Inc.Inventors: Simon Yan, JianHua Wang, Kaijian Shi, Bin Liu, Zhonghua Qian, Jim Zhang, Joyce Chen, Juan Zhou
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Publication number: 20240312546Abstract: Technology is disclosed herein for checking data integrity in a non-volatile storage system. The storage system may operate in a first mode in which a data integrity check is performed in closed blocks until more than an allowed number of word lines fail the data integrity check. After a closed block has more than the allowed number of the word lines fail the data integrity check, then the storage system may operate in a second mode in which a data integrity check is performed in open blocks. The allowed number of word lines may be equal to the number of word lines that can be recovered by XOR data in the event data is uncorrectable by an ECC engine. The data integrity check of a target word line in an open block may be performed after programming a word line adjacent to the target word line in the open block.Type: ApplicationFiled: July 25, 2023Publication date: September 19, 2024Applicant: Western Digital Technologies, Inc.Inventors: Sugandha Sharma, Mahim Raj Gupta
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Publication number: 20240312538Abstract: A non-volatile memory system is configured to perform a multiplane erase process that concurrently erases groups of memory cells in multiple planes. Based on that multiplane erase process, the memory system determines that a first group of memory cells in a first plane of the multiple planes is slow to erase. As a result, the system will perform one or more multiplane erase processes for the groups of memory cells in multiple planes without erasing the first group of memory cells in the first plane as part of the multiplane erase process(es).Type: ApplicationFiled: July 25, 2023Publication date: September 19, 2024Applicant: Western Digital Technologies, Inc.Inventors: Liang Li, Dandan Yi, Dana Lee
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Publication number: 20240312916Abstract: A semiconductor device package includes a substrate, a stack of memory dies positioned on the substrate, and an interposer spaced from the stack of memory dies and also positioned on the substrate. First and second sets of bond pads are electrically connected to the substrate, where the second set of bond pads is positioned on the interposer above the substrate. A first set of bond wires electrically connects a first sub-stack of the memory dies to the first set of bond pads. A second set of bond wires electrically connects a second sub-stack of memory dies, positioned above the first sub-stack, to the second set of bond wires. The first and second sub-stacks of memory dies may be electrically isolated from one another to reduce noise in electrical signals transmitted to and from the memory dies.Type: ApplicationFiled: July 28, 2023Publication date: September 19, 2024Applicant: Western Digital Technologies, Inc.Inventors: Nagesh Vodrahalli, Chih-Yang Li, Shrikar Bhagath, Narayanan Terizhandur V
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Patent number: 12093548Abstract: Aspects of a storage device are provided that optimize stream oriented writing of sequential data streams for improved read and write performance. The storage device includes a non-volatile memory including a plurality of blocks, and a controller configured to receive a plurality of host write commands each including a sequential data stream. In response to determining the host write commands include sequential data streams, the controller writes each of the sequential data streams respectively to different sequential open blocks, where the blocks are respectively associated with the sequential data streams. The controller may afterwards read each of the sequential data streams respectively from the different blocks. As a result, sequential data from multiple streams may not be stored in a mixed pattern in a same sequential block, thereby allowing the controller to issue fewer read or relocate commands in a block for a given sequential data stream.Type: GrantFiled: May 10, 2022Date of Patent: September 17, 2024Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Sridhar Prudviraj Gunda, Kalpit Bordia
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Patent number: 12094498Abstract: The present disclosure generally relates to a spin torque element disposed between a main pole and a shield in a magnetic recording head. The shield could be a trailing shield, a side shield, or a leading shield. The spin torque element includes a dual layer spin transfer structure that is spaced from magnetic layers on either side using spacer layers. One magnetic layer that faces a positive polarizer has a positive polarization while another magnetic layer facing the negative polarizer has a negative polarization. As such, torque in the spacer layers is maximized when the direction of the magnetization in the STL is opposite to the gap field.Type: GrantFiled: July 19, 2023Date of Patent: September 17, 2024Assignee: Western Digital Technologies, Inc.Inventors: Alexander Goncharov, James Mac Freitag, Susumu Okamura, Muhammad Asif Bashir
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Patent number: 12094499Abstract: The present disclosure generally relates to a dual free layer (DFL) read head. In one embodiment, a dual free layer (DFL) read head, comprising: a tunnel magneto resistance (TMR) sensor disposed at a media facing surface (MFS); soft bias (SB) side shields disposed adjacent to the TMR sensor at the MFS; and a rear soft bias (RSB) disposed adjacent to the TMR sensor recessed from the MFS. The RSB has a nonmagnetic cap, the nonmagnetic cap comprising: a first nonmagnetic cap layer; and a second nonmagnetic cap layer, wherein an etch selectivity of the first nonmagnetic cap layer to the second nonmagnetic cap layer is a ratio of a:b in a first chemistry and a ratio of x:y in a second chemistry, wherein a is greater than b, and y is greater than x, and the second nonmagnetic cap layer is disposed on the first nonmagnetic cap layer.Type: GrantFiled: July 10, 2023Date of Patent: September 17, 2024Assignee: Western Digital Technologies, Inc.Inventors: Howard Gordon Zolla, Rong Cao
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Patent number: 12094500Abstract: A hard disk drive carriage arm includes a top depressed portion or indentation extending from a top surface toward a bottom surface and a bottom depressed portion or indentation extending from the bottom surface toward the top surface and opposing the top depressed portion. As such, a separating structure between the depressed portions partitions a corresponding balance hole, preferably at or near a mid-plane between the top and bottom surfaces. This configuration does not notably increase windage-based power loss while suppressing fluid force fluctuation, thereby stabilizing and balancing the airflow inside of the depressed portions.Type: GrantFiled: July 17, 2023Date of Patent: September 17, 2024Assignee: Western Digital Technologies, Inc.Inventors: Yoshiyuki Hirono, Andre Chan
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Patent number: 12094503Abstract: Example storage medium servo patterns, data storage devices, and methods to provide servo tracks with continuously varying frequency in a data storage device are described. The data storage device may include storage media, such as magnetic disks, having servo sectors that define servo tracks, where adjacent servo tracks have continuously varying frequency as the head moves from one servo track to the next. As the head is actuated over the storage medium, a target track frequency may be determined based on the radial position of a target servo track and the channel frequency may be set to the target track frequency to follow the target servo track.Type: GrantFiled: August 3, 2023Date of Patent: September 17, 2024Assignee: Western Digital Technologies, Inc.Inventors: Guoxiao Guo, Jason Laks, Charles A. Park, Scott A. Ottele, Gary Herbst
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Patent number: 12096583Abstract: In one embodiment, an apparatus is provided. The apparatus includes a printed circuit board. The apparatus also includes a first connector coupled to the printed circuit board. The first connector is configured to couple the apparatus to a computing device. The apparatus further includes a second connector coupled to the printed circuit board. The second connector is configured to couple the apparatus to a data storage device. The apparatus further includes a securement mechanism comprising a first portion and a second portion. The securement mechanism is movable about the apparatus between a first position and a second position. The first portion is configured to maintain the securement mechanism at the first position. The second portion is configured to secure the data storage device to the apparatus when the securement mechanism is in the first position.Type: GrantFiled: January 27, 2023Date of Patent: September 17, 2024Assignee: Western Digital Technologies, IncInventors: Everett Lyons, Daniel Linnen, Randy Gillespie
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Patent number: 12094502Abstract: The present disclosure generally relates to a tape head and a tape drive including a tape head. The tape head comprises a plurality of data heads disposed at a media facing surface (MFS) and one or more servo heads disposed at the MFS. The plurality of data heads each individually have a first stripe height extending from the MFS to a back edge of a module. The one or more servo heads each individually have a second stripe height extending from the MFS towards the back edge of the module. The second stripe height is about 10% to about 75% less than the first stripe height. By making the second stripe height less than the first stripe height, the area of the servo heads is reduced while the resistance of the sensors of the servo heads is increased.Type: GrantFiled: July 28, 2023Date of Patent: September 17, 2024Assignee: Western Digital Technologies, Inc.Inventors: David J. Seagle, Diane L. Brown
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Patent number: 12092686Abstract: An apparatus for electrically coupling an electrical interface of a unit under test with a debugging component includes a bracket assembly having a socket configured to electrically couple with the electrical interface, a baseplate assembly configured to secure the unit under test on a plate, a crane assembly coupled to the bracket assembly, and a cable assembly. The crane assembly is configured to enable movement of the socket relative to the electrical interface in each of a horizontal direction, a vertical direction, and an angular direction; and secure the socket in place relative to the electrical interface while applying a force by the socket against the electrical interface. The cable assembly is associated in part with the bracket assembly and is configured to electrically couple with the socket at a first end and with the debugging component at a second end.Type: GrantFiled: December 14, 2021Date of Patent: September 17, 2024Assignee: Western Digital Technologies, Inc.Inventors: Aleksandr Dean Schwerdt, Daniel Roy Ostrander, David Alexander Jachmann, Lynn Charles Berning, Robert Joseph Harvey, Eric Lee Severtson, Curtis Adam Harper
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Patent number: 12094496Abstract: The present disclosure generally relates to a tape head and a tape head drive including a tape head. The tape head comprises at least one same gap verify (SGV) module comprising a plurality of write transducer and read transducer pairs. Each write transducer is coupled to writer bonding pads via writer leads, and each read transducer is coupled to reading bonding pads via reader leads. An isolation shield is disposed between the write transducer and read transducer such that the isolation shield is disposed between each writer lead and each reader lead. The isolation shield acts as a Faraday cage to reduce cross-talk between the write and read transducers. The SGV module is configured to write data to a tape using the write transducers and read verify the data written on the tape using the read transducers such that the write transducers and read transducers are concurrently operable.Type: GrantFiled: July 28, 2023Date of Patent: September 17, 2024Assignee: Western Digital Technologies, Inc.Inventors: David J. Seagle, Robert G. Biskeborn
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Patent number: 12094501Abstract: A hard disk drive head slider housing a read-write transducer includes electrical pads for bonding with a suspension flexure, electrically conductive bonding studs each extending into the slider body from a corresponding bonding pad, electrical pads for testing where each is positioned proximate to and at a distance from a corresponding bonding pad, electrically conductive testing studs each extending into the slider body from a corresponding testing pad, and a conductive layer within the slider body for electrically connecting a bonding pad with a corresponding testing pad via respective bonding and testing studs. This arrangement accomplishes the effects of a commonly-employed anti-wetting overlay separating the testing pad from the bonding pad, without the added cost, capital expenditure, process and yield difficulties associated with the anti-wetting overlay.Type: GrantFiled: July 21, 2023Date of Patent: September 17, 2024Assignee: Western Digital Technologies, Inc.Inventor: David P. Druist
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Publication number: 20240304273Abstract: A flash memory includes an improved error handling algorithm for data recovery. Rather than running a default read recovery only, an Enhance Read Retry (ERR) process also is performed. After running a default read recovery, WLs are flagged with an error flag if the read was unsuccessful. The flag triggers ERR mode. ERR mode implements increase of the row read bias or implements increase of row read time or implements multiple pulses at the same voltage, or a combination of all three.Type: ApplicationFiled: July 19, 2023Publication date: September 12, 2024Applicant: Western Digital Technologies, Inc.Inventors: Xuan TIAN, Liang LI, Vincent YIN, Daniel J. LINNEN
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Publication number: 20240302957Abstract: A storage device is communicatively coupled to a host that defines a quality of service level for responses transmitted from the storage device to the host. The storage device includes a memory device to store data. The storage device also includes a controller to perform background operations to manage resources on the memory device while performing foreground operations according to the quality of service level set by the host. The controller generates a free block file including information on free blocks in the memory device and transmits the free block file to the host. The host uses the free block file to determine when the memory device is at or near a critical level of block availability and transmits an indication from to the controller. The controller adjusts the priority of the background operations in response to receipt of the indication to maintain the quality of service level.Type: ApplicationFiled: August 9, 2023Publication date: September 12, 2024Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.Inventor: Niles Yang
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Patent number: D1042446Type: GrantFiled: June 11, 2021Date of Patent: September 17, 2024Assignee: Western Digital Technologies, Inc.Inventors: Steven Tzu-Yen Peng, Gregory A. VanderPol, Mark F. Sterzick