Abstract: A semiconductor device includes: a substrate; a channel layer disposed on the substrate, wherein the channel layer is made of GaN; a barrier layer disposed on the channel layer, wherein the barrier layer is made of AlzGa1-zN; and an inserting structure inserted between the channel layer and the barrier layer. The inserting structure includes: a first inserting layer disposed on the channel layer, wherein the first inserting layer is made of AlxGa1-xN; and a second inserting layer disposed on the first inserting layer, wherein the second inserting layer is made of AlyGa1-yN, and y is greater than x. The semiconductor device further includes: a gate electrode disposed on the barrier layer; a source electrode and a drain electrode disposed on the barrier layer and respectively at opposite sides of the gate electrode; and a spike region formed below at least one of the source electrode and the drain electrode.

Abstract: A vertical-cavity surface-emitting laser includes a substrate. A first mirror is disposed on the substrate. An active layer is disposed on the first mirror. An oxide layer is disposed on the active layer. An aperture is disposed on the active layer. The aperture is surrounded by the oxide layer. A second mirror is disposed on the aperture and the oxide layer. A high-contrast grating is disposed on the second mirror. The high-contrast grating includes a first grating element and a second grating element, and the first grating element and the second grating element are spaced apart from each other with an air gap therebetween. A passivation layer is disposed on the high-contrast grating. A first thickness of the passivation layer on a top surface of the first grating element is greater than a second thickness of the passivation layer on a first sidewall of the first grating element.

Abstract: A vertical cavity surface emitting laser includes an active area, an inner trench, an outer trench, and a first implantation region. The active area includes a first mirror, an active region, a second mirror, and an etch stop layer. The first mirror is formed over a substrate. The active region is formed over the first mirror. The second mirror is formed over the active region. The etch stop layer with an aperture is formed between the active region and the second mirror. The inner trench surrounds the active area in a top view. The outer trench is formed beside the inner trench. The first implantation region is formed below the inner trench.

Abstract: A HEMT structure includes a compound semiconductor substrate, a gate electrode, a source electrode, a drain electrode, a first metal pillar, a second metal pillar, a dielectric layer, and a metal layer. The gate electrode is disposed on the compound semiconductor substrate. The source electrode is disposed on the compound semiconductor substrate at a first side of the gate electrode. The drain electrode is disposed on the compound semiconductor substrate at a second side of the gate electrode. The first metal pillar is disposed on the source electrode. The second metal pillar is disposed on the drain electrode. The dielectric layer is disposed on the compound semiconductor substrate. The dielectric layer surrounds the gate electrode, the first metal pillar, and the second metal pillar. The metal layer is disposed on the dielectric layer. The metal layer straddles the gate electrode, the first metal pillar, and the second metal pillar.

Abstract: A heterojunction bipolar transistor includes: a substrate; a base mesa disposed on the substrate, wherein the base mesa includes a collector layer and a base layer disposed on the collector layer, and wherein in a top view, the base layer includes a first edge and a second edge opposite to the first edge; an emitter layer disposed on the base layer; a base electrode disposed on the substrate and connected to the base layer; a dielectric layer disposed on the base electrode, wherein a first via hole is formed in the dielectric layer at the first edge of the base layer, and a second via hole is formed in the dielectric layer at the second edge of the base layer; and a conductive feature disposed on the dielectric layer, wherein the conductive feature is connected to the base electrode through the first via hole and the second via hole.

Abstract: A bulk acoustic wave resonator and a formation method thereof are provided. The method for forming the bulk acoustic wave resonator includes forming a sacrificial structure on a substrate. A seed layer is formed on the sacrificial structure. A bottom electrode is formed on the seed layer. A piezoelectric layer is formed on the bottom electrode. A top electrode is formed on the piezoelectric layer. The sacrificial structure is removed to form a cavity. The seed layer is etched through the cavity.

Abstract: A semiconductor structure includes a substrate, and an active device and a passive device over the substrate. The active device is disposed in a first region of the substrate, and the passive device is disposed in a second region of the substrate. The semiconductor structure further includes a shielding structure and a passivation layer. The shielding structure includes a barrier layer and a ceiling layer. The barrier layer is on the passive device and the active device, and the ceiling layer is on the barrier layer. The passivation layer is under the barrier layer and covers a top surface of the passive device. An air cavity is defined by sidewalls of the barrier layer, a bottom surface of the ceiling layer, and the substrate.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate having a front side and a back side opposite the front side. The semiconductor structure also includes a first contact metal layer disposed on the front side of the substrate. The semiconductor structure further includes a III-V compound semiconductor layer disposed between the substrate and the first contact metal layer. Moreover, the semiconductor structure includes a via hole penetrating through the substrate and the III-V compound semiconductor layer from the back side of the substrate. The bottom of the via hole is defined by the first contact metal layer, and the first contact metal layer includes molybdenum, tungsten, iridium, palladium, platinum, cobalt, ruthenium, osmium, rhodium, rhenium, or a combination thereof.

Abstract: A bipolar transistor includes a substrate, a sub-collector layer, a collector layer, a base layer, an emitter layer, a passivation layer, and a collector electrode. The sub-collector layer is formed over the substrate. The collector layer is formed over the sub-collector layer. The base layer is formed over the collector layer. The emitter layer is formed over the base layer. The passivation layer is formed over the substrate and covering a sidewall of the collector layer. The collector electrode is connected to the sub-collector layer through an opening in the passivation layer. The opening exposes at least a portion of the sub-collector layer.

Abstract: A semiconductor structure includes a substrate, a passive device and an active device over the substrate. The active device is formed in the first region of the substrate, and the passive device is formed in the second region of the substrate. The semiconductor structure further includes a passivation layer that covers the top surface of the passive device. The passivation layer has an opening that exposes the active device.

Abstract: A bulk acoustic wave filter comprises a substrate, an insulating layer disposed on the substrate and having a first cavity and a second cavity formed therein, a first bulk-acoustic-wave-resonance-structure disposed on the first cavity and a second bulk-acoustic-wave-resonance-structure disposed on the second cavity. The first bulk-acoustic-wave-resonance-structure comprises a first bottom electrode disposed on the first cavity, a first top electrode disposed on the first bottom electrode, a first piezoelectric layer portion sandwiched between the first top electrode and the first bottom electrode, and a first frequency tuning structure disposed between the first cavity and the first bottom electrode. The second bulk-acoustic-wave-resonance-structure comprises a second bottom electrode disposed on the second cavity, a second top electrode disposed on the second bottom electrode, a second piezoelectric layer portion sandwiched between the second top electrode and the second bottom electrode.

Abstract: A heterojunction bipolar transistor includes an emitter layer on a base layer on a collector layer on an upper sub-collector layer over a bottom sub-collector layer, a first dielectric film over the bottom sub-collector layer, the base layer and the emitter layer, a base electrode on the first dielectric film, electrically connected to the base layer through at least one first via hole in the first dielectric film, a second dielectric film on the first dielectric film and the base electrode, and a conductive layer on the second dielectric film, with conductive layer electrically connected to base electrode through a second via hole disposed in the second dielectric film, first dielectric film between the base electrode and first sidewall of a stack including the base layer and the collector layer, and second via hole laterally separated from the base layer.

Abstract: A method for fabricating bulk acoustic wave resonator with mass adjustment structure, comprising following steps of: forming a sacrificial structure mesa on a substrate; etching the sacrificial structure mesa such that any two adjacent parts have different heights, a top surface of a highest part of the sacrificial structure mesa is coincident with a mesa top extending plane; forming an insulating layer on the sacrificial structure mesa and the substrate; polishing the insulating layer to form a polished surface; forming a bulk acoustic wave resonance structure including a top electrode, a piezoelectric layer and a bottom electrode on the polished surface; etching the sacrificial structure mesa to form a cavity; the insulating layer between the polished surface and the mesa top extending plane forms a frequency tuning structure, the insulating layer between the mesa top extending plane and the cavity forms a mass adjustment structure.

Abstract: A heterojunction bipolar transistor includes a bottom sub-collector layer formed over a substrate. The heterojunction bipolar transistor also includes an upper sub-collector layer formed over the bottom sub-collector layer. The heterojunction bipolar transistor also includes a collector layer formed over the upper sub-collector layer. The heterojunction bipolar transistor also includes a base layer formed over the collector layer. The heterojunction bipolar transistor also includes an emitter layer formed over the base layer. The heterojunction bipolar transistor also includes a passivation layer covering the bottom sub-collector layer, the upper sub-collector layer, the collector layer, the base layer, and the emitter layer. The heterojunction bipolar transistor also includes a collector electrode that covers the portion of the passivation layer that is over the sidewall of the upper sub-collector layer.

Abstract: A gallium arsenide (GaAs) radio frequency (RF) circuit is disclosed. The GaAs RF circuit includes a power amplifier and a low noise amplifier; a first transmit/receive (TR) switch, coupled to the power amplifier and the low noise amplifier, wherein the first TR switch is fabricated by a pHEMT (Pseudomorphic High Electron Mobility Transistor) process; and a first active phase shifter, coupled to the power amplifier or the low noise amplifier, wherein the first active phase shifter is fabricated by an HBT (Heterojunction Bipolar Transistor) process; wherein the GaAs RF circuit is formed within a GaAs die.

Abstract: A power flat no-lead (FN) package is provided. The power FN package includes a die paddle; a die, disposed on the die paddle, operating at a radio frequency; a first lead, disposed by a first side of the die paddle, configured to receive an input signal of the power FN package; and a capacitor, disposed on the first lead; wherein a lead width of the first lead is greater than a half of a first side length of the first side.

Abstract: A monolithic integration of enhancement mode (E-mode) and depletion mode (D-mode) field effect transistors (FETs) comprises a compound semiconductor substrate overlaid by an epitaxial structure overlaid by source and drain electrodes. The epitaxial structure includes from bottom to top sequentially a buffer layer, a channel layer, a Schottky barrier layer, a first etch stop layer, and a first cap layer. The respective first gate metal layers of the D-mode and E-mode FET are in contact with the first etch stop layer. The D-mode and E-mode gate-sinking regions are beneath the respective first gate metal layers of the D-mode and E-mode gate electrode at least within the first etch stop layer. The first gate metal layer material of the D-mode is the same as that of the E-mode, where the first gate metal layer thickness of the E-mode is greater than that of the D-mode.

Abstract: A heterojunction bipolar transistor includes an emitter layer on a base layer on a collector layer on an upper sub-collector layer over a bottom sub-collector layer, a first dielectric film over the bottom sub-collector layer, the base layer and the emitter layer, a base electrode on the first dielectric film, electrically connected to the base layer through at least one first via hole in the first dielectric film, a second dielectric film on the first dielectric film and the base electrode, and a conductive layer on the second dielectric film, with conductive layer electrically connected to base electrode through a second via hole disposed in the second dielectric film, first dielectric film between the base electrode and first sidewall of a stack including the base layer and the collector layer, and second via hole laterally separated from the base layer.

Abstract: A gate-sinking pseudomorphic high electron mobility transistor comprises a compound semiconductor substrate overlaid with an epitaxial structure which includes sequentially a buffer layer, a channel layer, a Schottky layer, and a first cap layer. The Schottky layer comprises from bottom to top at least two stacked regions of semiconductor material. Each of the two adjacent stacked regions differs in material from the other and provides a stacked region contact interface therebetween. In any two adjacent stacked regions of the Schottky layer, one stacked region composed of AlGaAs-based semiconductor material alternates with the other stacked region composed of InGaP-based semiconductor material. A gate-sinking region is beneath the first gate metal layer of the gate electrode, and the bottom boundary of the gate-sinking region is located at the one of the at least one stacked region contact interface of the Schottky layer.

Abstract: A bipolar transistor includes an upper sub-collector layer, a collector layer, a base layer, an emitter layer, and a collector electrode. The collector layer is disposed on the upper sub-collector layer. The base layer is disposed on the collector layer. An emitter layer is disposed on the base layer. The collector electrode is disposed directly on a sidewall of the upper sub-collector layer.