Patents Assigned to WIN Semiconductors Corp.
  • Patent number: 11177374
    Abstract: A heterojunction bipolar transistor includes an emitter layer on a base layer on a collector layer on an upper sub-collector layer over a bottom sub-collector layer, a first dielectric film over the bottom sub-collector layer, the base layer and the emitter layer, a base electrode on the first dielectric film, electrically connected to the base layer through at least one first via hole in the first dielectric film, a second dielectric film on the first dielectric film and the base electrode, and a conductive layer on the second dielectric film, with conductive layer electrically connected to base electrode through a second via hole disposed in the second dielectric film, first dielectric film between the base electrode and first sidewall of a stack including the base layer and the collector layer, and second via hole laterally separated from the base layer.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: November 16, 2021
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: She-Hsin Hsiao, Rong-Hao Syu, Shu-Hsiao Tsai
  • Patent number: 11177379
    Abstract: A gate-sinking pseudomorphic high electron mobility transistor comprises a compound semiconductor substrate overlaid with an epitaxial structure which includes sequentially a buffer layer, a channel layer, a Schottky layer, and a first cap layer. The Schottky layer comprises from bottom to top at least two stacked regions of semiconductor material. Each of the two adjacent stacked regions differs in material from the other and provides a stacked region contact interface therebetween. In any two adjacent stacked regions of the Schottky layer, one stacked region composed of AlGaAs-based semiconductor material alternates with the other stacked region composed of InGaP-based semiconductor material. A gate-sinking region is beneath the first gate metal layer of the gate electrode, and the bottom boundary of the gate-sinking region is located at the one of the at least one stacked region contact interface of the Schottky layer.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: November 16, 2021
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Chia-Ming Chang, Jung-Tao Chung, Chang-Hwang Hua, Ju-Hsien Lin, Yan-Cheng Lin, Yu-Chi Wang
  • Patent number: 11164962
    Abstract: A bipolar transistor includes an upper sub-collector layer, a collector layer, a base layer, an emitter layer, and a collector electrode. The collector layer is disposed on the upper sub-collector layer. The base layer is disposed on the collector layer. An emitter layer is disposed on the base layer. The collector electrode is disposed directly on a sidewall of the upper sub-collector layer.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: November 2, 2021
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Chien-Rong Yu, Shu-Hsiao Tsai, Jui-Pin Chiu
  • Patent number: 11128264
    Abstract: A bias compensation circuit, coupled to an amplifying transistor, is disclosed. The bias compensation circuit comprises a voltage locking circuit, comprising a first terminal and a second terminal, wherein the first terminal is coupled to a third terminal the amplifying transistor, and the second terminal is coupled to a control terminal of the amplifying transistor; and a first resistor, coupled to the first terminal of the voltage locking circuit; wherein when the voltage locking circuit is conducted, a voltage difference between the first terminal and the second terminal is substantially constant.
    Type: Grant
    Filed: April 19, 2020
    Date of Patent: September 21, 2021
    Assignee: WIN Semiconductors Corp.
    Inventors: Po-Kie Tseng, Chih-Wen Huang, Jui-Chieh Chiu, Shao-Cheng Hsiao
  • Patent number: 11101533
    Abstract: A radio frequency (RF) device includes a chip comprising a plurality of vias and at least a hot via; a signal lead and a ground lead disposed under a back side of the chip; and a signal metal sheet, a first ground metal sheet and a second ground metal sheet disposed on a top side of the chip. The signal metal sheet crosses over the first gap formed between the signal lead and the ground lead. The first ground metal sheet and the second ground metal sheet are coupled to the ground lead through the plurality of vias. The first ground metal sheet and the second ground metal sheet substantially surround the signal metal sheet.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: August 24, 2021
    Assignee: WIN Semiconductors Corp.
    Inventors: Chih-Wen Huang, Jui-Chieh Chiu
  • Patent number: 11081485
    Abstract: A monolithic integrated circuit device formed in a multi-layer structure comprises a low-pinch-off-voltage pHEMT and a high-pinch-off-voltage pHEMT. A Schottky layer in the multi-layer structure contains at least three stacked regions of semiconductor material, wherein each of the two adjacent stacked regions differs in material and provides a stacked region contact interface therebetween. The gate-sinking pHEMTs each includes a gate contact, a first gate metal layer, a gate-sinking region, and a gate-sinking bottom boundary. The first gate metal layers are in contact with the topmost stacked region of the Schottky layer. The gate-sinking regions are beneath the first gate metal layers. The gate-sinking bottom boundary of the high-pinch-off-voltage pHEMT, which is closer to the semiconductor substrate than the gate-sinking bottom boundary of the low-pinch-off-voltage pHEMT, locates within 10 ? above or below one of the stacked region contact interfaces of the Schottky layer.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: August 3, 2021
    Assignee: Win Semiconductors Corp.
    Inventors: Chia-Ming Chang, Jung-Tao Chung, Yan-Cheng Lin, Lung-Yi Tseng
  • Patent number: 11070185
    Abstract: A method for forming cavity of bulk acoustic wave resonator comprising following steps of: forming a sacrificial epitaxial structure mesa on a compound semiconductor substrate; forming an insulating layer on the sacrificial epitaxial structure mesa and the compound semiconductor substrate; polishing the insulating layer by a chemical-mechanical planarization process to form a polished surface; forming a bulk acoustic wave resonance structure on the polished surface, which comprises following steps of: forming a bottom electrode layer on the polished surface; forming a piezoelectric layer on the bottom electrode layer; and forming a top electrode layer on the piezoelectric layer, wherein the bulk acoustic wave resonance structure is located above the sacrificial epitaxial structure mesa; and etching the sacrificial epitaxial structure mesa to form a cavity, wherein the cavity is located under the bulk acoustic wave resonance structure.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: July 20, 2021
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Chia-Ta Chang, Chun-Ju Wei, Kuo-Lung Weng
  • Patent number: 10886392
    Abstract: A semiconductor structure for improving the thermal stability and Schottky behavior by engineering the stress in a III-nitride semiconductor, comprising a III-nitride semiconductor and a gate metal layer. The III-nitride semiconductor has a top surface on which a conductive area and a non-conductive area are defined. The gate metal layer is formed directly on the top surface of the III-nitride semiconductor and comprises a gate connection line and at least one gate contact extending from the gate connection line in a second direction perpendicular to the length of the gate connection line. The at least one gate contact forms a Schottky contact with the III-nitride semiconductor on the conductive area, and the gate connection line is in direct contact with the III-nitride semiconductor on the non-conductive area. The non-conductive area of the III-nitride semiconductor is at least partially covered by the gate connection line.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: January 5, 2021
    Assignee: Win Semiconductors Corp.
    Inventors: Jhih-Han Du, Yi Wei Lien, Che-Kai Lin, Wei-Chou Wang
  • Patent number: 10811407
    Abstract: A monolithic integration of enhancement mode (E-mode) and depletion mode (D-mode) field effect transistors (FETs) comprises a compound semiconductor substrate overlaid by an epitaxial structure overlaid by source and drain electrodes. The epitaxial structure includes from bottom to top sequentially a buffer layer, a channel layer, a Schottky barrier layer, a first etch stop layer, and a first cap layer. The respective first gate metal layers of the D-mode and E-mode FET are in contact with the first etch stop layer. The D-mode and E-mode gate-sinking regions are beneath the respective first gate metal layers of the D-mode and E-mode gate electrode at least within the first etch stop layer. The first gate metal layer material of the D-mode is the same as that of the E-mode, where the first gate metal layer thickness of the E-mode is greater than that of the D-mode.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: October 20, 2020
    Assignee: WIN SEMICONDUCTOR CORP.
    Inventors: Chia-Ming Chang, Jung-Tao Chung, Yan-Cheng Lin, Lung-Yi Tseng
  • Patent number: 10804176
    Abstract: A low stress moisture resistant structure of semiconductor device comprises a low stress moisture resistant layer, wherein a semiconductor device is formed on a semiconductor wafer, the semiconductor device comprises at least one pad, the low stress moisture resistant layer is coated on the semiconductor device and the semiconductor wafer so that a pad top center surface of the pad is exposed. The low stress moisture resistant layer comprises a material comprising crosslinked fluoropolymer. A before-coated stress measured on the semiconductor wafer before the low stress moisture resistant layer is coated and an after-cured stress measured on the semiconductor wafer after the low stress moisture resistant layer is coated and cured define a stress difference, the stress difference is greater than or equal to ?5×107 dyne/cm2 and less than or equal to 5×107 dyne/cm2.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: October 13, 2020
    Assignees: WIN Semiconductors Corp., The Chemours Company FC, LLC
    Inventors: Ray Chen, Xudong Chen, Shih-Hui Huang, Liang-Feng Shen, Gin Tsai, Walter Tony Wohlmuth
  • Patent number: 10756625
    Abstract: An integrated module of acoustic wave device with active thermal compensation comprises a substrate, an acoustic wave filter, an active adjustment circuit and at least one variable capacitance device. The acoustic wave filter comprises a plurality of series acoustic wave resonators formed on the substrate, at least one shunt acoustic wave resonator formed on the substrate and a thermal sensing acoustic wave resonator. Each of the variable capacitance device is connected in parallel to one of the series and shunt acoustic wave resonators. The active adjustment circuit outputs an active thermal compensation signal correlated to a thermal variation sensed by the thermal sensing acoustic wave resonator to the variable capacitance device. The active thermal compensation signal induces a capacitance variation of the variable capacitance device such that the impact of the thermal variation to the acoustic wave device is compensated.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: August 25, 2020
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Re Ching Lin, Shu Hsiao Tsai, Cheng Kuo Lin, Chih-Feng Chiang, Fan Hsiu Huang, Tung-Yao Chou
  • Patent number: 10727741
    Abstract: An acoustic wave filter having thermal sensing acoustic wave resonator comprises a substrate, a plurality of series acoustic wave resonators formed on the substrate, at least one shunt acoustic wave resonator formed on the substrate and a thermal sensing acoustic wave resonator. The thermal sensing acoustic wave resonator is one of a series acoustic wave resonator and a shunt acoustic wave resonator. Thereby the thermal sensing acoustic wave resonator plays dual roles of thermal sensing and acoustic wave filtering.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: July 28, 2020
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Re Ching Lin, Shu Hsiao Tsai, Cheng Kuo Lin, Fan Hsiu Huang, Chih-Feng Chiang, Tung-Yao Chou
  • Patent number: 10720390
    Abstract: An ohmic metal for GaN device comprises a diffusion barrier seed metal layer and a plurality of metal layers. The diffusion barrier seed metal layer is formed on an epitaxial structure layer. The diffusion barrier seed metal layer is made of Pt. The epitaxial structure layer is made of AlGaN or GaN. The plurality of metal layers is formed on the diffusion barrier seed metal layer. The plurality of metal layers comprises a first metal layer and a second metal layer. The first metal layer is formed on the diffusion barrier seed metal layer. The first metal layer is made of Ti. The second metal layer is formed on the first metal layer. The second metal layer is made of Al. By the diffusion barrier seed metal layer, so as to suppress the diffusion of the plurality of metal layers into the epitaxial structure layer.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: July 21, 2020
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Chang-Hwang Hua, Yi-Wei Lien
  • Patent number: 10714409
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate; an active circuit portion, disposed on the substrate; a dielectric portion, disposed on the active circuit portion, wherein a hole is formed within the dielectric portion and the hole penetrates through the dielectric portion; and a radiating metal sheet, disposed on the dielectric portion; wherein the active circuit portion and the radiating metal sheet are coupled through the hole.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: July 14, 2020
    Assignee: WIN Semiconductors Corp.
    Inventors: Chih-Wen Huang, Jui-Chieh Chiu
  • Patent number: 10679924
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate; an active circuit portion including at least an active component and formed on a topside of the semiconductor device; and a radiating metal sheet formed on a backside of the semiconductor device. A hole is formed within the substrate and the hole penetrates through the substrate. The active circuit portion and the radiating metal sheet are coupled through the hole.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: June 9, 2020
    Assignee: WIN Semiconductors Corp.
    Inventors: Chih-Wen Huang, Jui-Chieh Chiu
  • Patent number: 10665555
    Abstract: A transition structure disposed in a package is disclosed. The transition structure comprises a first ground lead and a second ground lead; and a signal lead, disposed between the first ground lead and the second ground lead, wherein the first ground lead and the second ground lead have an exterior edge and an interior edge, the signal lead is coupled to a metal line formed on a printed circuit board (PCB) and a signal terminal of the die within the package; wherein an exterior gap formed between the first ground lead and the second ground lead at the exterior edge is wider than an interior gap formed between the first ground lead and the second ground lead at the interior edge.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: May 26, 2020
    Assignee: WIN Semiconductors Corp.
    Inventors: Jui-Chieh Chiu, Chih-Wen Huang, Chen-Yang Hsieh, You-Cheng Lai
  • Patent number: 10656178
    Abstract: A method for aligning an inhomogeneous receiver with an anisotropic emitter on a wafer probing system, wherein a reference semiconductor die comprising a reference pad and an anisotropic emitter is formed on a semiconductor wafer, the reference pad is located at a reference-pad-and-anisotropic-emitter relative position corresponding to the anisotropic emitter, the method comprises following steps of: measuring a receiver center position of an inhomogeneous receiver configured on a wafer probing system by a profile sensor; measuring a reference tip position of a reference tip of a reference probe on a probe card by a measuring instrument; displacing the inhomogeneous receiver in an aligning displacement according to the reference-pad-and-anisotropic-emitter relative position, the reference tip position and the receiver center position; and aligning the reference tip with the reference pad by a probe-tip-and-pad aligning machine of the wafer probing system.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: May 19, 2020
    Assignee: Win Semiconductors Corp.
    Inventor: Shu-Jeng Yeh
  • Patent number: 10643993
    Abstract: A compound semiconductor monolithically integrated circuit device with transistors and diodes comprises a compound semiconductor substrate, a transistor epitaxial structure, a transistor upper structure, a first diode, and a second diode. The transistor epitaxial structure forms on the compound semiconductor substrate. The first diode, the second diode, and the transistor upper structure form on a first part, a second part, and a third part of the transistor epitaxial structure, respectively. The transistor upper structure and the third part of the transistor epitaxial structure form a transistor. The first diode comprises a first part of an n-type doped epitaxial layer, a first part of a first intrinsic epitaxial layer, a first electrode, and a second electrode. The second diode comprises a second part of the n-type doped epitaxial layer, a second part of the first intrinsic epitaxial layer, a first electrode, and a second electrode.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: May 5, 2020
    Assignee: Win Semiconductors Corp.
    Inventors: Hsi-Tsung Lin, Yan-Cheng Lin, Sheng-Hsien Liu
  • Patent number: 10608608
    Abstract: A method for fabricating bulk acoustic wave resonator with mass adjustment structure, comprising following steps of: forming a sacrificial structure mesa on a substrate; etching the sacrificial structure mesa such that any two adjacent parts have different heights, a top surface of a highest part of the sacrificial structure mesa is coincident with a mesa top extending plane; forming an insulating layer on the sacrificial structure mesa and the substrate; polishing the insulating layer to form a polished surface; forming a bulk acoustic wave resonance structure including a top electrode, a piezoelectric layer and a bottom electrode on the polished surface; etching the sacrificial structure mesa to form a cavity; the insulating layer between the polished surface and the mesa top extending plane forms a frequency tuning structure, the insulating layer between the mesa top extending plane and the cavity forms a mass adjustment structure.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: March 31, 2020
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Chia-Ta Chang, Chun-Ju Wei, Kuo-Lung Weng
  • Patent number: 10594286
    Abstract: A method for forming cavity of bulk acoustic wave resonator comprising following steps of: forming a sacrificial epitaxial structure mesa on a compound semiconductor substrate; forming an insulating layer on the sacrificial epitaxial structure mesa and the compound semiconductor substrate; polishing the insulating layer by a chemical-mechanical planarization process to form a polished surface; forming a bulk acoustic wave resonance structure on the polished surface, which comprises following steps of: forming a bottom electrode layer on the polished surface; forming a piezoelectric layer on the bottom electrode layer; and forming a top electrode layer on the piezoelectric layer, wherein the bulk acoustic wave resonance structure is located above the sacrificial epitaxial structure mesa; and etching the sacrificial epitaxial structure mesa to form a cavity, wherein the cavity is located under the bulk acoustic wave resonance structure.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: March 17, 2020
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Chia-Ta Chang, Chun-Ju Wei, Kuo-Lung Weng