Patents Assigned to Winbond Electronic Corp.
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Publication number: 20220359525Abstract: Provided is a memory device including a substrate, a plurality of bit-line structures, a plurality of bit-line contacts, and a plurality of protective structures. The substrate has a plurality of active areas. The plurality of bit-line structures are disposed on the substrate in parallel along a X direction. The plurality of bit-line contacts are respectively disposed at overlaps of the plurality of bit-line structures and the plurality of active areas, and electrically connect the plurality of bit-line structures and the plurality of active areas. The plurality of protective structures are disposed at least on a first sidewall and a second sidewall of the plurality of bit-line contacts. A method of forming a memory device is also provided.Type: ApplicationFiled: January 20, 2022Publication date: November 10, 2022Applicant: Winbond Electronics Corp.Inventors: Chun-Sheng Yang, Hsing-Hao Chen
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Publication number: 20220359173Abstract: An etching method of etching apparatus is disclosed. The etching apparatus performs an etching process on a material to be processed which includes a material layer and a mask layer formed on the material layer. The etching method includes the following steps. The mask layer is etched. A light intensity at a specific wavelength for light generated is detected when the etching process is performed on the mask layer to be processed and an end point detection signal is generated. An etching completion time of the mask layer to be etched is determined according to the end point detection signal. A thickness of the mask layer to be etched is calculated according to the etching completion time. An etching time of the material layer is adjusted according to the thickness of the mask layer to be etched. The material layer is etched after adjusting the etching time.Type: ApplicationFiled: July 21, 2022Publication date: November 10, 2022Applicant: Winbond Electronics Corp.Inventors: Shih-Chieh Lin, Shuen-Hsiang Ke
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Patent number: 11495304Abstract: A control method of a memory device is provided. When a target memory cell whose source is connected to a first source line needs to be read, a word line controller provides a first voltage to a word line corresponding to the target memory cell and also provides the first voltage to a word line corresponding to the next row of the target memory cell, so that the period when the word line corresponding to the target memory cell remains at the first voltage overlaps the period when the word line corresponding to the next row of the target memory cell remains at the first voltage. When the target memory cell needs to be read, a source line controller provides a second voltage to the first source line, and provides a third voltage to the second source line; the third voltage is not equal to the second voltage.Type: GrantFiled: July 23, 2021Date of Patent: November 8, 2022Assignee: Winbond Electronics Corp.Inventor: Wen-Chiao Ho
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Patent number: 11495637Abstract: Provided are a resistive random access memory and a method of manufacturing the same. The resistive random access memory includes a stacked structure and a bit line structure. The stacked structure is disposed on a substrate. The stacked structure includes a bottom electrode, a top electrode and a resistance-switching layer. The bottom electrode is disposed on the substrate. The top electrode is disposed on the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The bit line structure covers a top surface of the stacked structure and covers a portion of a sidewall of the stacked structure. The bit line structure is electrically connected to the stacked structure.Type: GrantFiled: July 1, 2020Date of Patent: November 8, 2022Assignee: Winbond Electronics Corp.Inventors: Po-Yen Hsu, Shih-Ning Tsai, Bo-Lun Wu, Tse-Mian Kuo
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Patent number: 11496118Abstract: A semiconductor device that can automatically transition from a standby mode to a deep power down (DPD) mode is provided. The semiconductor device includes a DPD controller supporting the DPD mode and multiple internal circuits. The DPD controller measures a time since a time point of entering the standby mode and generates multiple power down enable signals for further reducing power consumption in the standby mode in response to elapse of a measurement time, so that operations of the multiple internal circuits are stopped in stages.Type: GrantFiled: January 14, 2021Date of Patent: November 8, 2022Assignee: Winbond Electronics Corp.Inventor: Naoaki Sudo
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Patent number: 11494259Abstract: Provided is a variable resistance random-access memory for suppressing degradation of performance by recovering a memory cell that fails. A variable resistance random-access memory of the disclosure includes a memory array, a row selection circuit, a column selection circuit, a controller, an error checking and correcting (ECC) circuit, an error bit flag register, and an error bit address register. The memory array includes a plurality of memory cells. The column selection circuit includes a sense amplifier and a write driver/read bias circuit. The error bit flag register stores bits for indicating presence/absence of an error bit in a write operation. The error bit address register stores an address of the error bit. The controller recovers the error bit when a predetermined event occurs.Type: GrantFiled: December 11, 2020Date of Patent: November 8, 2022Assignee: Winbond Electronics Corp.Inventor: Norio Hattori
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Patent number: 11495605Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The manufacturing method includes the following steps. A substrate having a capacitor region and a periphery region is provided, wherein a transistor is formed in the substrate in the capacitor region, and a conductive device is formed in the substrate in the periphery region. A capacitor is formed on the substrate in the capacitance region, wherein the capacitor is electrically connected to the transistor, and an upper electrode layer of the capacitor extends onto the substrate in the periphery region. A protective layer is formed on the upper electrode layer. A doped layer is formed in at least the surface of the protective layer in the capacitor region. An etching process is performed using the doped layer as a mask to remove the protective layer and the upper electrode layer in the periphery region.Type: GrantFiled: December 15, 2020Date of Patent: November 8, 2022Assignee: Winbond Electronics Corp.Inventors: Chi-An Wang, Kai Jen, Wei-Che Chang
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Patent number: 11495492Abstract: Provided is a method for manufacturing a semiconductor device, including: forming a conductive layer on the first dielectric layer; forming a recess in the conductive layer; performing a first etching process to round a top corner of the recess; performing a second etching process to remove the conductive layer exposed from a bottom surface of the recess and thereby forming an opening having a rounding top corner in the conductive layer; and forming a second dielectric layer in the opening.Type: GrantFiled: September 9, 2020Date of Patent: November 8, 2022Assignee: Winbond Electronics Corp.Inventor: Cheng-Che Lee
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Patent number: 11495312Abstract: A memory circuit and a memory programming method adapted to program flash memory are provided. The memory circuit includes a charge pumping circuit, a voltage regulator, a voltage sensor, and a plurality of switch circuits. The charge pumping circuit generates a pumping voltage and a pumping current. The voltage regulator is coupled to the charge pumping circuit and generates a programming voltage and a programming current to program the flash memory according to the pumping voltage and the pumping current. The voltage sensor is coupled to the voltage regulator to monitor a voltage value of the programming voltage. Each of the plurality of switch circuits includes a first terminal coupled to the voltage sensor and a second terminal coupled to the flash memory. A quantity of the plurality of switch circuits that are turned on is determined by the voltage value of the programming voltage.Type: GrantFiled: May 20, 2021Date of Patent: November 8, 2022Assignee: Winbond Electronics Corp.Inventors: Wen-Chiao Ho, Pil-Sang Ryoo
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Publication number: 20220352710Abstract: An electrostatic discharge (ESD) protection circuit includes a first transistor, a second transistor, a capacitor, a voltage dividing circuit, and a first diode. The first transistor is coupled between a first power rail and a second power rail. The second transistor is coupled between the first power rail and the second power rail. A bulk of the second transistor is coupled to a control terminal of the first transistor. The capacitor is coupled between the first power rail and a control terminal of the second transistor. The voltage dividing circuit is coupled between the control terminal of the second transistor and the second power rail, and has a divided voltage output terminal coupled to the bulk of the second transistor. The first diode is coupled between the divided voltage output terminal and the second power rail.Type: ApplicationFiled: January 13, 2022Publication date: November 3, 2022Applicant: Winbond Electronics Corp.Inventors: Jhih-Chun Syu, Chao-Lung Wang
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Publication number: 20220352463Abstract: A resistive random access memory cell includes a first electrode layer, an oxygen reservoir layer, a variable resistance layer, and a second electrode. The first electrode layer is located on a dielectric layer, and includes a body part extending in a first direction and multiple extension parts connected to a sidewall of the body part and extending in a second direction. The second direction is perpendicular to the first direction. The oxygen reservoir layer covers the first electrode layer. The variable resistance layer is located between the first electrode layer and the oxygen reservoir layer. The second electrode is located above a top surface of the oxygen reservoir layer and around an upper sidewall of the oxygen reservoir layer.Type: ApplicationFiled: September 2, 2021Publication date: November 3, 2022Applicant: Winbond Electronics Corp.Inventors: Po-Yen Hsu, Bo-Lun Wu, Tse-Mian Kuo
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Publication number: 20220352172Abstract: A memory structure including a substrate, a bit line structure, a contact structure, a stop layer, and a capacitor structure is provided. The substrate includes a memory array region. The bit line structure is located in the memory array region and located on the substrate. The contact structure is located in the memory array region and located on the substrate on one side of the bit line structure. The stop layer is located in the memory array region and located above the bit line structure. The capacitor structure is located in the memory array region. The capacitor structure passes through the stop layer and is electrically connected to the contact structure. A bottom surface of the capacitor structure is lower than a bottom surface of the stop layer.Type: ApplicationFiled: May 3, 2021Publication date: November 3, 2022Applicant: Winbond Electronics Corp.Inventors: Keng-Ping Lin, Shu-Ming Li, Tzu-Ming Ou Yang
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Patent number: 11487614Abstract: A semiconductor storing apparatus capable of shortening a ECC processing time of a readout operation is provided, including a flash memory includes: a memory cell array; a page buffer/sense circuit holding data read out from a selected page of the memory cell array; an error correcting code circuit receiving data from the page buffer/sense circuit and holding error address information of the data; an output circuit selecting data from the page buffer/sense circuit based on a column address, and outputting the selected data to a data bus; and an error correction part correcting data of the data bus based on the error address information.Type: GrantFiled: March 3, 2021Date of Patent: November 1, 2022Assignee: Winbond Electronics Corp.Inventor: Makoto Senoo
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Patent number: 11488644Abstract: A semiconductor device capable of performing high-speed read or high-reliability read is provided. A reading method of a NAND flash memory includes: pre-charging a sensing node through a voltage-supply node; discharging the sensing node to the voltage-supply node for a prescribed operation; recharging the sensing node by the voltage-supply node after the prescribed operation; and discharging a NAND string and sensing a memory cell.Type: GrantFiled: May 14, 2021Date of Patent: November 1, 2022Assignee: Winbond Electronics Corp.Inventors: Sho Okabe, Makoto Senoo
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Patent number: 11487343Abstract: A semiconductor storing apparatus and a flash memory operation method, for shortening a recovery time from a deep power-down (DPD) mode without a dedicated command for the DPD are provided. A flash memory includes: a standard command interface circuit and a DPD controller, operating through an external power voltage; a voltage supply node, for supplying power from the external power voltage via a first current path; a voltage supply node, for supplying power from the external power voltage via a second current path; an internal circuit group, connected to the voltage supply node; and a charge pump circuit, connected to the voltage supply node. When the DPD mode is released, the internal circuit group is enabled after the charge pump circuit is enabled.Type: GrantFiled: May 26, 2020Date of Patent: November 1, 2022Assignee: Winbond Electronics Corp.Inventor: Naoaki Sudo
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Publication number: 20220344343Abstract: A dynamic random access memory includes a substrate, an isolation structure, and a buried word line structure. The isolation structure is located in the substrate and defines multiple active regions. The buried word line structure is located in a word line trench in the substrate, and the word line trench passes through the active regions and the isolation structure. The buried word line structure includes a gate conductive layer, a first gate dielectric layer, and a second gate dielectric layer. The gate conductive layer is located in the word line trench. The first gate dielectric layer is located on a sidewall and a bottom surface of the word line trench. The second gate dielectric layer is located between the first gate dielectric layer and the gate conductive layer, and a top surface of the second gate dielectric layer is lower than a top surface of the gate conductive layer.Type: ApplicationFiled: September 2, 2021Publication date: October 27, 2022Applicant: Winbond Electronics Corp.Inventor: Hung-Yu Wei
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Publication number: 20220344348Abstract: Provided is a DRAM including: a substrate, a plurality of chop structures, and a plurality of buried word lines. The plurality of chop structures are located in the substrate. Each of the plurality of chop structures comprises a first portion and a second portion. The first portion is located above the second portion, and a width of the second portion is less than a width of the first portion. The plurality of buried word lines, located at bottoms of a plurality of buried word line trenches. The plurality of buried word line trenches passes through the first portion of the plurality of chop structures and the substrate.Type: ApplicationFiled: July 6, 2022Publication date: October 27, 2022Applicant: Winbond Electronics Corp.Inventors: Chang-Hung Lin, Feng-Jung Chang, Tzu-Ming Ou Yang
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Publication number: 20220345135Abstract: A monotonic counter memory system including a counter circuit and a memory circuit is provided. The counter circuit is configured to increase a count by one in response to a clock signal and output a count value of n bits, where n is a positive integer. The memory circuit includes a plurality of memory cells. The memory circuit is configured to store the count value. The stored count value changes one bit at each input count of the clock signal, and a bit switching time of the stored count value are smaller than 2n?1 times.Type: ApplicationFiled: April 26, 2021Publication date: October 27, 2022Applicant: Winbond Electronics Corp.Inventors: Chuen-Der Lien, Chi-Shun Lin
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Publication number: 20220342827Abstract: A memory-control logic, disposed in a memory circuit, is provided. The memory circuit includes a memory-cell array that is divided into a plurality of regions that include a damaged region. The memory-control logic includes a one-time-programmable (OTP) memory array, an array-control circuit, and an address-redirecting circuit. The array-control circuit programs a memory-size type of the memory-cell array, a region-failure flag corresponding to each region, and a redirecting mapping table corresponding to each region in the OTP memory array. The array-control circuit programs the redirecting mapping table corresponding to each region according to the memory-size type to direct the redirecting mapping table corresponding to each damaged region to non-repetitive good regions.Type: ApplicationFiled: September 7, 2021Publication date: October 27, 2022Applicant: Winbond Electronics Corp.Inventor: Chih-Chiang LAI
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Publication number: 20220344342Abstract: A method of manufacturing a DRAM includes proving a substrate having active regions. First bit line structures are buried in the substrate. Each of first bit line structures extends along a first direction. Every two of the first bit line structures are disposed between two neighboring ones of the active regions arranged along a second direction. A plurality of pillar structures are formed arranged along the first direction by dividing each of the active regions. Second bit line structures are formed. Each of the second bit line structures is located between the pillar structures of a corresponding one of the active regions and extends through the corresponding one of the active regions along the second direction to be disposed on the first bit line structures at two sides of the corresponding one of the active regions and be electrically connected to the first bit line structures below.Type: ApplicationFiled: July 14, 2022Publication date: October 27, 2022Applicant: Winbond Electronics Corp.Inventors: Kai Jen, Hao-Chuan Chang
