Abstract: A semiconductor memory apparatus including a data memory array, a parity memory array, a data read/write and correction part, a parity read/write part and a syndrome generating and decoding part is provided. The data read/write and correction part reads the data memory array and outputs a first application reading data. The parity read/write part reads the parity memory array and outputs a parity reading data. During a read cycle of an application data, the syndrome generating and decoding part generates a syndrome writing data according to the first application reading data, compares and decodes the syndrome writing data with the parity reading data to generate a verifying comparison data. In the same read cycle, the data read/write and correction part corrects the application data according to the verifying comparison data, and writes the corrected application data back to the data memory array and outputs a corresponding output data.

Abstract: A DRAM device and its manufacturing method are provided. The DRAM device includes an interlayer dielectric layer and capacitor units framed on a substrate. The interlayer dielectric layer has capacitor unit accommodating through holes and includes a first support layer, a composite dielectric layer, and a second support layer sequentially formed on the substrate. The composite dielectric layer includes at least one first insulating layer and second insulating layer alternately stacked. Each capacitor unit accommodating through hole forms a first opening in the second insulating layer and forms a second opening communicating with the first opening in the first insulating layer. The second opening is wider than the first opening. The capacitor units are formed in the capacitor unit accommodating through holes. The top of the capacitor unit is higher than the top surface of the interlayer dielectric layer and defines a recessed region.

Abstract: A semiconductor apparatus and a continuous readout method for improving prior continuous readout are provided. A flash memory includes: a NAND memory cell array, an input/output circuit, an ECC circuit, a controller, a word-line selection circuit, a page buffer/readout circuit, and a row selection circuit. When performing the continuous readout of pages, the controller performs an array readout of a first half page of a selection page on the memory cell array and an array readout of a second half page of the selection page on the memory cell array independently, and continuously outputs the respectively read data of the half pages in synchronization with a clock signal.

Abstract: A semiconductor memory device is provided to suppress occurrence of disturbance regardless of the position of the activated word line. The semiconductor memory device includes a plurality of word lines, a bit line, a plurality of memory cells connected to the bit line and one of the plurality of word lines, a sense amplifier connected to the bit line, and a control portion. The control portion is configured to control timing of activating the sense amplifier. When a position of an activated word line among the plurality of word lines is closer to the sense amplifier, the control portion controls the timing of activating the sense amplifier to be delayed more.

Abstract: A semiconductor device and method of forming the same are provided. The semiconductor device includes a first conductive line over a substrate and a memory structure over the first conductive line. The memory structure is electrically coupled to the first conductive line through a conductive via. A spacer layer is laterally aside the memory structure and covers sidewalls of the memory structure. A first dielectric layer is on the spacer layer and laterally aside the memory structure. A second dielectric layer is on the memory structure, the spacer layer and the first dielectric layer. A second conductive line penetrates through the second dielectric layer, the first dielectric layer and the spacer layer to electrically couple to the memory structure. The second conductive line includes a body part at least partially embedded in the second dielectric layer and an extension part underlying the body part and laterally protruding from a sidewall of the body part.

Abstract: An etching apparatus and an etching method thereof are provided. An end point detector detects a light intensity at a specific wavelength for light generated when an etching process is performed on a material to be processed, and generates an end point detection signal. The material to be processed includes a material layer and at least one mask layer formed on the material layer. A control device determines an etching completion time of the mask layer according to the end point detection signal, calculates a thickness of the mask layer according to the etching completion time, and adjusts an etching time of the material layer according to the thickness of the mask layer.

Abstract: A sense amplification device is provided. The sense amplification device includes a first sense amplifier, a second sense amplifier, and a third sense amplifier. An input terminal of the first sense amplifier is coupled to a first bit line. An input terminal of the second sense amplifier is coupled to a second bit line. The third sense amplifier has a differential input pair and a differential output pair, wherein a first input terminal of the differential input pair is coupled to an output terminal of the first sense amplifier, a second input terminal of the differential input pair is coupled to an output terminal of the second sense amplifier, a first output terminal of the differential output pair is coupled to the input terminal of the first sense amplifier, and a second output terminal of the differential output pair is coupled to the input terminal of the second sense amplifier.

Abstract: A semiconductor device and a method for manufacturing the same are provided. The method includes forming a plurality of bit line structures on a semiconductor substrate, wherein there is a plurality of trenches between the bit line structures. The method also includes forming a first oxide layer conformally covering the bit line structures and the trenches, and forming a photoresist material layer in the trenches and on the first oxide layer, wherein the photoresist material layer has an etch selectivity that is higher than that of the first oxide layer. The method further includes removing the photoresist material layer to form a plurality of capacitor contact holes between the bit line structures, and forming a capacitor contact in the capacitor contact holes.

Abstract: A memory apparatus embedded with a computing function and an operation method thereof are provided. The memory apparatus includes a memory array, a plurality of data flow controllers, a plurality of computation circuits, a data bus, and a control logic circuit. The memory array includes a plurality of block groups having a plurality of memory blocks. Each of the data flow controllers selects a transmission path of data of each memory block according to a corresponding one of the data flow control signals. In a computation mode, the computation circuit computes first data from the corresponding memory block. In a normal mode, second data is transmitted between the data bus and the corresponding memory block. The data flow controller transmits the first data from the corresponding memory block to the computation circuit according to the data flow control signal provided by the control logic circuit to compute the first data.

Abstract: A method for forming a semiconductor structure includes forming a gate electrode layer over a semiconductor substrate, forming a first spacer layer to cover a sidewall of the gate electrode layer, recessing the first spacer layer to expose an upper portion of the sidewall of the gate electrode layer, forming a metal material to cover an upper surface and the upper portion of the sidewall of the gate electrode layer; reacting a semiconductor material of the gate electrode layer with the metal material using an anneal process to form a silicide layer, and removing the metal material after the anneal process.

Abstract: A semiconductor device including a substrate and a capacitor is provided. The substrate includes a memory array region. The capacitor is located in the memory array region. The capacitor includes a first electrode, a second electrode, and an insulating layer. The first electrode is located on the substrate. The second electrode includes a first conductive layer and a metal layer. The first conductive layer is located on the first electrode. The metal layer is located on the first conductive layer. The metal layer exposes a portion of the first conductive layer. The insulating layer is located between the first electrode and the second electrode.

Abstract: A memory device includes a syndrome generating circuit and a plurality of latch circuits. The syndrome generating circuit includes a plurality of input terminals and plurality of logic circuits. The latch circuits are coupled to the syndrome generating circuit and are configured to set the input terminals of the syndrome generating circuit to a predetermined logic state according to a pre-charge reset signal. The latch circuits are configured to provide a plurality of data bits to the input terminals of the syndrome generating circuit after the input terminals of the syndrome generating circuit are set to the predetermined logic state. The syndrome generating circuit is configured to generate a syndrome bit based on the data bits by the logic circuits, wherein the syndrome bit indicates a presence of an error bit among the data bits.

Abstract: A manufacturing method for a memory structure including the following steps is provided. A bit line structure is formed on the substrate. A contact structure is formed on the substrate on one side of the bit line structure. A capacitor structure is formed on the contact structure. The capacitor structure includes a first electrode, a second electrode and an insulating layer. The first electrode is disposed on the contact structure in a misaligned manner. The first electrode includes a first bottom surface and a second bottom surface. The first bottom surface is lower than the second bottom surface. The first bottom surface is disposed on the contact structure. The second electrode is located on the first electrode. The insulating layer is disposed between the first electrode and the second electrode.

Abstract: A conductive wire structure including a first conductive wire and a second conductive wire is provided. The second conductive wire is located on one side of the first conductive wire. The first conductive wire includes a first conductive wire portion and a first pad portion. The first conductive wire portion extends in a first direction and has a first end and a second end. The first pad portion is connected to the first end of the first conductive wire portion. The second conductive wire includes a second conductive wire portion and a second pad portion. The second conductive wire portion extends in a second direction and has a third end and a fourth end. The third end is adjacent to the first end, and the fourth end is adjacent to the second end. The second pad portion is connected to the fourth end of the second conductive wire portion.

Abstract: A memory device includes a power supply device, a power-on-reset device, a memory array, and a memory controller. The power supply device converts the external supply voltage into an internal supply voltage. When the external supply voltage exceeds a first threshold, the power-on-reset device generates a reset signal. The power-on-reset device further raises the first threshold to a second threshold according to a deep-sleep signal. The memory array is supplied with the internal supply voltage. The memory controller is supplied with the internal supply voltage, accesses the memory array, and is reset according to the reset signal. When the memory controller operates in a deep-sleep mode, the memory controller generates the deep-sleep mode.

Abstract: A memory apparatus and a memory testing method are provided. The memory testing method includes: generating a plurality of testing patterns; writing each of the testing patterns to a plurality of selected memory blocks of the memory according to a setting address; reading out a plurality of pieces of readout data from the selected memory blocks according to the setting address; and comparing the plurality of pieces of readout data to generate a testing result.

Abstract: A buried word line structure, including a first isolation structure, a buried word line, a first barrier layer, a second barrier layer, a channel layer, and a second isolation structure, is provided. The first isolation structure is disposed in the substrate and has a trench. The buried word line is disposed on a bottom surface of the trench. The first barrier layer is disposed between the buried word line and a sidewall and the bottom surface of the trench. The second barrier layer covers a top surface of the buried word line and includes a main portion and an extension portion. The main portion is located on the buried word line, and the extension portion extends upward from periphery of the main portion. The channel layer is disposed on the first barrier layer and the second barrier layer. The second isolation structure is disposed on the channel layer.

Abstract: A resistive random access memory, including a first electrode layer and a second electrode layer disposed opposite to each other, a variable resistance layer located between the first electrode layer and the second electrode layer, an oxygen exchange layer located between the variable resistance layer and the second electrode layer, a vacancy-supplying layer surrounding a middle sidewall of the oxygen exchange layer; and a vacancy-driving electrode layer located on the vacancy-supply layer and surrounding an upper sidewall of the oxygen exchange layer, is provided. A method of fabricating the resistive random access memory is also provided.

Abstract: A semiconductor device including a substrate and a capacitor is provided. The substrate includes a memory array region. The capacitor is located in the memory array region. The capacitor includes a first electrode, a second electrode, and an insulating layer. The first electrode is located on the substrate. The second electrode includes a first conductive layer and a metal layer. The first conductive layer is located on the first electrode. The metal layer is located on the first conductive layer. The metal layer exposes a portion of the first conductive layer. The insulating layer is located between the first electrode and the second electrode.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes the following steps: forming a lining layer on a substrate and a plurality of gate structures; forming a first spacer layer on the lining layer; forming a stop layer on the first spacer layer; forming a first sacrificial layer on the stop layer and between the gate structures; removing a portion of the first sacrificial layer so that the top surface of the first sacrificial layer is located between the upper portions of the gate structures; forming a second spacer layer on the first sacrificial layer and the gate structures; and removing a portion of the second spacer layer so that the remaining second spacer layer is located between the upper portions of the gate structures.