Abstract: A memory device and a multiple cells error correction in a memory cell is provided. The memory device includes a plurality of memory cells and a memory control circuit. Each of the memory cells includes a first type physical cell and a second type physical cell. The memory control circuit is coupled to each of the memory cells. The memory control circuit writes a writing data into the first type physical cell and verifies the data stored in the first type physical cell is same as the writing data or not. The writing data is set and processed by performing a write operation. The memory control circuit writes the writing data into the second type physical cell when the data stored in the first type physical cell is not same as the writing data.

Abstract: A semiconductor storing apparatus capable of suppressing a peak current in a pre-charge operation and shortening a sense time is provided. A pre-charge method of a bit line of an NAND type flash memory includes: turning on a transistor (BLPRE) and supplying a pre-charge voltage to a sense node (SNS) at time (t1); turning on a transistor (BLCLAMP) connected to the sense node (SNS) and used for generating a clamp voltage and turning on a transistor (BLCN) connected to a node (BLS) at time (t2), turning on a transistor (BLSe/BLSo) connected between the node (BLS) and a bit line (GBLe/GBLo) at time (t3), and performing the pre-charge operation on the bit line.

Abstract: Provided is a manufacturing method of a memory device, including: forming a stacked layer on a substrate; patterning the stacked layer to form a plurality of openings in the stacked layer; forming a spacer on a sidewall of the openings; performing a first etching process by using the spacer as a mask to form a plurality of stack structures, wherein the spacer is embedded in the stack structures, such that a width of an upper portion of the stack structures is less than a width of a lower portion thereof; forming a dielectric layer on the stack structures and the spacer; and respectively forming a plurality of contact plugs on the substrate between the stack structures.

Abstract: A memory system includes memory chips connected to each other. Each of the memory chips includes a memory array, a read/write data strobe pin, a look-up table storage device, a chip number identification circuit, and a control logic circuit. The memory array stores data. The read/write data strobe pin is connected to read/write data strobe pins of other memory chips. The look-up table storage device stores a plurality of trimming shift values related to a number of chip connections in advance. The chip number identification circuit identifies a current number of chip connections according to a state information, and finds a selected trimming shift value from the look-up table storage device. The control logic circuit transmits a data signal in response to a clock signal, and adjusts a setup hold time between the clock signal and the data signal according to the selected trimming shift value.

Abstract: A flash memory capable of automatically releasing a deep power-down mode is provided. The flash memory includes: a standard command interface (I/F) circuit and a deep power-down mode (DPD) controller, operating through an external power voltage; and an internal circuit, operating through internal voltages supplied from voltage supply nodes. The DPD controller detects whether the flash memory is in the deep power-down mode when a standard command is inputted to the standard command I/F circuit and recovers the internal circuit from the DPD mode in the case where the deep power-down mode is detected. The standard command is executed after the internal circuit is recovered.

Abstract: An input receiver includes a first current source circuit, a second current source circuit, a first rail-to-rail amplifier circuit, a first inverter circuit, and a second inverter circuit. The first current source circuit adjusts an operating current flowing through a first node according to a first bias signal. The second current source circuit adjusts a ground current flowing through a second node according to a second bias signal. The first rail-to-rail amplifier circuit and the first inverter circuit are connected in parallel between the first node and the second node. The first rail-to-rail amplifier circuit receives an input signal and compares the input signal with a reference voltage and accordingly outputs an amplified signal. The second inverter circuit is coupled between an operating voltage and a ground voltage. The second inverter circuit generates an output signal according to an inverted signal outputted by the first inverter circuit.

Abstract: Provided is a semiconductor device including a substrate, a passivation layer, and a connector. The passivation layer is disposed on the substrate. The connector is embedded in the passivation. An interface of the connector in contact with the passivation layer is uneven, thereby improving the structural stability of the connector. A method of manufacturing the semiconductor is also provided.

Abstract: A non-volatile memory structure including a substrate, a plurality of charge storage layers, a first dielectric layer, and a control gate is provided. The charge storage layers are located on the substrate. An opening is provided between two adjacent charge storage layers. The first dielectric layer is located on the charge storage layers and on a surface of the opening. A bottom cross-sectional profile of the first dielectric layer located in the opening is a profile that is recessed on both sides. The control gate is located on the first dielectric layer and fills the opening.

Abstract: A NAND flash memory and manufacturing method thereof are provided. The NAND flash memory is capable of preventing a short circuit between gates extending along a vertical direction. The NAND flash memory includes a substrate; a plurality of channel stacks formed on the substrate and extending along an X direction; an interlayer dielectric formed between the channel stacks; a plurality of trenches formed apart from each other in the interlayer dielectric and arranged along a Y direction; an insulator stack including a charge storage layer formed to cover sidewalls of each of the trenches; and a plurality of conductive vertical gates elongating along the vertical direction in a space formed by the insulator stack in each of the trenches and extending along the Y direction.

Abstract: A discharge device is provided. The discharge device discharges an internal power of an electronic device. The discharge device includes a voltage regulation circuit, a charge storage circuit, a control signal generator and a discharge path. The voltage regulation circuit regulates the internal power to a regulated power. The charge storage circuit stores the regulated power. The control signal generator is configured to receive the regulated power and an external power, enabled according to the regulated power, and generating a control signal in response to a voltage level of the external power. The discharge path is configured to receive the internal power, and turned on according to the control signal to discharge the internal power.

Abstract: The present invention includes a semiconductor structure having a substrate, a gate structure, and a first spacer. The gate structure includes a floating gate structure, an inter-gate dielectric layer, and a control gate structure. The floating gate structure is disposed on the substrate. The inter-gate dielectric layer is disposed on the floating gate structure. The control gate structure is deposited on the inter-gate dielectric layer and includes an electrode layer, a contact layer and a cap layer. The electrode layer is disposed on the inter-gate dielectric layer. The contact layer is disposed on the electrode layer. The cap layer is disposed on the contact layer. The first spacer is disposed on sidewalls of the control gate structure and covers the electrode layer, the contact layer, and the cap layer. Furthermore, the bottom surface of the first spacer is disposed between the bottom surface and the top surface of the electrode layer.

Abstract: An integrated circuit, a crack status detector and a crack status detection method are provided. The crack status detector includes a detection ring, multiple switches, and a current measuring circuit. The detection ring is formed by multiple conductive wire segments coupled in series. The detection ring is disposed adjacent to a side of at least one guard ring in the integrated circuit. The detection ring has a first endpoint and a second endpoint to respectively receive a first reference voltage and a second reference voltage. Each of the switches is disposed between two adjacent conductive wire segments. The switches are respectively turned on or cut off according to multiple control signals. The current measuring circuit transmits the control signals and measures a current on the detection ring according to a turned-on or cut-off status of each of the switches, so as to detect a crack status of the integrated circuit.

Abstract: An impedance calibration circuit is provided. The impedance calibration circuit includes a first calibration circuit, a second calibration circuit and a control circuit. The first calibration circuit is adapted to be coupled to an external resistor through a calibration pad, and generate a first voltage according to a first control signal and a resistance value of the external resistor. The second calibration circuit generates a second voltage according to the first control signal and a second control signal. The control circuit is configured to compare the first voltage and a reference voltage to obtain a first comparison result, and compare the first voltage and the second voltage to obtain a second comparison result, and generate the first control signal according to the first comparison result, and generate the second control signal according to the second comparison result.

Abstract: The invention provides a memory apparatus including a memory cell array and a voltage generation circuit. The voltage generation circuit is electrically connected to the memory cell array and includes an active voltage circuit and a sensing circuit. The active voltage circuit is configured to output an operating voltage to the memory cell array when the memory apparatus is in an active mode. The sensing circuit is configured to sense the operating voltage when the memory apparatus is in a standby mode and briefly activate the active voltage circuit to pull up the operating voltage after the operating voltage drops below a threshold.

Abstract: A resistive random access memory (RRAM) device is provided. The RRAM device includes a gate structure on a substrate, and a source region and a drain region disposed on opposite sides of the gate structure on the substrate. The source region includes a semiconductor bulk, and the drain region includes a plurality of semiconductor fins adjacent to the semiconductor bulk, wherein the semiconductor fins are separated from each other by an isolation layer. The RRAM device further includes a plurality of RRAM units, wherein each of the RRAM units electrically contacts one of the semiconductor fins.

Abstract: A memory device includes: a resistive switching layer, a conductive pillar, a barrier layer, a word line, a plurality of resistive layers, and a plurality of bit lines. The resistive switching layer is shaped as a cup and has an inner surface to define an opening. The conductive pillar is disposed in the opening. The barrier layer is disposed between the resistive switching layer and the conductive pillar. The word line is electrically connected to the conductive pillar. The resistive layers are respectively distributed on an outer surface of the resistive switching layer. The bit lines are electrically connected to the resistive layers, respectively.

Abstract: A flash memory device and its manufacturing method are provided. The flash memory device includes a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, a first polycrystalline silicon layer and a second polycrystalline silicon layer. The first dielectric layer is formed on the substrate located in a first region of a peripheral region, the second dielectric layer is formed on the substrate located in a second region of the peripheral region, and the third dielectric layer is formed on the substrate located in an array region. A bottom surface of the third dielectric layer is lower than a bottom surface of the second dielectric layer. The first polycrystalline silicon layer is formed on the first and the second dielectric layers. The second polycrystalline silicon layer is formed on the third dielectric layer.

Abstract: A control circuit of delay lock loop and a control method thereof are provided. The control circuit includes a power status detector, a voltage comparator, an enable signal generator and a control signal generator. The power status detector detects a transition edge of a clock enable signal to generate a trigger signal corresponding to a variation of an operation power. The voltage comparator compares the operation power with a reference voltage to generate a comparison result. The enable signal generator sets an enable signal to an active state according to the trigger signal and sets the enable signal to a non-active state according to the comparison result. The control signal generator outputs a control clock to generate a control signal when the enable signal is in the active state.

Abstract: A data writing method is provided. According to the present application, the data writing method includes steps of receiving an expected data, performing a plurality of readings on a target storage unit to obtain a plurality of read data; determining whether the plurality of read data are the same as the expected data respectively to generate a plurality of comparison results; and performing a writing operation procedure on the target storage unit according to the plurality of comparison results and the expected data.

Abstract: A patterning method includes sequentially forming a target layer, a first layer, a second layer, a third layer, and a first mask pattern. A first spacer is formed on a sidewall of the first mask layer. The first mask pattern is removed to form a plurality of peripheral openings surrounding a central opening in the first spacer. A rounding process is performed to round the peripheral openings and form a second mask pattern. A portion of the second layer is removed by using the second mask pattern as a mask, so as to form a third mask pattern. A second spacer is formed in the third mask pattern. The third mask pattern is removed. Portions of the first layer and the target layer are removed by using the second spacer as a mask.