Patents Assigned to Winbond Electronics Corporation
  • Publication number: 20160189789
    Abstract: Serial NAND flash memory may be provided with the characteristics of continuous read of the memory across page boundaries and from logically contiguous memory locations without wait intervals, while also being clock-compatible with the high performance serial flash NOR (“HPSF-NOR”) memory read commands so that the serial NAND flash memory may be used with controllers designed for HPSF-NOR memory. Serial NAND flash memory having these compatibilities is referred to herein as high-performance serial flash NAND (“SPSF-NAND”) memory. Since devices and systems which use HPSF-NOR memories and controllers often have extreme space limitations, HPSF-NAND may also be provided with the same physical attributes of low pin count and small package size of HPSF-NOR memory for further compatibility. HPSF-NAND memory is particularly suitable for code shadow applications, even while enjoying the low “cost per bit” and low per bit power consumption of a NAND memory array at higher densities.
    Type: Application
    Filed: March 9, 2016
    Publication date: June 30, 2016
    Applicant: Winbond Electronics Corporation
    Inventors: Robin John Jigour, Hui Chen, Oron Michael
  • Patent number: 9367392
    Abstract: A continuous read operation may be achieved by using a data buffer having a partitioned data register and a partitioned cache register, user configurable internal ECC associated with the cache register, and fast bad block management. During a data read operation, the ECC status may be indicated by ECC status bits. The status (1:1), for example, may indicate for the Continuous Read Mode that the entire data output contains more than 4 bits errors/page in multiple pages. However, one may wish to know the ECC status of each page or of each page partition. For the former, the ECC status for the entire page may be determined and made in the status register at the end of the output of the page. For the latter, the ECC status of each page partition may be determined and output before output of the corresponding page partition.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: June 14, 2016
    Assignee: WINBOND ELECTRONICS CORPORATION
    Inventor: Oron Michael
  • Patent number: 9348995
    Abstract: A memory device package encloses two separate die, one being a standard nonvolatile memory integrated circuit (“IC”) die, and the other being any suitable authentication IC die. Either die may be stacked upon the other, or the die may be placed side-by-side. The external contacts may correspond to the power and signal requirements of the standard nonvolatile memory IC die so that the pin-out of the memory device package may present a standard pinout. The power and signal requirements of the authentication IC die may be satisfied with some or all of the pins for the nonvolatile memory integrated circuit die, or with other unused pins of the device package. One or more additional external contacts may be added exclusively for the authentication integrated circuit die. One or more signals may be dedicated as between the standard nonvolatile memory IC die and the authentication IC die.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: May 24, 2016
    Assignee: WINBOND ELECTRONICS CORPORATION
    Inventors: Ming-Huei Shieh, Krishna Chandra Shekar, Hui Chen
  • Patent number: 9343162
    Abstract: A non-volatile memory (NVM) device includes an NVM array, which is configured to store data, and control logic. The control logic is configured to receive data values for storage in the NVM array, and to write at least some of the received data values to the NVM array and simultaneously to write complements of the at least some of the received data values.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: May 17, 2016
    Assignee: WINBOND ELECTRONICS CORPORATION
    Inventors: Nir Tasher, Valery Teper, Dennis Chin Cheng, Boaz Tabachnik
  • Patent number: 9324450
    Abstract: Serial NAND flash memory may be provided with the characteristics of continuous read of the memory across page boundaries and from logically contiguous memory locations without wait intervals, while also being clock-compatible with the high performance serial flash NOR (“HPSF-NOR”) memory read commands so that the serial NAND flash memory may be used with controllers designed for HPSF-NOR memory. Serial NAND flash memory having these compatibilities is referred to herein as high-performance serial flash NAND (“SPSF-NAND”) memory. Since devices and systems which use HPSF-NOR memories and controllers often have extreme space limitations, HPSF-NAND may also be provided with the same physical attributes of low pin count and small package size of HPSF-NOR memory for further compatibility. HPSF-NAND memory is particularly suitable for code shadow applications, even while enjoying the low “cost per bit” and low per bit power consumption of a NAND memory array at higher densities.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: April 26, 2016
    Assignee: WINBOND ELECTRONICS CORPORATION
    Inventors: Robin John Jigour, Hui Chen, Oron Michael
  • Patent number: 9275738
    Abstract: A flash memory device may operate from two supply voltages, one being provided externally, and the other being generated within the flash memory device from the external supply voltage. The flash memory device may be provided with a selectable-level buffer for interfacing with either low supply voltage or high supply voltage integrated circuits. To provide even greater flexibility, the flash memory device may be provided with the capability of receiving a second supply voltage from an external source, which may take precedence over the internally-generated second supply voltage or may be combined with the internally-generated second supply voltage.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: March 1, 2016
    Assignee: Winbond Electronics Corporation
    Inventors: Jongjun Kim, Eungjoon Park
  • Publication number: 20160034351
    Abstract: The NAND flash memory array in a memory device may be programmed using a cache program execute technique for fast performance. The memory device includes a page buffer, which may be implemented as a cache register and a data register. Program data may be loaded to the cache register, where it may be processed by an error correction code (“ECC”) circuit. Thereafter, the ECC processed data in the cache register may be replicated to the data register and used to program the NAND flash memory array. Advantageously, immediately after the ECC processed data in the cache register is replicated to the data register, the cache register may be made available for other operations. Of particular benefit is that a second page of program data may be loaded into the cache register and ECC processed while the first page of program data is being programmed into the NAND flash memory array.
    Type: Application
    Filed: July 31, 2014
    Publication date: February 4, 2016
    Applicant: Winbond Electronics Corporation
    Inventor: Oron Michael
  • Publication number: 20160034346
    Abstract: A continuous read operation may be achieved by using a data buffer having a partitioned data register and a partitioned cache register, user configurable internal ECC associated with the cache register, and fast bad block management. During a data read operation, the ECC status may be indicated by ECC status bits. The status (1:1), for example, may indicate for the Continuous Read Mode that the entire data output contains more than 4 bits errors/page in multiple pages. However, one may wish to know the ECC status of each page or of each page partition. For the former, the ECC status for the entire page may be determined and made in the status register at the end of the output of the page. For the latter, the ECC status of each page partition may be determined and output before output of the corresponding page partition.
    Type: Application
    Filed: August 1, 2014
    Publication date: February 4, 2016
    Applicant: WINBOND ELECTRONICS CORPORATION
    Inventor: Oron Michael
  • Publication number: 20160034352
    Abstract: A page buffer suitable for continuous page read may be implemented with a partitioned data register, a partitioned cache register, and a suitable ECC circuit. The partitioned data register, partitioned cache register, and associated ECC circuit may also be used to realize a substantial improvement in the page read operation by using a modified Page Data Read instruction and/or a Buffer Read instruction, including in some implementations the use of a partition busy bit.
    Type: Application
    Filed: July 31, 2014
    Publication date: February 4, 2016
    Applicant: WINBOND ELECTRONICS CORPORATION
    Inventors: Oron Michael, Anil Gupta
  • Patent number: 9245590
    Abstract: Any number of Serial Peripheral Interface (“SPI”) flash memory die may be stacked and packaged using any desired multi-chip packaging technique to realize any one or combination of various capabilities such as low per-bit cost, high density storage, code shadowing to RAM, and fast random access for “execute in place” applications, while preserving the advantages of the SPI interface. During device manufacture, each of the stacked die is assigned a unique identifier or “Die ID” relative to the other stacked die in the package. During normal operations, the unique Die IDs are used by a Die Select instruction to enable one of the stacked die to respond to subsequent instructions on the SPI interface, while disabling the other stacked die in the package from responding to subsequent instructions but for certain “Universal” instructions which include the Die Select instruction. Concurrent operations by the stacked die are supported.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: January 26, 2016
    Assignee: Winbond Electronics Corporation
    Inventors: Hui Chen, Teng Su
  • Patent number: 9223960
    Abstract: An apparatus for detecting tampering with a clock of a state-machine, comprising, a master state-machine having master states and driven by a master clock, the master states being switchable responsive to events, and an auxiliary state-machine having auxiliary states and driven by an auxiliary clock synchronous with the master clock, the auxiliary states being switchable responsive to a signal generated based at least on said events, consequently establishing a correspondence between the master states and the auxiliary states, thus ensuing that subsequent to tampering with the master clock the correspondence between the master states and the auxiliary states become discordant, thereby indicating that the master clock has been tampered with.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: December 29, 2015
    Assignee: WINBOND ELECTRONICS CORPORATION
    Inventors: Uri Kaluzhny, Tsachi Weiser, Valery Teper, Nir Tasher
  • Patent number: 9214211
    Abstract: Respective die IDs are determined for a plurality of memory die commonly packaged as a memory device based on their respective Unique Identifiers (“UIDs”). An external controller initiates an internal Die ID (“DID”) determination process in which each die eventually asserts a signal on its inter-die signaling pin after a number of clocks as determined by its UID, and assigns itself a Die ID based on the number of signals asserted by other die prior to its own signaling response. Each die keeps track of the number of signals asserted by the other die prior to its own signaling response, as well as, optionally, the total number of signals on the signaling pin to determine the package die count for the device.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: December 15, 2015
    Assignee: WINBOND ELECTRONICS CORPORATION
    Inventor: Johnny Chan
  • Publication number: 20150346246
    Abstract: A monolithic integrated circuit device may include a supply voltage glitch detector for detecting improper supply voltage conditions. Advantageously, the detection threshold of the supply voltage glitch detector is adaptively set based on the mode of operation of the device or a particular part of the device, which is internally known to the device based on certain inputs received by the device, such as commands, interrupts, control signals, and so forth.
    Type: Application
    Filed: June 2, 2014
    Publication date: December 3, 2015
    Applicant: WINBOND ELECTRONICS CORPORATION
    Inventors: Nir Tasher, Valery Teper, Dennis Chin Cheng, Koying Huang
  • Publication number: 20150332747
    Abstract: Respective die IDs are determined for a plurality of memory die commonly packaged as a memory device based on their respective Unique Identifiers (“UIDs”). An external controller initiates an internal Die ID (“DID”) determination process in which each die eventually asserts a signal on its inter-die signaling pin after a number of clocks as determined by its UID, and assigns itself a Die ID based on the number of signals asserted by other die prior to its own signaling response. Each die keeps track of the number of signals asserted by the other die prior to its own signaling response, as well as, optionally, the total number of signals on the signaling pin to determine the package die count for the device.
    Type: Application
    Filed: May 15, 2014
    Publication date: November 19, 2015
    Applicant: WINBOND ELECTRONICS CORPORATION
    Inventor: Johnny Chan
  • Publication number: 20150287477
    Abstract: A method in a memory device that operates in a testing mode, includes receiving a vector to be written to the memory device. The vector is written to the memory device only if the vector belongs to a predefined set of test vectors. If the vector does not belong to the set of test vectors, the vector is converted to one of the test vectors, and the converted vector is written to the memory device.
    Type: Application
    Filed: April 3, 2014
    Publication date: October 8, 2015
    Applicant: Winbond Electronics Corporation
    Inventors: Nir Tasher, Uri Kaluzhny, Tsachi Weiser, Valery Teper
  • Patent number: 9128822
    Abstract: Certain functions relating to creation and use of a look-up table for bad block mapping may be implemented “on chip” in the memory device itself, that is on the same die in an additional circuit, or even within the command and control logic of the memory device, so as to reduce the overhead. Moreover, the on-chip implementation of the look-up table may be tightly integrated with other functions of the command and control logic to enable powerful new commands for NAND flash memory, such as a continuous read command and variations thereof.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: September 8, 2015
    Assignee: WINBOND ELECTRONICS CORPORATION
    Inventors: Oron Michael, Robin John Jigour, Anil Gupta
  • Publication number: 20150248921
    Abstract: Any number of Serial Peripheral Interface (“SPI”) flash memory die may be stacked and packaged using any desired multi-chip packaging technique to realize any one or combination of various capabilities such as low per-bit cost, high density storage, code shadowing to RAM, and fast random access for “execute in place” applications, while preserving the advantages of the SPI interface. During device manufacture, each of the stacked die is assigned a unique identifier or “Die ID” relative to the other stacked die in the package. During normal operations, the unique Die IDs are used by a Die Select instruction to enable one of the stacked die to respond to subsequent instructions on the SPI interface, while disabling the other stacked die in the package from responding to subsequent instructions but for certain “Universal” instructions which include the Die Select instruction. Concurrent operations by the stacked die are supported.
    Type: Application
    Filed: February 28, 2014
    Publication date: September 3, 2015
    Applicant: Winbond Electronics Corporation
    Inventors: Hui Chen, Teng Su
  • Publication number: 20150228342
    Abstract: A flash memory device may operate from two supply voltages, one being provided externally, and the other being generated within the flash memory device from the external supply voltage. The flash memory device may be provided with a selectable-level buffer for interfacing with either low supply voltage or high supply voltage integrated circuits. To provide even greater flexibility, the flash memory device may be provided with the capability of receiving a second supply voltage from an external source, which may take precedence over the internally-generated second supply voltage or may be combined with the internally-generated second supply voltage.
    Type: Application
    Filed: April 27, 2015
    Publication date: August 13, 2015
    Applicant: Winbond Electronics Corporation
    Inventors: Jongjun Kim, Eungjoon Park
  • Publication number: 20150199128
    Abstract: A flash memory for code and data storage includes a code memory array having fast read access and suitability for execute in place, a data memory array having the characteristics of low bit cost and high density storage, and a suitable interface to provide access to both the code and data. The code memory array may be a NOR array or a performance-enhanced NAND array. The memory may be implemented in a single chip package or multi-chip package solution.
    Type: Application
    Filed: March 27, 2015
    Publication date: July 16, 2015
    Applicant: Winbond Electronics Corporation
    Inventors: Eungjoon Park, Robin John Jigour, Jooweon Park, Masaru Yano
  • Patent number: 9082499
    Abstract: A Flash memory device operable under a single-bit or multiple-bit serial protocol is provided with a capability to determine the address boundary condition of an application from the address field of an address boundary configurable (“ABC”) read command. Based on the identified address boundary condition, the Flash memory device may perform multiple sensing of the memory array as required by the ABC read command using optimal internal sense times for each sensing. The number of dummy bytes may be specified for the read command in advance by the user, based on the address boundary of the application and the desired frequency of operation of the Flash memory device. Therefore, Flash memory device read performance is improved both by minimizing the number of dummy bytes in the read command and by optimizing the internal sense times for the read operation.
    Type: Grant
    Filed: April 10, 2014
    Date of Patent: July 14, 2015
    Assignee: WINBOND ELECTRONICS CORPORATION
    Inventor: Oron Michael