Abstract: A high-speed low-latency interconnect interface (HLII) for silicon interposer interconnection is provided. The HLII is configured to perform large-scale input/output (I/O) interconnection on a silicon interposer, and includes a physical link (PL) and an LL (LL). The LL receives a data signal, a configuration signal, and a control signal of logical resource inside a chiplet, and can complete data conversion, parity check, training, channel repair, instruction stream generation, and other functions for the PL. The PL receives and transmits a data signal converted by the LL. The PL includes a high-speed I/O port, a first input first output (FIFO), and related control logic. The high-speed I/O port of the PL is compatible with both a double date rate (DDR) transmission mode and a single data rate (SDR) transmission mode.

Abstract: An apparatus and a method for testing a multi-channel high-speed low-latency interconnect interface (HLII) for a silicon interposer are provided. The apparatus includes: a standard test port configured to exchange a test instruction; an asynchronous bypass port configured to directly access an input/output (I/O) port of a channel of a physical layer of the interconnection interface; a built-in self-test (BIST) engine configured to implement inter-level loopback testing and data verification; a redundant data channel configured to repair a damaged data channel; and a delay chain testing circuit configured to test a function and linearity of a delay chain. The apparatus embeds test and repair logic into the physical layer and a link layer, achieving internal test control without any external controller. In this way, a sample can be tested and quickly screened to ensure its performance.

Abstract: An FPGA for implementing data transmission by using a built-in edge module is provided. The FPGA is provided with a built-in edge module. A read port of each resource module connected to the edge module in the FPGA is separately connected to a winding architecture and the edge module, and/or a write port of each resource module connected to the edge module in the FPGA is separately connected to the winding architecture and the edge module. The edge module includes a read/write controller and a cache unit. The read/write controller simultaneously reads data from read ports of a plurality of resource modules and temporarily stores the read data in the cache unit. Alternatively, the read/write controller simultaneously writes temporarily stored data in the cache unit into write ports of the plurality of resource modules.

Abstract: A chip state monitoring circuit based on a self-balancing differential signal integration and amplification circuit is provided. The chip state monitoring circuit is built in a chip, and can sense a state signal of the chip and transmit the state signal to a chip configuration circuit after performing amplification and analog-to-digital conversion, such that the chip configuration circuit can monitor a state and provide a timely feedback or response, thereby improving reliability and a service life of the chip. The chip state monitoring circuit uses a brand new self-balancing differential signal integration and amplification circuit. With a built-in positive coefficient integration network and negative coefficient balancing network, the self-balancing differential signal integration and amplification circuit can perform amplification by required times to enter a self-balancing stable state, thereby achieving fixed-multiple amplification without timed reading. The control method is simple and flexible.

Abstract: A configuration control circuit of a flash-type FPGA capable of suppressing programming interference is provided. The configuration control circuit adds a programming selection circuit compared with a conventional configuration control circuit. When a programming operation is performed on a flash memory cell located in a target row and a target column, the programming selection circuit controls a path between a programming bit line (BL) voltage and a BL voltage obtaining terminal of the flash memory cell located in the target row and the target column to be turned on, and a path between the programming BL voltage and a BL voltage obtaining terminal of a flash memory cell located in another row and the target column to be turned off.

Abstract: A routing node scheduling method for an NOC in an FPGA is used when a plurality of input ports each have a data packet to be transmitted to a routing node at the same time. A scheduling controller within the routing node is used to enable each input port according to a predetermined scheduling order, and the routing node receives a data packet through the enabled input port. In addition, quantities of times at least two input ports are enabled are different in one scheduling cycle, which means that the scheduling controller implements biased scheduling control over each input port, allowing different input ports to transmit data packets at different frequencies. This can increase a quantity of times an input port with high communication importance is enabled, making a data packet at the input port be transmitted more timely and achieving better transmission efficiency. The scheduling method can well match transmission requirements of different services to achieve optimal transmission performance of an NOC.

Abstract: A phase interpolation circuit with a high linearity includes a first parallel circuit constituted by M phase interpolation units, and a second parallel circuit constituted by N phase interpolation units. An input terminal of the first parallel circuit is connected to a first clock input terminal and grounded via a first capacitor. An input terminal of the second parallel circuit is connected to a second clock input terminal and grounded via a second capacitor. An output terminal of the first parallel circuit and an output terminal of the second parallel circuit are connected to a clock output terminal and grounded via a zeroth capacitor. A circuit parameter of each phase interpolation unit corresponds to a target output weight respectively. The target output weight of each phase interpolation unit is determined by iteration to minimize a phase difference between all output clock signals of the phase interpolation circuit.

Abstract: The present disclosure discloses an FPGA device forming a network-on-chip by using a silicon connection layer. An active silicon connection layer is designed inside the FPGA device. A silicon connection layer interconnection framework is arranged inside the silicon connection layer. Bare die functional modules inside an FPGA bare die are connected to the silicon connection layer interconnection framework to jointly form the network-on-chip. Each bare die functional module and a network interface and a router that are in the silicon connection layer interconnection framework form an NOC node. The NOC nodes intercommunicate with each other, so that the bare die functional modules in the FPGA bare die without a built-in NOC network can achieve efficient intercommunication by means of the silicon connection layer interconnection framework, reducing the processing difficulty on the basis of improving the data transmission bandwidth and performance inside the FPGA device.

Abstract: The present disclosure discloses an FPGA device for implementing a network-on-chip transmission bandwidth expansion function, and relates to the technical field of FPGAs. When a predefined functional module with built-in hardcore IP nodes is integrated in an FPGA bare die, soft-core IP nodes are configured and formed by using logical resource modules in the FPGA bare die and are connected to the hardcore IP nodes to form an NOC network structure, so as to increase nodes and expand the transmission bandwidth of the predefined functional module. On the other hand, the soft-core IP nodes can be additionally connected to input and output signals in the predefined functional module and also can expand the transmission bandwidth of the predefined functional module.

Abstract: A field-programmable gate array (FPGA) for using a configuration shift chain to implement a multi-bitstream function includes a bitstream control circuit, a multi-bitstream configuration shift chain and a configurable module. The FPGA enables multi-bitstream storage configuration bits to latch configuration bitstreams by adjusting a circuit structure of a multi-bitstream configuration shift chain in a combination of a control logic of a bitstream control circuit for the multi-bitstream configuration shift chain, and outputs one latched configuration bitstream from a configuration output terminal to a configurable module through each multi-bitstream storage configuration bit as required, so that the configurable module implements a logic function corresponding to the configuration bitstream outputted by the multi-bitstream configuration shift chain.

Abstract: A field programmable gate array (FPGA) for improving the reliability of a key configuration bitstream by reusing a buffer memory includes a configuration buffer, a configuration memory and a control circuit. The configuration memory includes N configuration blocks. The FPGA stores a key configuration chain by using the configuration buffer and ensures correct content of the key configuration chain through an error correcting code (ECC) check function of the configuration buffer, so that when the FPGA runs normally, a control circuit reads the key configuration chain in the configuration buffer at an interval of a predetermined time and writes the key configuration chain into a corresponding configuration block to update the key configuration chain, thereby ensuring accuracy of the content of the key configuration chain and improving running reliability of the FPGA.

Abstract: A field programmable gate array (FPGA) with an automatic error detection and correction function for programmable logic modules includes an error checking and correction device. A check code generation circuit in the error checking and correction device performs error correcting code (ECC) encoding according to input data of corresponding programmable logic registers to generate a check code, and refreshes and writes the check code into a check code register according to a clock signal. A check circuit checks outputs of the programmable logic registers and check code registers to generate syndromes for implementing checking. A decoding circuit generates upset signals corresponding to the syndromes according to a trigger enable pulse of a trigger circuit to control a fault register to directly and asynchronously upset content to correct the error. A circuit area is greatly reduced by using the FPGA, thereby improving a degree of integration of the circuit.

Abstract: In an anti-fuse memory reading circuit with controllable reading time, a reading time control circuit generates a control signal corresponding to reading time. Based on a clock signal, a programmable reading pulse generation circuit generates a reading pulse with a pulse width corresponding to the control signal. Based on the reading pulse and the control signal, the reading amplification circuit selects a pull-up current source corresponding to the reading time, pulls up a voltage on a bit line (BL) of an anti-fuse memory cell, reads data stored in the anti-fuse memory cell starting from a rising edge of the reading pulse, and latches the read data at a falling edge of the reading pulse. The anti-fuse memory reading circuit can generate a reading pulse with a corresponding pulse width and a pull-up current source with a corresponding size based on the required reading time.

Abstract: A delay adjustment cell is disposed in a channel of at least one regional clock of a chip clock architecture, and the delay adjustment cell includes a plurality of parallel delay paths with different delay values. The delay adjustment cell gates one of the delay paths based on an obtained configuration signal such that a connected regional clock has a corresponding target delay, and a target delay of each regional clock corresponds to a clock skew mode of the programmable logic chip. A clock skew between different regional clocks is adjusted by controlling the gated delay path in the delay adjustment cell, such that a clock skew of the chip can be adjusted in a relatively large range. Under the same resource configuration, different path choices of the delay adjustment cell lead to different clock skews to meet different clock skew modes in different application scenarios.

Abstract: A configuration circuit of a flash FPGA for realizing external monitoring and configuration is provided. In the configuration circuit, a positive high-voltage output terminal of a positive high-voltage charge pump is connected to a positive high-voltage external monitoring port through a positive high-voltage bidirectional switch circuit, and the positive high-voltage output terminal of a positive high-voltage charge pump is further configured as a positive output end of a voltage supply circuit. A negative high-voltage output terminal of a negative high-voltage charge pump is connected to a negative high-voltage external monitoring port through a negative high-voltage bidirectional switch circuit, and the negative high-voltage output terminal of a negative high-voltage charge pump is further configured as a negative output end of the voltage supply circuit. Based on a received mode adjustment signal, a mode control circuit controls to enter an external monitoring mode or an external configuration mode.

Abstract: A logic process-based level conversion circuit of a flash flash field programmable gate array (FPGA) performs three-stage level conversion by using three conversion modules. A first-stage conversion module is configured to convert an input first signal of a VDD-GND voltage domain into a second signal of a VP1-GND voltage domain, an intermediate-stage conversion module is configured to convert the input second signal of the VP1-GND voltage domain into a third signal of a VP1-VN voltage domain, and a drive-stage conversion module is configured to convert the input third signal of the VP1-VN voltage domain into a drive signal of a VP2-VN voltage domain and output a drive word line. The logic process-based level conversion circuit reduces the pressure of conversion at each stage, ensures a capability of driving the next stage, increases the conversion speed, and provides a large driving capability at the last stage.

Abstract: In an anti-fuse programming control circuit based on a master-slave charge pump structure, a master charge pump module obtains an external voltage and is connected to a plurality of slave charge pump modules. Each slave charge pump module is connected to an anti-fuse bank. The distance between the layout position of each slave charge pump module and the layout position of the connected anti-fuse bank does not exceed a predetermined distance. Based on a programming voltage output by each slave charge pump module to the connected anti-fuse bank, the feedback network outputs a feedback signal corresponding to the slave charge pump module to the master charge pump module. Based on the feedback signal corresponding to each slave charge pump module, the master charge pump module adjusts a master drive signal provided to the slave charge pump module to stabilize the programming voltage output by the slave charge pump module.

Abstract: A field programmable gate array (FPGA) for improving the reliability of a key configuration bitstream by reusing a buffer memory includes a configuration buffer, a configuration memory and a control circuit. The configuration memory includes N configuration blocks. The FPGA stores a key configuration chain by using the configuration buffer and ensures correct content of the key configuration chain through an error correcting code (ECC) check function of the configuration buffer, so that when the FPGA runs normally, a control circuit reads the key configuration chain in the configuration buffer at an interval of a predetermined time and writes the key configuration chain into a corresponding configuration block to update the key configuration chain, thereby ensuring accuracy of the content of the key configuration chain and improving running reliability of the FPGA.

Abstract: A field-programmable gate array (FPGA) for using a configuration shift chain to implement a multi-bitstream function includes a bitstream control circuit, a multi-bitstream configuration shift chain and a configurable module. The FPGA enables multi-bitstream storage configuration bits to latch configuration bitstreams by adjusting a circuit structure of a multi-bitstream configuration shift chain in a combination of a control logic of a bitstream control circuit for the multi-bitstream configuration shift chain, and outputs one latched configuration bitstream from a configuration output terminal to a configurable module through each multi-bitstream storage configuration bit as required, so that the configurable module implements a logic function corresponding to the configuration bitstream outputted by the multi-bitstream configuration shift chain.

Abstract: A field-programmable gate array (FPGA) for implementing data transfer between different configuration and application processes includes a programmable logic resource, a configuration memory and a hardware memory. A write port and a read port of the hardware memory are respectively connected to a programmable logic resource by a wiring path, data in the hardware memory remains unchanged at an abnormal running stage of the programmable logic resource, and running data generated by a user design in a configuration and application process can be transferred to a user design in a subsequent configuration and application process by using the hardware memory for use during running. This enlarges functions of the FPGA, and meets application requirements in a plurality of different scenarios.