Abstract: A field-programmable gate array (FPGA) for implementing data transfer between different configuration and application processes includes a programmable logic resource, a configuration memory and a hardware memory. A write port and a read port of the hardware memory are respectively connected to a programmable logic resource by a wiring path, data in the hardware memory remains unchanged at an abnormal running stage of the programmable logic resource, and running data generated by a user design in a configuration and application process can be transferred to a user design in a subsequent configuration and application process by using the hardware memory for use during running. This enlarges functions of the FPGA, and meets application requirements in a plurality of different scenarios.

Abstract: A phase interpolation circuit with a high linearity includes a first parallel circuit constituted by M phase interpolation units, and a second parallel circuit constituted by N phase interpolation units. An input terminal of the first parallel circuit is connected to a first clock input terminal and grounded via a first capacitor. An input terminal of the second parallel circuit is connected to a second clock input terminal and grounded via a second capacitor. An output terminal of the first parallel circuit and an output terminal of the second parallel circuit are connected to a clock output terminal and grounded via a zeroth capacitor. A circuit parameter of each phase interpolation unit corresponds to a target output weight respectively. The target output weight of each phase interpolation unit is determined by iteration to minimize a phase difference between all output clock signals of the phase interpolation circuit.

Abstract: A field programmable gate array (FPGA) with an automatic error detection and correction function for programmable logic modules includes an error checking and correction device. A check code generation circuit in the error checking and correction device performs error correcting code (ECC) encoding according to input data of corresponding programmable logic registers to generate a check code, and refreshes and writes the check code into a check code register according to a clock signal. A check circuit checks outputs of the programmable logic registers and check code registers to generate syndromes for implementing checking. A decoding circuit generates upset signals corresponding to the syndromes according to a trigger enable pulse of a trigger circuit to control a fault register to directly and asynchronously upset content to correct the error. A circuit area is greatly reduced by using the FPGA, thereby improving a degree of integration of the circuit.