Abstract: A configuration circuit of a flash FPGA for realizing external monitoring and configuration is provided. In the configuration circuit, a positive high-voltage output terminal of a positive high-voltage charge pump is connected to a positive high-voltage external monitoring port through a positive high-voltage bidirectional switch circuit, and the positive high-voltage output terminal of a positive high-voltage charge pump is further configured as a positive output end of a voltage supply circuit. A negative high-voltage output terminal of a negative high-voltage charge pump is connected to a negative high-voltage external monitoring port through a negative high-voltage bidirectional switch circuit, and the negative high-voltage output terminal of a negative high-voltage charge pump is further configured as a negative output end of the voltage supply circuit. Based on a received mode adjustment signal, a mode control circuit controls to enter an external monitoring mode or an external configuration mode.

Abstract: A delay adjustment cell is disposed in a channel of at least one regional clock of a chip clock architecture, and the delay adjustment cell includes a plurality of parallel delay paths with different delay values. The delay adjustment cell gates one of the delay paths based on an obtained configuration signal such that a connected regional clock has a corresponding target delay, and a target delay of each regional clock corresponds to a clock skew mode of the programmable logic chip. A clock skew between different regional clocks is adjusted by controlling the gated delay path in the delay adjustment cell, such that a clock skew of the chip can be adjusted in a relatively large range. Under the same resource configuration, different path choices of the delay adjustment cell lead to different clock skews to meet different clock skew modes in different application scenarios.

Abstract: A logic process-based level conversion circuit of a flash flash field programmable gate array (FPGA) performs three-stage level conversion by using three conversion modules. A first-stage conversion module is configured to convert an input first signal of a VDD-GND voltage domain into a second signal of a VP1-GND voltage domain, an intermediate-stage conversion module is configured to convert the input second signal of the VP1-GND voltage domain into a third signal of a VP1-VN voltage domain, and a drive-stage conversion module is configured to convert the input third signal of the VP1-VN voltage domain into a drive signal of a VP2-VN voltage domain and output a drive word line. The logic process-based level conversion circuit reduces the pressure of conversion at each stage, ensures a capability of driving the next stage, increases the conversion speed, and provides a large driving capability at the last stage.

Abstract: In an anti-fuse programming control circuit based on a master-slave charge pump structure, a master charge pump module obtains an external voltage and is connected to a plurality of slave charge pump modules. Each slave charge pump module is connected to an anti-fuse bank. The distance between the layout position of each slave charge pump module and the layout position of the connected anti-fuse bank does not exceed a predetermined distance. Based on a programming voltage output by each slave charge pump module to the connected anti-fuse bank, the feedback network outputs a feedback signal corresponding to the slave charge pump module to the master charge pump module. Based on the feedback signal corresponding to each slave charge pump module, the master charge pump module adjusts a master drive signal provided to the slave charge pump module to stabilize the programming voltage output by the slave charge pump module.

Abstract: A field-programmable gate array (FPGA) for using a configuration shift chain to implement a multi-bitstream function includes a bitstream control circuit, a multi-bitstream configuration shift chain and a configurable module. The FPGA enables multi-bitstream storage configuration bits to latch configuration bitstreams by adjusting a circuit structure of a multi-bitstream configuration shift chain in a combination of a control logic of a bitstream control circuit for the multi-bitstream configuration shift chain, and outputs one latched configuration bitstream from a configuration output terminal to a configurable module through each multi-bitstream storage configuration bit as required, so that the configurable module implements a logic function corresponding to the configuration bitstream outputted by the multi-bitstream configuration shift chain.

Abstract: A field programmable gate array (FPGA) for improving the reliability of a key configuration bitstream by reusing a buffer memory includes a configuration buffer, a configuration memory and a control circuit. The configuration memory includes N configuration blocks. The FPGA stores a key configuration chain by using the configuration buffer and ensures correct content of the key configuration chain through an error correcting code (ECC) check function of the configuration buffer, so that when the FPGA runs normally, a control circuit reads the key configuration chain in the configuration buffer at an interval of a predetermined time and writes the key configuration chain into a corresponding configuration block to update the key configuration chain, thereby ensuring accuracy of the content of the key configuration chain and improving running reliability of the FPGA.

Abstract: A field-programmable gate array (FPGA) for implementing data transfer between different configuration and application processes includes a programmable logic resource, a configuration memory and a hardware memory. A write port and a read port of the hardware memory are respectively connected to a programmable logic resource by a wiring path, data in the hardware memory remains unchanged at an abnormal running stage of the programmable logic resource, and running data generated by a user design in a configuration and application process can be transferred to a user design in a subsequent configuration and application process by using the hardware memory for use during running. This enlarges functions of the FPGA, and meets application requirements in a plurality of different scenarios.

Abstract: A phase interpolation circuit with a high linearity includes a first parallel circuit constituted by M phase interpolation units, and a second parallel circuit constituted by N phase interpolation units. An input terminal of the first parallel circuit is connected to a first clock input terminal and grounded via a first capacitor. An input terminal of the second parallel circuit is connected to a second clock input terminal and grounded via a second capacitor. An output terminal of the first parallel circuit and an output terminal of the second parallel circuit are connected to a clock output terminal and grounded via a zeroth capacitor. A circuit parameter of each phase interpolation unit corresponds to a target output weight respectively. The target output weight of each phase interpolation unit is determined by iteration to minimize a phase difference between all output clock signals of the phase interpolation circuit.

Abstract: A field programmable gate array (FPGA) with an automatic error detection and correction function for programmable logic modules includes an error checking and correction device. A check code generation circuit in the error checking and correction device performs error correcting code (ECC) encoding according to input data of corresponding programmable logic registers to generate a check code, and refreshes and writes the check code into a check code register according to a clock signal. A check circuit checks outputs of the programmable logic registers and check code registers to generate syndromes for implementing checking. A decoding circuit generates upset signals corresponding to the syndromes according to a trigger enable pulse of a trigger circuit to control a fault register to directly and asynchronously upset content to correct the error. A circuit area is greatly reduced by using the FPGA, thereby improving a degree of integration of the circuit.