Abstract: A micro-device structure comprises a source substrate having a sacrificial layer comprising a sacrificial portion adjacent to an anchor portion, a micro-device disposed completely over the sacrificial portion, the micro-device having a top side opposite the sacrificial portion and a bottom side adjacent to the sacrificial portion and comprising an etch hole that extends through the micro-device from the top side to the bottom side, and a tether that physically connects the micro-device to the anchor portion. A micro-device structure comprises a micro-device disposed on a target substrate. Micro-devices can be any one or more of an antenna, a micro-heater, a power device, a MEMs device, and a micro-fluidic reservoir.

Abstract: An example of a cavity structure comprises a cavity substrate comprising a substrate surface, a cavity extending into the cavity substrate, the cavity having a cavity bottom and cavity walls, and a cap disposed on a side of the cavity opposite the cavity bottom. The cavity substrate, the cap, and the one or more cavity walls form a cavity enclosing a volume. A component can be disposed in the cavity and can extend above the substrate surface. The component can be a piezoelectric or a MEMS device. The cap can have a tophat configuration. The cavity structure can be micro-transfer printed from a source wafer to a destination substrate.

Abstract: A stamp for micro-transfer printing includes a support having a support surface and posts disposed on the support surface. Each post has a proximal end in contact with the support and a distal end extending away from the support. The post has a post surface on the distal end. The post surface is a structured surface comprising spatially separated ridges that extend in a ridge direction entirely across the post surface and can be operable to form multiple delamination fronts when a first side of a micro-device is in contact with the post surface, a second side of the micro-device is in contact with a target surface of a target substrate, and the support is moved in a horizontal direction parallel to the target substrate surface. The post surface or ridges can be rectangular or non-rectangular with opposing edges having different lengths.

Abstract: An example of a cavity structure comprises a cavity substrate comprising a substrate surface, a cavity extending into the cavity substrate, the cavity having a cavity bottom and cavity walls, and a cap disposed on a side of the cavity opposite the cavity bottom. The cavity substrate, the cap, and the one or more cavity walls form a cavity enclosing a volume. A component can be disposed in the cavity and can extend above the substrate surface. The component can be a piezoelectric or a MEMS device. The cap can have a tophat configuration. The cavity structure can be micro-transfer printed from a source wafer to a destination substrate.

Abstract: A suspended device structure comprises a substrate, a cavity disposed in a surface of the substrate, and a device suspended entirely over a bottom of the cavity. The device is a piezoelectric device and is suspended at least by a tether that physically connects the device to the substrate. The tether has a non-linear centerline. A wafer can comprise a plurality of suspended device structures.

Abstract: A monolithic multi-FET transistor comprises an epitaxial layer disposed on a dielectric layer. The epitaxial layer comprises a crystalline semiconductor material and a multi-FET area. An isolation structure surrounds the multi-FET area and divides the multi-FET area into separate FET portions. A gate disposed on a gate dielectric extends over each FET portion. A source and a drain are each disposed on opposite sides of the gate on the epitaxial layer within each FET portion. Each gate, source, and drain comprise a separate electrical conductor and the gate, source, drain, and epitaxial layer within each FET portion form a field-effect transistor. Gate, source, and drain contacts electrically connect the gates, sources, and drains of the separate FET portions, respectively. At least the sources or drains of two neighboring FET portions are disposed in common over at least a portion of the isolation structure dividing the two neighboring FET portions.

Abstract: An example of a cavity structure comprises a cavity substrate comprising a substrate surface, a cavity extending into the cavity substrate, the cavity having a cavity bottom and cavity walls, and a cap disposed on a side of the cavity opposite the cavity bottom. The cavity substrate, the cap, and the one or more cavity walls form a cavity enclosing a volume. A component can be disposed in the cavity and can extend above the substrate surface. The component can be a piezoelectric or a MEMS device. The cap can have a tophat configuration. The cavity structure can be micro-transfer printed from a source wafer to a destination substrate.

Abstract: A monolithic multi-FET transistor comprises an epitaxial layer disposed on a dielectric layer. The epitaxial layer comprises a crystalline semiconductor material and a multi-FET area. An isolation structure surrounds the multi-FET area and divides the multi-FET area into separate FET portions. A gate disposed on a gate dielectric extends over each FET portion. A source and a drain are each disposed on opposite sides of the gate on the epitaxial layer within each FET portion. Each gate, source, and drain comprise a separate electrical conductor and the gate, source, drain, and epitaxial layer within each FET portion form a field-effect transistor. Gate, source, and drain contacts electrically connect the gates, sources, and drains of the separate FET portions, respectively. At least the sources or drains of two neighboring FET portions are disposed in common over at least a portion of the isolation structure dividing the two neighboring FET portions.

Abstract: A micro-component comprises a component substrate having a first side and an opposing second side. Fenders project from the first and second sides of the component substrate and include first-side fenders extending from the first side and a second-side fender extending from the second side of the component substrate. At least two of the first-side fenders have a non-conductive surface and are disposed closer to a corner of the component substrate than to a center of the component substrate.

Abstract: A method of making a secure integrated-circuit system comprises providing a first integrated circuit in a first die having a first die size and providing a second integrated circuit in a second die. The second die size is smaller than the first die size. The second die is transfer printed onto the first die and connected to the first integrated circuit, forming a compound die. The compound die is packaged. The second integrated circuit is operable to monitor the operation of the first integrated circuit and provides a monitor signal responsive to the operation of the first integrated circuit. The first integrated circuit can be constructed in an insecure facility and the second integrated circuit can be constructed in a secure facility.

Abstract: A suspended device structure comprises a substrate, a cavity disposed in a surface of the substrate, and a device suspended entirely over a bottom of the cavity. The device is a piezoelectric device and is suspended at least by a tether that physically connects the device to the substrate. The tether has a non-linear centerline. A wafer can comprise a plurality of suspended device structures.

Abstract: A suspended device structure comprises a substrate, a cavity disposed in a surface of the substrate, and a device suspended entirely over a bottom of the cavity. The device is a piezoelectric device and is suspended at least by a tether that physically connects the device to the substrate. The tether has a non-linear centerline. A wafer can comprise a plurality of suspended device structures. A device structure can comprise a device over a sacrificial portion or cavity and a tether with a tether opening extending to the sacrificial portion or cavity. The tether or tether opening can have a T shape. The tether can have a tether length at least one third as large as a device length and the device can have a device length at least twice as large as a device width.

Abstract: A stacked electronic component comprises a stack of three or more print layers. Each print layer has an area less than any print layers beneath the print layer in the stack. Each print layer comprises a dielectric layer and a functional layer disposed on the dielectric layer. The functional layer comprises an exposed conductive portion that is not covered with a dielectric layer of any of the print layers and each exposed conductive portion is nonoverlapping with any other exposed conductive portion. A patterned electrode layer is coated on at least a portion of the stack and defines one or more electrodes. Each electrode of the one or more electrodes in electrical contact with an exclusive subset of the exposed conductive portions. The functional layers can be passive conductors forming capacitors, resistors, inductors, or antennas, or active layers forming electronic circuits.

Abstract: An example of a printable electronic component includes a component substrate having a connection post side and an opposing contact pad side. The component can include one or more non-planar, electrically conductive connection posts protruding from the connection post side of the component substrate. Each of the one or more connection posts can have a peak area smaller than a base area. The component can include one or more non-planar, electrically conductive exposed component contact pads disposed on (e.g., directly on, indirectly on, or in) the contact pad side of the component substrate. Multiple components can be stacked such that connection post(s) of one are in contact with non-planar contact(s) of one or more others.

Abstract: A method of making a secure integrated-circuit system comprises providing a first integrated circuit in a first die having a first die size and providing a second integrated circuit in a second die. The second die size is smaller than the first die size. The second die is transfer printed onto the first die and connected to the first integrated circuit, forming a compound die. The compound die is packaged. The second integrated circuit is operable to monitor the operation of the first integrated circuit and provides a monitor signal responsive to the operation of the first integrated circuit. The first integrated circuit can be constructed in an insecure facility and the second integrated circuit can be constructed in a secure facility.

Abstract: Provided are optical devices and systems fabricated, at least in part, via printing-based assembly and integration of device components. In specific embodiments the present invention provides light emitting systems, light collecting systems, light sensing systems and photovoltaic systems comprising printable semiconductor elements, including large area, high performance macroelectronic devices. Optical systems of the present invention comprise semiconductor elements assembled, organized and/or integrated with other device components via printing techniques that exhibit performance characteristics and functionality comparable to single crystalline semiconductor based devices fabricated using conventional high temperature processing methods. Optical systems of the present invention have device geometries and configurations, such as form factors, component densities, and component positions, accessed by printing that provide a range of useful device functionalities.

Abstract: A overhanging device cavity structure comprises a substrate and a cavity disposed in or on the substrate. The cavity comprises a first cavity side wall and a second cavity side wall opposing the first cavity side wall on an opposite side of the cavity from the first cavity side wall. A support extends from the first cavity side wall to the second cavity side wall and at least partially divides the cavity. A device is disposed on, for example in direct contact with, the support and extends from the support into the cavity.

Abstract: A method of making a secure integrated-circuit system comprises providing a first integrated circuit in a first die having a first die size and providing a second integrated circuit in a second die. The second die size is smaller than the first die size. The second die is transfer printed onto the first die and connected to the first integrated circuit, forming a compound die. The compound die is packaged. The second integrated circuit is operable to monitor the operation of the first integrated circuit and provides a monitor signal responsive to the operation of the first integrated circuit. The first integrated circuit can be constructed in an insecure facility and the second integrated circuit can be constructed in a secure facility.

Abstract: A compound sensor device includes a semiconductor substrate having an active electronic circuit formed in or on the semiconductor substrate. A sensor including a sensor substrate including a sensor circuit having an environmental sensor or actuator formed in or on the sensor substrate is micro-transfer printed onto the semiconductor substrate. One or more electrical conductors electrically connect the active electronic circuit to the sensor circuit. The semiconductor substrate includes a first material and the sensor substrate includes a second material different from the first material.

Abstract: A monolithic multi-FET transistor comprises an epitaxial layer disposed on a dielectric layer. The epitaxial layer comprises a crystalline semiconductor material and a multi-FET area. An isolation structure surrounds the multi-FET area and divides the multi-FET area into separate FET portions. A gate disposed on a gate dielectric extends over each FET portion. A source and a drain are each disposed on opposite sides of the gate on the epitaxial layer within each FET portion. Each gate, source, and drain comprise a separate electrical conductor and the gate, source, drain, and epitaxial layer within each FET portion form a field-effect transistor. Gate, source, and drain contacts electrically connect the gates, sources, and drains of the separate FET portions, respectively. At least the sources or drains of two neighboring FET portions are disposed in common over at least a portion of the isolation structure dividing the two neighboring FET portions.