Abstract: Disclosed are solid-state potentiometers having high resolution and high accuracy. An exemplary potentiometer has a first main terminal, a second main terminal, a wiper terminal, and a resistor stack having a plurality M of resistors coupled in series to one another at a plurality of M−1 internal nodes. Each of the resistors in the stack has substantially the same value of RS ohms. The potentiometer further has a first variable resistance network coupled between one end of the resistor stack and the potentiometer's first main terminal, and a second variable resistance network coupled between the other end of the resistor stack and the potentiometer's second main terminal. The first variable resistance network has a variable resistance value R1 which varies between zero ohms and RP ohms. The second variable resistance network has a variable resistance value R2 which is maintained substantially at value of (RP−R1).

Abstract: A battery management system is provided having a battery management unit (BMU) and an integrated switch and sensor unit (SSU) for accurately measuring the charge state of a rechargeable battery and providing charge protection for the rechargeable battery. The system uses a charger unit to charge the rechargeable battery and a combination sensor switch circuit having a first and second mirror current proportional to the current used to charge and discharge the rechargeable battery. The switch function in sensor switch circuit disconnects the battery from receiving additional charge when a disconnect signal is provided. A battery management unit is used to detect conditions such as over voltage, over current, and over temperature associated with the rechargeable battery and transmit the disconnect signal to the sensor and switch unit when at least one condition is detected.

Abstract: A compact, electrically-erasable and electrically-programmable nonvolatile memory device employing novel programming and erasing techniques and using two layers of conductive or semiconductive material is disclosed. The memory cell of the present invention comprises a first layer serving as a floating gate and a second layer serving the functions of erasing the floating gate and of selecting the device for reading and programming the floating gate. The second layer may be made common to more than one memory device of the present invention. Programming of the device occurs by tunneling electrons into the first layer (floating gate) by hot-electron injection from a channel region controlled by the second layer. In one preferred embodiment of the present invention, erasure of the memory cell occurs by causing the tunneling of electrons from the first layer (floating gate) to the second layer by an enhanced tunneling mechanism.

Abstract: An apparatus and method for depositing a tunneling oxide layer between two conducting layers utilizing a low pressure, low temperature chemical vapor depostion (LPCVD) process is disclosed wherein tetraethylorthosilicate (TEOS) is preferably used. As applied to an electrically erasable programmable read only memory (EEPROM) device having polysilicon layers, the apparatus is constructed by forming a first layer of polysilicon, patterned as desired. A layer of silicon dioxide is then deposited by decomposition of TEOS to form the tunneling oxide to a predetermined thickness. If enhanced emission structures are desired, a layer of relatively thin tunneling oxide may be grown on the first layer of polysilicon. The oxide layer is then annealed and densified, preferably using steam and an inert gas at a specific temperature. A second layer of polysilicon is then formed on top of the tunneling oxide.

Abstract: A compact, electrically-erasable and electrically-programmable nonvolatile memory device employing novel programming and erasing techniques and using two layers of conductive or semiconductive material is disclosed. The memory cell of the present invention comprises a first layer serving as a floating gate and a second layer serving the functions of erasing the floating gate and of selecting the device for reading and programming the floating gate. The second layer may be made common to more than one memory device of the present invention. Programming of the device occurs by tunneling electrons into the first layer (floating gate) by hot-electron injection from a channel region controlled by the second layer. In one preferred embodiment of the present invention, erasure of the memory cell occurs by causing the tunneling of electrons from the first layer (floating gate) to the second layer by an enhanced tunneling mechanism.

Abstract: A wireless communication system for communicating between a host system and a stand-alone device through an electromagnetic coupling medium is disclosed. The communication system has the capabilities of bi-directional data communications between the host and the stand-alone device and of powering the stand-alone device with energy pulses coupled through the electromagnetic coupling medium from the host. The electromagnetic medium is capable of supporting the bi-directional flow of energy pulses and energy transitions thereof between the host and stand-alone device. In one embodiment, bi-directional communication is provided by transmitting and detecting predetermined numbers of consecutive energy transitions coupled through the medium. Resting durations immediately precede and follow each predetermined number of consecutive energy transitions.

Abstract: A compact, electrically-erasable and electrically-programmable nonvolatile memory device employing novel programming and erasing techniques and using two layers of conductive or semiconductive material is disclosed. The memory cell of the present invention comprises a first layer serving as a floating gate and a second layer serving the functions of erasing the floating gate and of selecting the device for reading and programming the floating gate. The second layer may be made common to more than one memory device of the present invention. Programming of the device occurs by tunneling electrons into the first layer (floating gate) by hot-electron injection from a channel region controlled by the second layer. In one preferred embodiment of the present invention, erasure of the memory cell occurs by causing the tunneling of electrons from the first layer (floating gate) to the second layer by an enhanced tunneling mechanism.

Abstract: A wireless communication system for communicating between a host system and a stand-alone device through an electromagnetic coupling medium is disclosed. The communication system has the capabilities of bi-directional data communications between the host and the stand-alone device and of powering the stand-alone device with energy pulses coupled through the electromagnetic coupling medium from the host. The electromagnetic medium is capable of supporting the bi-directional flow of energy pulses and energy transitions thereof between the host and stand-alone device. In one embodiment, bi-directional communication is provided by transmitting and detecting predetermined numbers of consecutive energy transitions coupled through the medium. Resting durations immediately precede and follow each predetermined number of consecutive energy transitions.

Abstract: A wireless communication system for communicating between a host system and a stand-alone device through an electromagnetic coupling medium is disclosed. The communication system has the capabilities of bi-directional data communications between the host and the stand-alone device and of powering the stand-alone device with energy pulses coupled through the electromagnetic coupling medium from the host. The electromagnetic medium is capable of supporting the bi-directional flow of energy pulses and energy transitions thereof between the host and stand-alone device. In one embodiment, bi-directional communication is provided by transmitting and detecting predetermined numbers of consecutive energy transitions coupled through the medium. Resting durations immediately precede and follow each predetermined number of consecutive energy transitions.

Abstract: A semiconductor integrated circuit device is disclosed having first and second conducting layers, with the first layer having a shape which enhances field emission tunneling off of the surface thereof. A dual thickness dielectric layer separates the conducting layers. When a potential difference is applied between the conducting layers, field emission tunneling occurs primarily through the thinner portion of the dielectric layer.

Abstract: A three-terminal serial-communication peripheral device for low-cost applications is described. The peripheral device comprises a first terminal for receiving a modulated power signal including a source of power and a clocking signal, a second terminal for receiving a reference potential such as a ground reference, and a third terminal for communicating data to and from the peripheral device. The peripheral device further comprises a digital subsystem which exchanges data with an application system. The exchanged data may be stored and retrieved by the digital subsystem, as when the subsystem is a memory unit, or the data may be in the form of measurement data which the peripheral device is supplying to the application system, the measured data being supplied by a sensor of the subsystem. With its three terminals, the peripheral device can communicate data to and from the application system.

Abstract: An apparatus and method for depositing a tunneling oxide layer between two conducting layers utilizing a low pressure, low temperature chemical vapor deposition (LPCVD) process is disclosed wherein tetraethylorthosilicate (TEOS) is preferably used. As applied to an electrically erasable programmable read only memory (EEPROM) device having polysilicon layers, the apparatus is constructed by forming a first layer of polysilicon, patterned as desired. A layer of silicon dioxide is then deposited by decomposition of TEOS to form the tunneling oxide to a predetermined thickness. If enhanced emission structures are desired, a layer of relatively thin tunneling oxide may be grown on the first layer of polysilicon. The oxide layer is then annealed and densified, preferably using steam and an inert gas at a specific temperature. A second layer of polysilicon is then formed on top of the tunneling oxide.

Abstract: A field-programmable redundancy apparatus for integrated circuit semiconductor memory arrays is disclosed. The present invention allows the user to replace a defective memory cell with a redundant memory cell while the integrated circuit memory array is in the field. The user communicates with the redundancy apparatus over standard signal paths of the integrated circuit semiconductor memory array and with standard voltage levels. The redundancy apparatus detects a predetermined code sequence on one or more of the address and data lines of the memory array to enter a special redundancy-reconfiguration mode. In the reconfiguration mode, the redundancy apparatus provides information on the availability and functionality of the redundant memory cells and enables the user to replace a defective memory cell with a selected redundant memory cell.

Abstract: A field-programmable redundancy apparatus for integrated circuit semiconductor memory arrays is disclosed. The present invention allows the user to replace a defective memory cell with a redundant memory cell while the integrated circuit memory array is in the field. The user communicates with the redundancy apparatus over the standard signal paths with standard voltage levels of the integrated circuit semiconductor memory array. The redundancy apparatus detects a predetermined code sequence on one or more of the address and data lines of the memory array to enter a special redundancy-reconfiguration mode. In the reconfiguration mode, the redundancy apparatus provides information on the availability and functionality of the redundant memory cells and enables the user to replace a defective memory cell with a selected redundant memory cell.

Abstract: A semiconductor integrated circuit device is disclosed having first and second conducting layers, with the first layer having a shape which enhances field emission tunneling off of the surface thereof. A dual thickness dielectric layer separates the conducting layers. When a potential difference is applied between the conducting layers, field emission tunneling occurs primarily through the thinner portion of the dielectric layer.

Abstract: A variable impedance circuit for use in an external circuit is disclosed. The impedance value is selected by an external circuit. The variable impedance is generated between two terminals which are accessible for connection to external circuitry. The impedance provided between these terminals is determined by a control circuit responsive to electrical signals coupled to the control circuit. An internal register in the control circuit stores a value which specifies the impedance between the two terminals. The stored value is copied into a programmable nonvolatile read-only memory in response to a first predetermined electrical signal. Similarly, the value stored in the read-only memory is selectively copied into the internal control circuit register in response to a second predetermined electrical signal.

Abstract: A nonvolatile integrated circuit memory cell (10) is provided which is smaller in size than conventional memory cells and uses only two layers of polysilicon with floating gate portion (50) of the memory cell formed partly from a first polysilicon layer (20) and partly from second polysilicon layer (26), contact between the two portions being made using residual polysilicon bridge or overlapping portion (34) between the two layers. The invention enables programming and erase tunneling oxides to be formed in a single step while maximizing the capacitive coupling between the floating gate (50) and the substrate (12) by forming a silicon dioxide layer (102) between the floating gate and substrate separately from formation of the programming (30) and erase (28) tunneling elements.

Abstract: A dual mode high voltage coupler is described for enabling a low current capacity high voltage generator to supply high voltage to an output load, such as a row or word line in an EEPROM memory device during a nonvolatile write or erase operation. The coupler limits the amount of current to defective cells or rows in the memory without limiting current to the cells and rows that are operating normally. In a first mode, a single stage charge pump, including a storage capacitor driven by a periodic voltage signal, develops a metered current through a diode to the output load whose amplitude is equal to the product of the capacitance of the storage capacitor, the change in voltage across the capacitor in each cycle of said periodic signal and the frequency of said signal. In a second mode, said high voltage is coupled directly to said output load without limiting the current whenever the voltage across said load exceeds a predetermined value.

Abstract: An apparatus for generating and regulating a substrate bias voltage for use in semiconductor devices. The invention comprises a sensor which is responsive to the substrate bias voltage, and generates a continuously variable regulating voltage and a continuously variable oscillator bias voltage. A variable impedance device whose resistance is adjustable over a range of values as a function of said regulating voltage is coupled to a charge pump to control the amount of charge pumped by said charge pump per unit time from the substrate of the semiconductor device. An oscillator whose frequency is continuously controlled by the oscillator bias voltage from the sensor is coupled to said charge pump so as to further control the amount of charge pumped by said charge pump per unit time.

Abstract: A nonvolatile, semiconductor randon access memory cell comprising a static RAM element and a nonvolatile memory element having differential charge storage capabilities is presented. The static RAM and nonvolatile memory elements are interconnected to allow information to be exchanged between two elements, thus allowing the faster static RAM element to serve as the primary memory to the system and allowing the nonvolatile memory element to serve as permanent storage during power-down conditions. In one embodiment, the nonvolatile memory element comprises two electrically erasable PROM devices (EEPROMs). The two EEPROM devices store differential charges corresponding to the complementary outputs of the static RAM element. The nature of the differential charge storage allows lower programming voltages to be used on the EEPROM devices, resulting in increased storage intergrity and increased endurance of the EEPROM devices.