Abstract: A substrate voltage bias generator is disclosed including a charge pump whose output is clamped during charge pump capacitor charging cycles to zero volts thereby eliminating a voltage drop associated with prior art clamping diodes. The charge pump further includes a stand-by and booted mode, the stand-by mode providing a first level of output current at a specified generated substrate bias voltage and in the booted mode generating increased output current and voltage. The increased voltage is generated across the charge pump capacitor by a second capacitor that is only operative in the booted mode and whose charge is shared with the charge pump capacitor thereby developing a higher voltage across the charge pump capacitor. The output voltage generated by the substrate bias generator is detected and if it is too low a voltage, the booted mode is turned off. An external signal determines whether the stand-by mode or booted mode are selected.

Abstract: The voltage clamp circuit can clamp positive and/or negative voltages. The voltage clamp circuit includes voltage sensing and clamping circuit consisting of a chain of series connected diodes connected between an output and a reference terminal of the voltage clamp circuit. A current mirror circuit is connected to the chain of series connected diodes. A current generating circuit is connected to the current mirror circuit and sensing and clamping circuit. The voltage clamp circuit consumes only enough current to develop a threshold voltage across each of the chain of series connected diodes.

Abstract: A current metering circuit is configured as a single stage charge pump for limiting the current level applied to the tunneling regions of an integrated circuit, nonvolatile, floating gate memory cell. The current metering circuit includes a storage capacitor which has one plate pumped by a periodic signal. The other plate of the capacitor is charged from a voltage that is boot-strapped from the voltage that presently exists across the active tunneling region. More particularly, a high voltage is applied to the drain of a transistor whose gate is connected to the tunneling region. The source of this transistor is coupled to a plate of the storage capacitor. This source develops a voltage equal to the present voltage across the load less the turnon threshold of the transistor. When the periodic signal goes low, the storage capacitor is charged from the voltage appearing at the source of this transistor.

Abstract: A compact, floating gate, nonvolatile, electrically alterable memory device is fabricated with three layers of polysilicon. In a nonvolatile memory array, each cell is electrically isolated from other cells to eliminate data disturb conditions in nonaddressed cells of the memory array. The memory cell and array is described as including four electrode layers, one of which being formed as a substrate coupling electrode. The cell is also described as being relatively process intolerant. The first electrode layer above the substrate is used to mask the diffusion or implantation of the substrate coupling electrode and other regions in the substrate to form self-aligned active devices.

Abstract: A variable impedance circuit for use in an external circuit. The impedance value may be altered by an external circuit. The invention consists of a plurality of two terminal impedance elements connected in series. A node is provided between each pair of impedance elements in the series chain. At least one of the first element and last elements in the series chain are connected to terminals which are accessible for connection to the external circuit. Each of the nodes may be connected to a terminal which is also accessible for connection to the external circuit. An electrically reprogrammable read-only memory stores the identity of the node connected such that the identity of this node is retained when power is removed from the invention. When power is returned to the invention, the node which was previously connected to the terminal is automatically reconnected.

Abstract: Low power consumption methods and apparatus for distributing and controlling on-chip generated high voltage, for programming nonvolatile memory arrays and the like.

Abstract: A compact, floating gate, nonvolatile, electrically alterable memory device is fabricated with three layers of polysilicon. In a nonvolatile memory array, each cell is electrically isolated from other cells to eliminate data disturb conditions in nonaddressed cells of the memory array. The memory cell and array is described in a first embodiment as including four electrode layers, one of which being formed as a substrate coupling electrode. A second embodiment includes a three electrode layer device wherein the need for the substrate coupling electrode is eliminated.

Abstract: Integrated high voltage clamping methods and devices which provide a controllable "soft" clamping action. The systems are particularly useful for "on-chip" EEPROM high voltage power supplies.

Abstract: Low power consumption methods and apparatus for distributing and controlling on-chip generated high voltage, for programming nonvolatile memory arrays and the like.

Abstract: Integrated circuit high voltage ramp rate control methods and devices which provide a controllable ramp rate action. The systems are particularly useful for "on-chip" EEPROM high voltage power supplies.

Abstract: A compact, floating gate, nonvolatile, electrically-alterable memory device fabricated with three layers of polysilicon and a substrate coupling electrode is described. A particular form of the device utilizes asperities to promote tunnel current flow through relatively thick oxides by means of relatively low average applied voltages. The use of four electrode layers leads to an extremely dense cell and memory array configuration. The substrate electrode is used to establish bias voltages in the cell.

Abstract: An integrated testing apparatus provides bidirectional coupling of a high voltage either from an internal source on an integrated circuit to a first external pin on the integrated circuit package, or to the output point of said internal source of high voltage from a voltage source external to the integrated circuit package that is coupled to said first external pin, said coupling occurring in response to an enabling signal externally impressed on a second external pin on said integrated circuit package. The testing apparatus is substantially transparent to normal integrated circuit operation when said enabling signal is removed from said second external pin.

Abstract: An integrated circuit system for generating a regulated high voltage tunneling pulse whose voltage level varies as a function of the voltage level needed to initiate tunneling of electrons across one or more dielectric gaps between respective first and second regions. The voltage level of initial electron tunneling is compared with a predetermined voltage margin so as to cause said generated tunneling voltage pulse to have a voltage level equal to the sum of said detected tunneling voltage and said voltage margin. The tunneling voltage pulse is then maintained substantially at this level for a predetermined duration before the tunneling pulse is discharged.

Abstract: Nonvolatile, integrated metal-oxide semiconductor random access memory systems utilizing integrated floating gate circuit elements, and integrated means for the generation and control of high voltages in the provision of self-contained, nonvolatile electrically-alterable static RAM circuit systems.

Abstract: Integrated circuit system for generating a rise-time regulated and level controlled high voltage pulse utilizing a plurality of diode-connected stages driven by capacitively coupled low voltage clocks. The maximum output voltage may be controlled by a gated diode reference device, which provides a reference voltage independent of power supply voltage. A feedback circuit may be provided which controls the high voltage rise time by modulating the effective low voltage clock amplitude driving the high voltage generator. A MOS logic level interface circuit may also be provided for sensing achievement of the predetermined high voltage level.

Abstract: A compact, floating gate, nonvolatile, electrically-alterable memory device fabricated with four layers of polysilicon is described. A particular form of the device utilizes asperities to promote tunnel current flow through relatively thick oxides by means of relatively low average applied voltages. The use of four electrode layers leads to an extremely dense cell and memory array configuration.

Abstract: Nonvolatile, semiconductor random access memory cells comprising a static, RAM cell and a nonvolatile memory element which may be interconnected with the static random-access memory cell by capacitative coupling, such that the RAM cell contents may be directly copied to the nonvolatile element, and such that the nonvolatile memory cell contents will be copied to the RAM cell upon applying power to the RAM cell. The nonvolatile memory element may be a substrate-coupled floating gate cell incorporating self-regulated and asperity enhanced tunnel currents.

Abstract: Nonvolatile semiconductor electrically-alterable, floating-gate memory methods and devices which utilize substrate coupling for self-regulated, tunnel-current-shaping to provide improved device characteristics. The substrate coupling also facilitates the cell interconnection to other circuit elements.

Abstract: Nonvolatile, integrated metal-oxide semiconductor random access memory systems utilizing integrated floating gate circuit elements, and integrated means for the generation and control of high voltages in the provision of self-contained, nonvolatile electrically-alterable static RAM circuit systems.