Abstract: In a method for manufacturing a memory device, a plurality of first insulating layers and a bottom select gate (BSG) layer are formed over a substrate, where the first insulating layers are disposed between the substrate and the BSG layer. One or more first dielectric trenches are formed to pass through the BSG layer and the first insulating layers, and extend in a length direction of the substrate. A plurality of word line layers and a plurality of second insulating layers are formed over the BSG layer, where the second insulating layers are disposed between the BSG layer and the word line layers. One or more common source regions are formed over the substrate to extend in the length direction of the substrate, and further extend through the BSG layer, the first insulating layers, the word line layers, and the second insulating layers.

Abstract: A memory device includes a staircase region and an array region, along a first lateral direction; a wall structure in the staircase region; and a first separation structure in the array region and arranged along the first lateral direction with the wall structure. The wall structure includes dielectric pairs of a first dielectric layer and a second dielectric layer stacked in the staircase region. The first separation structure is vertically through a stack structure in the array region. The stack structure includes pairs of the first dielectric layer and an electrode layer.

Abstract: Embodiments of the present disclosure provide a method for forming a hole structure in a semiconductor device. The method includes forming a first etch mask over a stack structure, and removing a portion of the stack structure exposed by the first etch mask. The first etch mask may have a first mask opening with a first lateral dimension. The method may also include forming a second etch mask from the first etch mask. The second etch mask may have a second mask opening with a second lateral dimension that is greater than the first lateral dimension. The method may further include removing another portion of the stack structure exposed by the second etch mask to form the hole structure having a first hole portion and a second hole portion connected to and over the first hole portion.

Abstract: Embodiments of three-dimensional memory devices are disclosed. A disclosed memory structure comprises a memory cell comprising: a cylindrical body having a cylindrical shape, an insulating layer surrounding the cylindrical body, a word line contact coupled to a word line and surrounding a first portion of the insulating layer, and multiple plate line contact segments coupled to multiple plate lines respectively and surrounding a second portion of the insulating layer. The memory structure further comprises a bit line contact coupled to a bit line and coupled to a first end of the cylindrical body, a source line contact coupled to a source line, and a source cap coupled between the source line contact and a second end of the cylindrical body to increase a distance between the source line contact and the plate line contact segments.

Abstract: Embodiments of three-dimensional memory devices and fabricating methods thereof are disclosed. One disclosed method for forming a memory structure comprises: forming a bottom conductive layer on a substrate; forming a dielectric stack on the bottom conductive layer, the dielectric stack comprising a plurality of alternatively arranged first dielectric layers and second dielectric layers; forming an opening penetrating the dielectric stack and exposing the bottom conductive layer; forming a cap layer on a bottom of the opening; forming a cylindrical body and a top contact on the cap layer and in the opening; and replacing the plurality of second dielectric layers with conductive layers.

Abstract: Embodiments of three-dimensional memory devices and fabricating methods thereof are disclosed. One disclosed method for forming a memory structure comprises: forming a bottom conductive layer on a substrate; forming a memory stack on the bottom conductive layer, the memory stack comprising a plurality of alternatively arranged dielectric layers and conductive layers; forming an opening penetrating the memory stack and exposing the bottom conductive layer; forming a cap layer on a bottom of the opening; forming a cylindrical body and a top contact on the cap layer and in the opening; and forming a plurality of interconnection structures to electrically connect the bottom conductive layer, the plurality of conductive layers of the memory stack, and the top contact.

Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, the memory device includes a stack structure having interleaved a plurality of conductor layers and a plurality of dielectric layers over a substrate along a vertical direction. The memory device also includes a channel structure extending in the stack structure along the vertical direction. A thickness of at least one of the plurality of conductor layers is nominally proportional to a width of the channel structure at the same depth.

Abstract: In a semiconductor device, a stack of alternating gate layers and insulating layers is formed over a substrate. Channel structures are formed in an array region of the stack. A first staircase is formed at a first section of the stack. A second staircase is formed at a second section of the stack. The first staircase is positioned over the second staircase. The first staircase includes first group stair steps descending in a second direction parallel to the substrate and first division stair steps descending in a third direction and a fourth direction that are parallel to the substrate and perpendicular to the second direction. The third direction and the fourth direction are opposite to each other. The second staircase includes second group stair steps descending in the second direction and second division stair steps descending in the third direction and the fourth direction.

Abstract: Disclosed herein are memory device, method for data preprocessing of program operations. In an aspect, a memory device comprises N data latches configured to store data and a controller coupled to the N data latches. The controller is configured to receive the data that includes data units and store the data units in the N data latches, wherein each of the data units includes N bits. The processor is further configured to convert the data units based on a first table and a second table and program cells of the memory device based on the converted data units. The first and the second tables include N rows and 2N columns of bits and bits from column 2N-1+2 to column 2N in Nth row of the second table are identical.

Abstract: A three-dimensional (3D) memory device includes a first memory cell, a second memory cell, a control gate between the first and second memory cells, a top contact coupled to the first memory cell, and a bottom contact coupled to the second memory cell. The first memory cell can include a first pillar, a first insulating layer surrounding the first pillar, a first gate contact coupled to a first word line, and a second gate contact coupled to a first plate line. The second memory cell can include a second pillar, a second insulating layer surrounding the second pillar, a third gate contact coupled to a second word line, and a fourth gate contact coupled to a second plate line. The 3D memory device can utilize dynamic flash memory (DFM), increase storage density, provide multi-cell storage, provide a three-state logic, decrease leakage current, increase retention time, and decrease refresh rates.

Abstract: The present disclosure describes flash controller for reading data from a flash memory device. A flash memory controller can include a controller storage and one or more processors. The one or more processors are configured to: receive a request for data stored in flash memory dies. The request includes a logical address of the data and at least one flash memory die of the flash memory dies includes one or more on-die static random access memory (SRAM) storage devices. The one or more processors are further configured to: identify an on-die SRAM storage device containing logical-to-physical (L2P) information; search the L2P information to obtain a physical address of the data that corresponds to the logical address; and retrieve the data from a flash memory array of corresponding flash memory die using the physical address.

Abstract: A three-dimensional (3D) memory device includes a memory cell, a top contact coupled to the memory cell, and a bottom contact coupled to the memory cell. The memory cell can include a pillar, an insulating layer surrounding the pillar, a first gate contact surrounding a first portion of the insulating layer, and a second gate contact surrounding a second portion of the insulating layer. The pillar can be configured to store an electrical charge. The pillar can be a monocrystalline material. The 3D memory device can utilize dynamic flash memory (DFM), decrease defects, increase manufacturing efficiency, decrease leakage current, decrease junction current, decrease power consumption, increase storage density, increase charge retention times, and decrease refresh rates.

Abstract: A three-dimensional (3D) memory device includes a memory cell, a top contact coupled to the memory cell, and a bottom contact coupled to the memory cell. The memory cell can include a pillar, an insulating layer surrounding the pillar, a first gate contact coupled to a word line, a second gate contact coupled to a plate line, and an annular dielectric layer within a portion of the pillar. The annular dielectric layer can increase a retention time of electrical charge in the pillar. The 3D memory device can utilize dynamic flash memory (DFM), increase retention times, decrease refresh rates, increase a floating body effect, decrease manufacturing defects, decrease leakage current, decrease junction current, decrease power consumption, increase an upper limit of charge density in the pillar, dynamically adjust a length of the plate line, and decrease parasitic resistance.

Abstract: A three-dimensional (3D) memory device includes a memory cell, a top contact coupled to the memory cell, and a bottom contact coupled to the memory cell. The memory cell can include a pillar, an insulating layer surrounding the pillar, a first gate contact coupled to a word line, a second gate contact coupled to a plate line, and a third gate contact configured to control electrical charge conduction between the first gate contact and the second gate contact. The 3D memory device can utilize dynamic flash memory (DFM), increase storage efficiency, provide tri-gate control, provide different programming options, increase read, program, and erase operation rates, decrease leakage current, increase retention time, and decrease refresh rates.

Abstract: Aspects of the disclosure provide methods for manufacturing semiconductor devices. One of the methods forms a string of transistors in a semiconductor device over a substrate of the semiconductor device. The method includes forming a first substring of transistors having a first channel structure that includes a first channel layer and a first gate dielectric structure that extend along a vertical direction over the substrate. The method includes forming a channel connector over the first substring and forming the second substring above the channel connector. The second substring has a second channel structure. The second channel structure includes the second channel layer and a second gate dielectric structure that extend along the vertical direction. The second gate dielectric structure is formed above the channel connector. The channel connector electrically couples the first channel layer and the second channel layer.

Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a NAND memory device includes a substrate, one or more peripheral devices on the substrate, a plurality of NAND strings above the peripheral devices, a single crystalline silicon layer above and in contact with the NAND strings, and interconnect layers formed between the peripheral devices and the NAND strings. In some embodiments, the NAND memory device includes a bonding interface at which an array interconnect layer contacts a peripheral interconnect layer.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A channel opening extending vertically is formed above a substrate. A semiconductor plug is formed in a lower portion of the channel opening. A memory film and a channel sacrificial layer are subsequently formed above the semiconductor plug and along a sidewall of the channel opening. A semiconductor plug protrusion protruding above the semiconductor plug and through a bottom of the memory film and the channel sacrificial layer is formed. A cap layer is formed in the channel opening and over the channel sacrificial layer. The cap layer covers the semiconductor plug protrusion. A semiconductor channel is formed between the memory film and the cap layer by replacing the channel sacrificial layer with a semiconductor material epitaxially grown from the semiconductor plug protrusion.

Abstract: A method for a memory device having memory dies includes performing high power portions of array operations in the memory dies, ending the high power portions in the memory dies, generating a register signal after ending the high power portions, and in response to obtaining the register signal, commencing one or more input/output (I/O) operations in the memory dies.

Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a method for forming a 3D memory device includes the following operations. First, a slit structure and a support structure are formed in a stack structure having interleaved a plurality of sacrificial material layers and a plurality of insulating material layers, the initial support structure between adjacent slit openings of the slit structure. A source structure is formed to include a source portion in each of the slit openings. A pair of first portions of a connection layer is formed in contact with and conductively connected to the source portion. A second portion of the connection layer is formed in contact with and conductively to the pair of first portions of the connection layer.

Abstract: A voltage regulator can include an operational amplifier powered by a supply voltage and configured to generate a first gate voltage. The voltage regulator can also include a first transistor configured to receive the first gate voltage and generate a first driving voltage. The voltage regulator can further include a second transistor configured to receive a second gate voltage and generate a second driving voltage. The first gate voltage can be generated based on feedback provided to the operational amplifier. The second gate voltage can be generated from the first gate voltage.