Abstract: A method and circuit for relatively accurately measuring the die temperature of an IC, such as a microprocessor, by sensing one or more internal circuit elements which have an electrical parameter which varies as a function of temperature, such as an input protection diode. By sensing the one or more circuit elements which have an electrical parameter that is temperature dependent, the method provides a relatively more accurate measurement of the die temperature than measuring the outside temperature of the IC package. In addition, a control circuit is provided for cooling the IC during excessive temperature conditions by slowing down the clock frequency of the IC until the die temperature is within the temperature limit in order to optimize the utility of the IC during excessive temperature conditions.

Abstract: A port replicator is disclosed that provides for the efficient connecting and disconnecting of peripheral devices to a computer. A replicator port connector is provided on a portable computer that duplicates the pins of a other peripheral connectors on the computers. The housing of the port replicator is attached by spring clips to the computer which covers the other peripheral connectors replicated by the port replicator. The replicated connectors are then reproduced on the connector housing. Cables for peripheral devices can remain connected to the connector housing but be connected to and disconnected from the computer in a single action.

Abstract: A control circuit inhibits the CLOCK input to the CPU during power-up to prevent newer submicron CPUs from locking up during a power-up condition. The control circuit also provides a delayed control signal representing that the power supply has stabilized. This delayed control signal is used to consistently control the RESET signal.

Abstract: A laptop computer system includes a protected mode microprocessor capable of operating in restricted and unrestricted modes, and an arrangement which in response to a predetermined condition saves information from the processor and then forcibly switches the processor to its unrestricted mode of operation. When running a multi-tasking operating system where an application program is being executed in a restricted mode, a suspend/resume operation can be carried out in which the system is substantially powered down and then powered back up, and will resume the interrupted application with the restricted mode back-in effect. Further, set-up changes such as adjustment of the processor speed can be made without exiting the application program running in the restricted mode.

Abstract: A computer system has a processing unit with suspend/resume capability, a memory, and a hard disk drive. In response to a first command from the processor, the hard disk drive sends its status to the processor and the processor stores it in the memory. In response to a second command from the processor, the hard disk accepts from the processor the status retrieved by the processor from the memory, and restores itself to this status. In an alternative embodiment, the hard disk drive response to the first command by storing its status on its own hard disk, and responds to the second command by restoring this status from the hard disk. In each case, an output line from the hard disk used to control a light emitting diode is also selectively used to create an interrupt to the processor which facilitates the systems entry into the suspend mode.

Abstract: A computer system includes a memory capable of storing a plurality of data words, and a central processing unit for outputting data words to be stored in the memory. A method and apparatus for facilitating transfer of the data words from the central processing unit to the memory involve accepting and temporarily storing in a storage portion each data word from the central processing unit and then subsequently storing in the memory each temporarily stored data word, the maximum number of data words which can be temporarily stored being selectively set to one of first and second values which are different.

Abstract: A shared bus arbitration system is disclosed which provides logic allowing multiple processors to co-exist on a common bus. In the present invention, the host processor is isolated from the bus by a posted write array or write buffer. The arbitration system accepts bus lock and cycle signals when the processor writes a locked instruction to the posted write array and provides a bus lock signal to the bus when the locked instructions are written to the bus.

Abstract: A computer system includes a system bus having a plurality of address lines and having a first control line. A connector is coupled to the address lines and the first control line, and can removably receive a circuit card which can accept and/or generate signals on the address lines and first control line. A bus control circuit is coupled to the address lines and to a second control line, and can accept and/or generate signals on the address lines and second control line.

Abstract: A computer system includes a control circuit having a request input, and a pair of connectors which are electrically coupled to the control circuit and are each connected to the request input of the control circuit, each connector being capable of removably receiving a circuit card. The control circuit includes a checking arrangement for detecting a condition in which the connectors each have therein a card having a request output controlling the request input of the control circuit.

Abstract: A portable computer system includes a housing, a lid supported on the housing for movement between open and closed positions, a keyboard supported on the housing below the lid, and a display provided on the lid. When the lid is opened, the keyboard is accessible and the display is visible, whereas when the lid is closed the keyboard and display are hidden and protected. The computer system includes a processor disposed within the housing and having a first operational mode in which it executes instructions and a second operational mode in which it is in a reduced power suspend state from which it can automatically exit in response to a predetermined condition. The system includes an arrangement responsive to closing of the lid when the processor is in its first operational state for switching the processor to its second operational state.

Abstract: A system includes a main memory having a plurality of sections which each include a plurality of selectively addressable storage locations, a cache memory, and an accessing arrangement for successively requesting data from respective locations in the main memory. A method and apparatus for controlling the system involve assigning each section of the main memory a changeable status condition which is one of a caching enabled status and a caching disabled status, and inhibiting reading and storing of data by the cache memory when data requested by the accessing unit is in one of the sections of the main memory having the caching disabled status. An alternative method and apparatus for controlling the system involve selective operation in a mode in which data in the cache memory is updated even when reading of data from the cache memory is inhibited.

Abstract: A computer disk drive control adapts the rate of data transfer between a disk drive and a CPU to correspond to one of three industry standard transfer rates. The timing of disk controller signals is provided for by a two phase state machine that receives a signal representative of a selected data transfer rate and generates disk controller signals of the appropriate frequency and configuration. Such disk controller signals cause a disk controller to effect data transfer at the selected rate. In a preferred embodiment, the two phase state machine is driven by two opposite phases of a single 24 MHz clock.

Abstract: A relatively fast system control processor, such as an Intel 8051, is substituted for an Intel 8042 microprocessor in a PC/AT type compatible personal computer. In one embodiment of the invention, a System Control Processor Interface (SCPI) is provided between the central processing unit (CPU) and the system control processor (SCP) to maintain compatibility with the PC/AT bus. The combination of the faster SCP and the SCPI interface improves the overall system performance. Control circuitry is also provided for setting the A20 signal relatively quickly to allow memory access above one megabyte. In an alternate embodiment of the invention, a Mouse Keyboard Interface (MKI) is provided. The MKI provides even quicker switching of the Gate A20 signal by eliminating the need to interrupt the SCP. The MKI also provides support for a type PS/2 mouse.

Abstract: A plurality of processors form a network used to communicate with one or more peripheral devices and the system control processor. One processor is dedicated to at least one peripheral device. Since the system control processor is not burdened with the relatively slow communications protocol with the peripheral devices, it is free to do other tasks which improves the overall system performance. Communication protocol between the dedicated processors allows for local and global communication.

Abstract: A system includes a system bus having data lines, an acknowledge line, an enable line, and a control line, a data storage device, a controller circuit, and an arrangement coupling the system bus, controller circuit and data storage device. The system bus can carry out a data transfer cycle in which the acknowledge, enable and control lines are actuated and the controller obtains and checks data from the data storage device and supplies it to data lines of the bus, and a verify cycle in which the acknowledge and enable lines are actuated and the control line is deactuated and the controller obtains and checks data from the storage device but does not supply it to the bus. The controller circuit is capable of operating in different modes, in one of which it forcibly sets a false error indication in response to the verify cycle.

Abstract: A zone-bit-recording disk drive has a rotating platter with a surface which is divided into at least two zones each having a respective different number of angularly spaced sectors therein. A method and apparatus for positioning the head relative to the platter surface involve maintaining a count of the number of sectors which pass the head after the platter passes a predetermined angular orientation, ignoring the count during a time interval when the head moves out of a first of the zones toward a second of the zones which contains the specified sector and until the head has entered the second zone and the platter thereafter passes a predetermined angular orientation, and thereafter determining when the count corresponds to the specified sector to be accessed.

Abstract: In response to an address decoded in a preselected range, a multiplexer combines translated high order address bits with CPU-generated low order address bits to access random access memory, especially reserved range random access memory. Otherwise, the multiplexer merely combines CPU-generated low order bits with CPU-generated high order address bits to access RAM. An expanded memory specification memory map drives the translator to generate the translated high order address bits. This generates the address for reserved range RAM. RAM contents, normal and reserved range, are available for processing by the CPU.

Abstract: A high speed memory component, such as a cache RAM (random access memory), has a bidirectional data line and a control line (CDRAMOE) which, when respectively set to first and second electrical states, causes the memory component to respectively output data onto and accept data from the bidirectional data line. An arrangement is provided to initiate transfers of data to and from the memory component on the bidirectional data line and to produce at a first point in time a valid indication signal (W/R) indicating that one of a data read and a data write is being initiated. A method and apparatus for controlling the memory component involve the control line being set to the second electrical state at a second point in time prior to the first point in time, and the control line being maintained in the second electrical state from the second point in time to the first point in time.