Abstract: When generating a voltage Vout of a DC-to-DC converter for a load which is connected to the converter, it is necessary to monitor the quality of the voltage, in particular its amplitude. For this, provision is made for a comparator to be arranged between the output of the DC-to-DC converter and a control input of the control unit, with a first input of the comparator being connected to the output of the DC-to-DC converter (Vout), the second input of the comparator being connected to a reference voltage (Vrestore) and the output of the comparator being connected to the control input of the control unit of the DC-to-DC converter, for controlling the voltage Vout.

Abstract: A System-on-Chip includes a controller for generating a switching signal for driving a switching element of a power stage of a switched power converter. The power stage generates an output voltage according to the switching signal and an input voltage by the switching element. The controller is located on the same chip as the System-on-Chip and wherein the output voltage is generated for powering a supply domain of the System-on-Chip.

Abstract: A method is provided for controlling a power stage of a power converter configured to generate an output voltage from an input voltage according to a control law controlling a switchable power stage. The method includes generating a pulsed control signal for switching the power stage and translating the pulsed control signal in phase relative to a constant frequency clock signal. The pulse is translated forward to increase charge in a cycle. The pulse is translated backward to decrease charge in a cycle. Thus, this method of charge control does not require compensation.

Abstract: A method is provided for controlling a power stage of a power converter configured to generate an output voltage from an input voltage according to a control law controlling a switchable power stage. The method comprises generating a pulsed control signal for switching the power stage by varying a pulse width of the pulsed control signal so that a square of the pulse width is a function of a voltage error control signal derived from a difference between a reference voltage and the output voltage. This is a predictive method of charge mode control. The method is for a modulation scheme that does not require compensation for the discontinuous conduction mode.

Abstract: An FPGA power management system includes a host power management integrated circuit connected to a system power control block of an FPGA via an FPGA configuration/monitoring bus and a computing device via a power configuration/monitoring bus. The host power management integrated circuit includes a configuration and monitoring block configured to communicate configuration/monitoring signals to and from the FPGA system power control block and the computing device. The host power management integrated circuit further includes at least one voltage regulator for supplying an output voltage to an FPGA power rail according to a power configuration signal communicated by the configuration and monitoring block. The host power management integrated circuit further includes a power profiler configured to measure and supply to the configuration and monitoring block an output current on the FPGA power rail.

Abstract: An optical lens has a light sensing die integrated into the optical lens. The optical lens is extended compared to a spherical optical lens such that the optical lens is elongated in order to allow for placement of the ambient light sensing die without causing any blocking or distortion of the optical lens. The shape of the optical lens and the placement of the ambient light sensing die is compensated for the change in shape compared to a spherical optical lens thus allowing for correct focal length parametrics.

Abstract: A method and arrangement for setting an effective resolution of an output signal in an incremental delta-sigma analog-to-digital conversion by an incremental delta-sigma analog-to-digital converter, includes feeding a difference between an input signal and a reference voltage signal formed in a feedback branch to a first integrator. Safeguarding the stability of multi-stage incremental delta-sigma analog-to-digital converters for large input signal ranges and not requiring direct damping of the input signal, such that a direct SNR impairment with regard to the ADC-inherent noise sources can be avoided, is achieved by a virtual reference voltage in the feedback branch of the incremental delta-sigma analog-to-digital converter. The reference voltage signal is adapted to a changing input signal range by a settable reference capacitance and a clock cycle number dependent thereon is set.

Abstract: In a control method for a power converter, an output voltage is generated according to a control law controlling a switched power stage. During ramp up of the power converter, at least one parameter of the power stage is identified, and the control law is adapted to the identified at least one parameter of the power stage for operating the power converter.

Abstract: A current sense arrangement for switched power converters is provided wherein the clock used for sampling a sensed current of a power stage of the switched power converter is derived asynchronously from a master clock such that the local clock and the master clock are de-correlated. De-correlation can be achieved by deriving the local clock from the master clock with a modulo-m-counter having a sequence length.

Abstract: A system includes a plurality of DC-DC converters connected in parallel. Each DC-DC converter of the plurality of converters comprising an adaptive controller is configured to adaptively alter an output resistance of the DC-DC converter by adaptively altering a load line of the DC-DC converter such that a difference between each current being supplied by each DC-DC converter of the plurality of DC-DC converters into a common load is minimized.

Abstract: A switched power converter includes a switchable power stage for generating an output voltage according to a switching signal and an input voltage via a switching element. The switching signal is generated by a multi-mode controller. The multi-mode controller controls a digital control path for generating a pulse width modulation switching signal and a constant-on-time control path for generating a constant-on-time switching signal. The switching signal for controlling the switching element is generated in the digital control path when the multi-mode controller is run in a high load mode. The switching signal is generated in the constant-on-time control path when the multi-mode controller is run in a light load mode.

Abstract: A switched power converter includes a power stage for generating an output voltage according to a switching signal and an input voltage via a switching element. The switching signal is generated by a variable timing generator which is controlled by a compensator. The pulses of the switching signal are generated on a “need to have basis”. Hence, theses pulses may be generated independently of a PWM period. The pulses can be generated such that switching losses are minimized. A switching pattern can be matched to the load current pattern. Thus, the behavior of the compensator can be synchronized to a regular pattern of the load current. A high resolution variable timing generator may be employed.

Abstract: A controller of a power converter and related method pre-determine a range of suitable compensators across an end user's design space and permit the end user to configure the compensator such that the most suitable compensator is selected.

Abstract: A control method and system are provided for regulating operation of power factor correction rectifiers based on the non-symmetric boost converter topology. Control of both the front-end stage is enabled taking sinusoidal current from the utility network and a downstream converter providing isolated DC output voltage. Also provided are a method and system for reducing volume of reactive components in boost-based rectifiers with power factor correction. Flux density through the inductor is reduced with a biasing inductor current having a much lower frequency than the switching frequency of the converter.

Abstract: In a Pulse Width Modulation power converter and control method, wherein one of the operating modes steady state or load transient is detected. For either of the two operating modes one set of PID coefficients is provided for the control law that controls the duty ratio command. In case a load transient is detected, the KP gain is selected adaptively. Operating mode detection is supported by oversampling the error signal.

Abstract: In a control method for a buck power converter, an output voltage is generated according to a pulse width modulation signal and an input voltage; an error signal is generated by sampling the output voltage and differencing the sampled output voltage and an output voltage reference; a duty ratio that defines a duty cycle of a pulse width modulation signal is determined by a control law; the pulse width modulation signal is generated by providing the duty ratio to a digital pulse width modulator; a steady state or a load transient is detected; and an average inductor current is monitored and a difference between the average inductor current and a specific inductor current limit is accumulated in order to generate an offset value which is subtracted from the output voltage reference.

Abstract: A method and an apparatus for generating PWM signals is provided. Upon detection of a load transient, a new PWM period is started if the load transient occurs during the off-time of a PWM signal and exceeds a specific magnitude.

Abstract: An arrangement and a method for controlling light-emitting diodes divided into segments of an array are provided. The second terminals of all segments in the array are connected to a constant current source via one respective switching element per terminal, resulting in formation of a number n of stages, each of which has an n-th segment and an associated n-th switching element. When the amplitude of the input alternating voltage is at zero volts, all switching elements in all n stages are through-switched. An n-th reference voltage and an node voltage measured at the second terminal of a segment in stage n+1 are compared, and if the n-th reference voltage is less than the node voltage, the switching element of the n-th stage is blocked.

Abstract: A method for regulating a buck converter, in which the amount of the output volume is adjusted via a controlled switching, comprising a pulse sequence having a pulse rate and being pulse width modulated, and an inductor, which is switched serially with a load over which an output voltage drops, and an arrangement with a control input and with a control output, between which an analog-to-digital converter, a non-linear amplifier, an IIR filter, and a pulse width modulation circuit is switched, to allow a quick reaction upon a load transient by which the regulation of the output voltage at a buck converter occurs faster and with less overshooting. This is attained such that the sample rate is adjusted to be greater than the pulse rate and the pulse values of the pulse sequence are controlled during the cycle duration.

Abstract: A method for operating an electric motor with primary and secondary sections, wherein the primary section has a multi-phase exciter winding, each of the phase connections of said exciter winding being connected to an output connection of an end stage, which has controllable semi-conductor switches for applying phase voltages to the output connections, includes the following steps: a) introducing an operating phase by applying the phase voltages to the output connections such that a moving magnetic field is induced in the exciter winding, the moving field effecting a relative motion between the primary and secondary sections, b) hinting off the phase voltage at least one of the output connections to introduce a measurement phase, and c) measuring the electrical back emf induced in the winding strand in order to determine the angular difference between the phase position of the exciter current and that of the back emf.