Abstract: In a Pulse Width Modulation power converter and control method, wherein one of the operating modes steady state or load transient is detected. For either of the two operating modes one set of PID coefficients is provided for the control law that controls the duty ratio command. In case a load transient is detected, the KP gain is selected adaptively. Operating mode detection is supported by oversampling the error signal.

Abstract: A method and an apparatus for generating PWM signals is provided. Upon detection of a load transient, a new PWM period is started if the load transient occurs during the off-time of a PWM signal and exceeds a specific magnitude.

Abstract: In a method for determining absolute position of a mobile element in reference to two magneto-sensitive sensors, having a source of a magnetic field fastened to the element, a first sensor signal and a second sensor signal are measured with one magneto-sensitive sensor each. An amplitude ratio of the respective sensor signals and the off-set values about the respective zero point of the sensor signals are determined from the minimum and maximum values of the sensor signals, and from these values, scaled sensor signals are calculated that form a sum signal and a difference signal, which are scaled, with the determination of the minimum and the maximum values occurring by a relative movement of the element over a full range of motion, and an absolute position is calculated via the scaled sum signal and the scaled difference signal.

Abstract: In a control method for a buck power converter, an output voltage is generated according to a pulse width modulation signal and an input voltage; an error signal is generated by sampling the output voltage and differencing the sampled output voltage and an output voltage reference; a duty ratio that defines a duty cycle of a pulse width modulation signal is determined by a control law; the pulse width modulation signal is generated by providing the duty ratio to a digital pulse width modulator; a steady state or a load transient is detected; and an average inductor current is monitored and a difference between the average inductor current and a specific inductor current limit is accumulated in order to generate an offset value which is subtracted from the output voltage reference.

Abstract: A circuit for performing arithmetic operations includes a differential capacitive transimpedance amplifier (CTIA) and a cross-multiplexer. The cross multiplexer forwards the current to be integrated out of a plurality of current sources either to the positive input port of the differential CTIA for positive integration in direct mode or to the negative input port of the differential CTIA for negative integration in reverse mode.

Abstract: An arrangement for digital measuring a capacitive sensor is provided with a charge balance frequency converter having an operational amplifier with an inverting input, a noninverting input and an output. Between the output and the inverting input an integrating capacitor is connected, and the noninverting input is connected with a reference potential. The arrangement provides a simple switched capacitor architecture for measuring the sensor capacitance, which tolerates grounded sensor capacitors, and which is not affected by the shunt resistance. The value of the shunt resistance is determined at the same time. The arrangement makes use of a two frequency measurement of the capacitor resistance combination by using the charge balancing procedure followed by a calculation based on the results of two conversions and the ratio of the clock frequencies of the first and second conversion.

Abstract: A method for regulating a buck converter, in which the amount of the output volume is adjusted via a controlled switching, comprising a pulse sequence showing a pulse rate and being pulse width modulated, of a conductivity, which is switched serially and drops over an output voltage, and an arrangement with a control input and with a control output, between which an analog-to-digital converter, a non-linear amplifier, an IIR filter, and a pulse width modulation circuit is switched, allow a quick reaction upon a load transient by which the regulation of the output voltage at a buck converter occurs faster and with less overshooting. This is attained such that the sample rate is adjusted greater than the pulse rate and the pulse values of the pulse sequence are controlled during the cycle duration.

Abstract: A circuit for performing arithmetic operations includes a differential capacitive transimpedance amplifier (CTIA) and a cross-multiplexer. The cross multiplexer forwards the current to be integrated out of a plurality of current sources either to the positive input port of the differential CTIA for positive integration in direct mode or to the negative input port of the differential CTIA for negative integration in reverse mode.

Abstract: A capacitive-to-digital converter is provided which includes: sensor, offset and reference capacitors, an integrator circuit and a demodulation circuit. The sensor capacitor is switched according to a first clock and the offset capacitor according to a second clock, which has a higher switching frequency. The reference capacitor is switched according to a return signal from the converter's output. The integrator circuit includes an integrator capacitor, and has first and second nodes, with the sensor, offset and reference capacitors each being switched to the first and second nodes based on the respective first clock, second clock or return signal. The demodulation circuit receives and converts output of the integrator circuit into a digital output. The higher frequency clocking of the offset capacitor allows for a reduction in capacitance of the offset, reference or integrator capacitor, and the multiclocking of the converter allows for use of a multireferencing to the sensor capacitor.

Abstract: Method and system are provided for evaluating linearity of a capacitive-to-digital converter (CDC) of a capacitive sensor integrated circuit chip. The evaluating employs multiple test capacitors, which may be on-chip with the CDC, and includes: obtaining capacitance values for the multiple test capacitors and parasitic capacitances of a first input A and a second input B to the capacitive-to-digital converter; applying the multiple test capacitors in multiple permutations to the first input A and the second input B, and for each of at least some permutations, determining an error between an expected output of the CDC using the obtained capacitance values and an actual measured output of the CDC; and determining linearity error for the CDC using the determined errors for the permutations of applying the multiple test capacitors to the first input A and the second input B of the CDC.

Abstract: An adaptive switch circuit is provided, which includes a CMOS switch, an off-level voltage generator, and a booster circuit. The CMOS switch includes first PMOS and NMOS coupled transistors. The generator provides, via first and second outputs, first and second voltage levels, and includes second PMOS and NMOS transistors. The second PMOS transistor is series connected between VDD and a first bias source and the second NMOS transistor is series connected between VSS and a second bias source. The booster circuit, which is coupled to the generator between its outputs, and to the PMOS and NMOS gates of the CMOS switch, capacitively stores during off level first and second boost voltages, which are coupled to the PMOS and NMOS gates. The boost voltages are offset from VDD and VSS, respectively, each by approximately a threshold voltage of the respective transistor type.

Abstract: An arrangement for digital measuring a capacitive sensor is provided with a charge balance frequency converter having an operational amplifier with an inverting input, a noninverting input and an output. Between the output and the inverting input an integrating capacitor is connected, and the noninverting input is connected with a reference potential. The arrangement provides a simple switched capacitor architecture for measuring the sensor capacitance, which tolerates grounded sensor capacitors, and which is not affected by the shunt resistance. The value of the shunt resistance is determined at the same time. The arrangement makes use of a two frequency measurement of the capacitor resistance combination by using the charge balancing procedure followed by a calculation based on the results of two conversions and the ratio of the clock frequencies of the first and second conversion.

Abstract: A method for automatic operating voltage detection, in which one internal supply voltage (vdd) is selected from at least two different external supply voltages, with a first external voltage supply (VDDA) being applied permanently, is based on the object of reducing the circuit complexity for automatic operating voltage detection, the operating current caused by the selection arrangement and the required chip area, in which case the voltage ratios between the two different external supply voltages can be as required. This object is achieved in that a reference voltage (Vref) and a voltage (VDDreg) is produced from the first external supply voltage (VDDA), the reference voltage (Vref) is compared with a second external supply voltage (VDDIO), and either the voltage (VDDreg) produced from the first external supply voltage (VDDA) or the second external supply voltage (VDDIO) is released as an internal supply voltage (vdd), depending on the comparison.

Abstract: A circuit arrangement for producing a defined output signal in CMOS integrated circuit is provided in which the output of a sensor signal conditioning circuit is connected to the drain terminal of a first N channel depletion transistor, to a source terminal of a second N channel depletion transistor and to the output (OUT) of an integrated CMOS circuit. The gate terminals of the first and second N channel depletion transistors are connected to the output (VP) of a control circuit and the first terminal of a discharge resistance. The second terminal of the discharge resistance and the source terminal of the first N channel depletion transistor are connected to a potential VSS, and the drain terminal of the second N channel depletion transistor is connected to a potential VDD.

Abstract: A method and a system for reducing a dynamic offset during the processing of asymmetric signal strings includes reducing a dynamic offset which allows a reduction of any disturbing influence on subsequent process steps. In every no-pulse period a capacitor is discharged by an amount depending on the value of the amplitude of the voltage of the high-pass structure on the input side.

Abstract: In a method and arrangement for forming reception pulses, output signals of an upstream comparator which recognizes light pulses are used to evaluate a downstream arrangement and are newly formed and emitted as pulses. The aim is to produce a method and an associated circuit arrangement for forming reception pulses which represent a saving in energy, whereby said arrangement can be integrated into existing receiver systems, requires no external time base and can work with the signal of an upstream comparator. In a first step, an input signal delivered by an upstream comparator is delayed, whereupon a time reference is produced in a controlled manner and an output pulse begins to be formed in a controlled manner by means of the delayed input signal from the first step. The input signal level is examined once production of the time reference is completed.

Abstract: A circuit arrangement for producing a defined output signal in CMOS integrated circuit is provided in which the output of a sensor signal conditioning circuit is connected to the drain terminal of a first N channel depletion transistor, to a source terminal of a second N channel depletion transistor and to the output (OUT) of an integrated CMOS circuit. The gate terminals of the first and second N channel depletion transistors are connected to the output (VP) of a control circuit and the first terminal of a discharge resistance. The second terminal of the discharge resistance and the source terminal of the first N channel depletion transistor are connected to a potential VSS, and the drain terminal of the second N channel depletion transistor is connected to a potential VDD.

Abstract: An arrangement is provided for carrying out current-to-voltage conversion, preferably for an infrared receiver, in which the static offset, which has an interfering effect with regard to sensitivity or malfunctions, is reduced during the carrying out of current-to-voltage conversion of received input pulses. In this arrangement, outputs of a second stage are fed back to inputs of a first stage of the multistage transimpedance stage.

Abstract: Circuitry is disclosed for the calibration of heating element and ambient temperature sensors, comprising: a) an amplifier having positive and negative inputs, and an output; b) one or more heating MOS transistors selectably coupled in parallel and having 1) a heating transistor drain coupled to the positive input of the amplifier; 2) a heating transistor source configured to receive a supply voltage; and 3) a heating transistor gate coupled to the amplifier output; c) one or more ambient MOS transistors selectably coupled in parallel and having 1) an ambient transistor drain, 2) an ambient transistor gate coupled to the amplifier output; and 3) an ambient transistor source configured to receive the supply voltage; d) a temperature difference resistance configured: 1) to be coupled at least partially between an ambient connection and the ambient transistor drain; and 2) to be coupled at least partially between the ambient connection and the negative input of the amplifier.

Abstract: A method for automatic operating voltage detection, in which one internal supply voltage (vdd) is selected from at least two different external supply voltages, with a first external voltage supply (VDDA) being applied permanently, is based on the object of reducing the circuit complexity for automatic operating voltage detection, the operating current caused by the selection arrangement and the required chip area, in which case the voltage ratios between the two different external supply voltages can be as required. This object is achieved in that a reference voltage (Vref) and a voltage (VDDreg) is produced from the first external supply voltage (VDDA), the reference voltage (Vref) is compared with a second external supply voltage (VDDIO), and either the voltage (VDDreg) produced from the first external supply voltage (VDDA) or the second external supply voltage (VVDIO) is released as an internal supply voltage (vdd), depending on the comparison.