Abstract: A request processing method and apparatus, a device, and a non-transitory readable storage medium. When modifying reflink data, in the present application, first reading continuous data including currently modified data from a disk to a cache, then modifying corresponding reflink data in the cache, but not modifying other data in the continuous data, and then allocating a new address for the modified new reflink data in the disk, and mapping the cache address of the new reflink data to the new address, so as to store the new reflink data in the new address, and at the same time reducing the reference count of the corresponding reflink data in the reflink shared tree by one. In this solution, there is only one read operation and one write operation for the disk, so the problem of write amplification is reduced.

Abstract: A method, system and apparatus for the sharing of an FPGA board by multiple virtual machines. Specifically, in the present application, a PCIE virtual layer (comprising a plurality of PCIE virtual sub-layers) and a virtual PCIE device are created; one virtual machine corresponds to one virtual PCIE device, multiple virtual PCIE devices correspond to one PCIE virtual sub-layer, and one PCIE virtual sub-layer corresponds to one FPGA board, thus enabling multiple virtual machines to share and use the FPGA board through one PCIE virtual sub-layer (that is, the multiple virtual machines share one PCIE bus, and same all access the FPGA board through the PCIE bus), thereby solving the problem of some of the virtual machines being unable to be started at the same time, and enhancing the experience effect of a user.

Abstract: A siphon-based heat sink for a server comprises a heat absorbing mechanism, a siphon mechanism, and a heat sink. The heat absorbing mechanism comprises a base plate and a cover plate. The base plate comprises a bottom plate and multiple sets of heat dissipating fins, and is in contact with the central processing unit. The heat sink comprises a cooling cavity and cooling fins. The evaporation cavity is communicated with the cooling cavity via two siphon tubes to enable heat transfer and circulation of a thermal conductive medium. Lower ends of the two fin plates are positioned close to and fixed to the bottom plate, while upper ends thereof are bent outward to form a curved mechanism, and an included angle between the two fin plates continuously increases from bottom to top.

Abstract: A method, an apparatus, and a device for target detection in consecutive images, and a computer-readable storage medium. A second frame is divided into multiple sub-images, before a target in the second frame in a video sequence is detected through a target-detecting network model. A first frame is searched, according to a preset rule for motion estimation, for a corresponding image block matched with each sub-image. Pixels of a sub-image, of which the matched image block is found in the first frame, are replaced with preset background pixels. Hence, a target repeating in both frames is replaced. Finally, the second frame subject to the replacement is inputted in to the target-detecting network model, to obtain a bounding box of a target object of the second frame and a category of such target object. An algorithm for target detection in consecutive images is optimized.

Abstract: An interconnecting device for a signal plate and an interconnecting method therefor, relating to the technical field of server signal plate interconnection. The interconnecting device includes a back plate and a fine-adjustment device. The back plate includes a transverse plate and a vertical plate. Multiple sliding grooves are provided on the transverse plate and the vertical plate. A fine-adjustment device is provided on two sides of each of the sliding grooves. The interconnecting method for the signal plate comprises the following steps: (I) an IO plate is inserted into a vertical plate, (II) a CPU plate is inserted into a transverse plate; and (III) the IO plate and the CPU plate are finely adjusted and inserted.

Abstract: A circuit and a method for reducing interference of power on/off to hardware test. The circuit includes: a power unit, a voltage processing unit, a PSU and a to-be-tested hardware. An input terminal of the voltage processing unit is connected to the power unit, an output terminal of the voltage processing unit is connected to an input terminal of the PSU, and an output terminal of the PSU is connected to the to-be-tested hardware; the power unit is configured to provide an operating voltage; the voltage processing unit is configured to eliminate electric sparks caused by instability of the operating voltage at an instant of power on/off; the PSU is configured to convert a stable operating voltage outputted from the voltage processing unit into a direct current voltage required for the to-be-tested hardware; and the to-be-tested hardware is configured to receive the direct current voltage outputted from the PSU.

Abstract: A GPU Box server cascade communication method, device, and system. The method includes: detecting an i2c communication bus through a baseboard management controller (BMC) in a powered-up GPU Box server to determine whether a next-stage GPU Box server corresponding to the GPU Box server exists, and if yes, reading an IP address and location information of the next-stage GPU Box server from the i2c communication bus by means of the BMC in the GPU Box server; and storing the IP address and the location information of the next-stage GPU Box server into a data structure of the GPU Box server so that a master control server reads the data structure of the GPU Box server, and establishing network communication with the next-stage GPU Box server according to the IP address and the location information stored in the data structure.

Abstract: A production line test method, system and device for a PCIE Switch product, and a medium. The method comprises: connecting to ports of a target PCIT Switch product using cables according to a preset rule, and controlling a target configuration file to run using a target controller such that the target PCIE Switch product enters a test state, wherein the target configuration file is a file pre-stored in the target PCIE Switch product, and the target controller is a controller pre-connected to the target PCIE Switch product; reading the current running information of the target PCIE Switch product and determining whether the current running information satisfies a preset condition; and if yes, determining that a production line of the target PCIE Switch product is normal. Hence, the method can greatly improve the test efficiency of a production line of a target PCIE Switch product.

Abstract: A method, an apparatus, a device and a computer readable storage medium for designing a dual-mirror shared conf partition file are provided. The method includes pre-configuring disk space occupation capacities for a first flash mirror file, a second flash mirror file, and a shared conf partition of the BMC, and generating a FW file of the BMC which does not include a shared conf partition file. The method further includes mounting partitions configured in one of the first and second flash mirror files firstly and then mounting the shared Conf partition at last, in response to an instruction for starting the one of the first and second flash mirror files. The shared conf partition stores a configuration file of the BMC. The shared conf partition and the configuration file are automatically generated when the BMC runs normally for the first time.

Abstract: It is provided an encryption hybrid model SI simulation method based on an ADS and an HSPICE. The method includes: extracting step response data of a TX end chip encryption model by using HSPICE transient simulation; externally generating a random code signal; and taking the extracted step response data and the random code signal as input sources of ADS channel simulation, to realize active simulation to the encryption hybrid model.

Abstract: A method and apparatus for controlling fan speed are provided. The method obtains a first PWM value and a second PWM value of the fan based on the temperature of the server component respectively through a PID regulation algorithm and an open-loop control algorithm, and controls the fan speed based on the larger value of the first PWM value and the second PWM value.

Abstract: A system for capturing a trace of an NVME hard disc can include a BMC, a BIOS, a protocol analysis instrument, and a fixture plate comprising a processor and a dial switch. The BIOS is configured to acquire register error information of the PCIe link when an error occurs to a PCIe link where the NVME hard disc is located, and send the register error information to the BMC, and the BMC is configured to send the received information to the fixture plate, and the fixture plate is configured to trigger the protocol analysis instrument to capture a PCIe trace of the NVME hard disc when a current error type corresponding to the dial switch is consistent with the error type of the register error information parsed by a processor of the fixture plate.

Abstract: A folder one-key mounting method includes: determining a size of a target folder when a one-key mounting instruction for the target folder is obtained; determining a size of a mirror image file based on the size of the target folder; determining a storage path of the mirror image file based on the size of the mirror image file; generating a target mirror image file corresponding to the target folder and the size of the mirror image file, and storing the target mirror image file in a position corresponding to the storage path; and mounting the target mirror image file to a server.

Abstract: There are provided a lighting control method, system, and device for an NVME backboard, and a medium. The method is applied to a mainboard. The method includes: executing a target code for parsing a target VPP signal upon reception of the target VPP signal, where the target code is added in the mainboard in advance and stores VPP addresses respectively corresponding to NVME backboards connected with the mainboard; parsing the target VPP signal to obtain a target VPP address corresponding to the target VPP signal; and delivering the target VPP address to a target NVME backboard corresponding to the target VPP address to light the target NVME backboard.

Abstract: A method, an apparatus, and a device for transmitting a file based on a BMC, and a medium are provided. The method includes: receiving, by a second BMC, a preset command sent by a first BMC, where the preset command indicates that transmission of a file is to be initiated; parsing the preset command, and stopping an IPMI process running based on a UART interface in response to the preset command; and receiving, by using a communication function of the UART interface, a data file transmitted by the first BMC. With the method, when the data file is transmitted between the BMCs, the data file is not intercepted and verified by the preset command processing function of the IPMI process running based on the UART interface, and the IPMI process is prevented from being blocked and crashing, thereby implementing transmission of data files between BMCs.

Abstract: Provided are a method, apparatus, device for determining a network anomaly behavior. The method includes: acquiring network data traffic in a target network, and determining each data packet contained in the network data traffic as a node of a complete graph, to construct a data complete graph; optimizing the data complete graph into a minimum spanning tree by a Kruskal algorithm, and determining each node of the minimum spanning tree as a cluster center; classifying all data packets contained in the network data traffic based on cluster centers, to acquire data element sets corresponding to the cluster centers respectively; and determining an anomaly behavior in the target network based on a type of each of the data element sets, wherein the type of the data element set is determined by a type of a network attack contained in the network data traffic.

Abstract: A method, a device, an apparatus for identifying a graphics card of a GPU server, and a medium are provided. The method includes: obtaining correlation information of a graphics card captured by an operation of enumerating PCI devices during a startup process of running a BIOS; determining whether the graphics card belongs to a preset category; reading a memory address of the graphics card in a configuration space of the PCI device in a case that the graphics card belongs to the preset category, and obtaining an actual memory address based on the memory address and an offset; and resetting the graphics card based on the actual memory address, and sending a restart instruction to perform a restart operation.

Abstract: An optical mechanism and an optical system for optical-medium storage. The mechanism includes an optical-medium storage device, and an optical-medium transmission device. The optical-medium storage device is provided with an optical-medium storage module, configured to store an optical medium, and an optical-medium input-output end, configured to receive and transmit the optical medium to the optical-medium storage module and read data from the optical-medium storage module. The optical-medium receiving module is configured to receive the optical medium transmitted from outside and transmit the optical medium to the optical-medium storage module via the optical-medium input-output end, according to a receiving instruction. The optical-medium storing module is configured to form a storage path for the optical medium with the optical-medium storage module.

Abstract: A method for testing a power module includes connecting an output capacitor of the power module to a load meter; inputting an input signal, an enable signal, a PowerGood signal, and an output signal of the power module to first, second, third, and fourth channels of an oscillometer, respectively; adjusting the load meter to a no-load state, and capturing and storing the power-on waveforms and power-off waveforms of four channels of signals of the power module; adjusting the load meter to a full-load state, and capturing and storing the power-on waveforms and power-off waveforms of the four channels of signals of the power module; and determining whether the power-on sequence, power-off sequence, overshoot voltage value, and undershoot voltage value of the power module are normal based on the power-on waveforms and power-off waveforms of the four channels of signals stored by the load meter under the no-load and full-load states.

Abstract: A method and an apparatus for performing a test for a CPU, and an electronic device. A decay command in a SETWP test and a command-executing duration corresponding to each command subsequent to the decay command can be automatically deployed. Thereby, the SETWP test is correctly performed for the CPU to obtain a test result. It is not necessary to rely on manual adjustment on a parameter of a delay corresponding to each command.