Abstract: A hot plugging module power supply device, method and system are provided. When a hot plugging module is connected to a system in a hot plugging manner, a control unit transmits a first control signal to a signal processing unit. The signal processing unit forms a switch-on signal and transmits the switch-on signal to a switch unit, to gradually switch on the switch unit, to provide power to the hot plugging module. During the hot plugging module is supplied with power, when an overcurrent fault occurs in the hot plugging module, the control unit transmits a second control signal to the signal processing unit, and the signal processing unit forms a switch-off signal and transmits the switch-off signal to the switch unit, to immediately switch off the switch unit, to stop supplying power to the hot plugging module.

Abstract: A production line test method, system and device for a PCIE Switch product, and a medium. The method comprises: connecting to ports of a target PCIT Switch product using cables according to a preset rule, and controlling a target configuration file to run using a target controller such that the target PCIE Switch product enters a test state, wherein the target configuration file is a file pre-stored in the target PCIE Switch product, and the target controller is a controller pre-connected to the target PCIE Switch product; reading the current running information of the target PCIE Switch product and determining whether the current running information satisfies a preset condition; and if yes, determining that a production line of the target PCIE Switch product is normal. Hence, the method can greatly improve the test efficiency of a production line of a target PCIE Switch product.

Abstract: An architecture for improving reliability of a multi-server system is provided. The hard disk backplane is provided with at least two hard disk modules, each of which includes a power supply isolation unit and a signal isolation unit. The power connection board is connected to the power supply isolation unit in each of the at least two hard disk modules, so that power supplies of the at least two hard disk module are isolated from each other. Each of the at least two server nodes is connected to at least one of the hard disks through a corresponding signal isolation unit. The server node, the signal isolation unit and the hard disk which are connected to each other form an isolated data communication group. Signal isolation units in any two of isolated data communication groups belong to different hard disk modules.

Abstract: A method and system for drawing and rendering a graphic in real-time in a layered manner are provided. Adjacent application frames spaced with a time period are extracted, a scene change rate is calculated, and whether the scene change rate exceeds a preset change rate threshold is determined. If the scene change rate does not exceed the preset change rate threshold, graphic elements are grouped to a same graphic layer. If the scene change rate exceeds the preset change rate threshold, M application frames chronologically located between the adjacent application frames are extracted. Each application frame is divided into N regions, and a scene change rate of adjacent application frames is calculated for each region. An average scene change rate for each region is calculated, a layering operation is performed based on the average scene change rate, and graphic layers are drew and rendered separately.

Abstract: A method for lighting a backplane lamp of multiple NVMe hard disks is provided. The method includes: transmitting a VPP address to the backplane in a cyclic manner by the controller, and analyzing the address transmitted by the controller by a programmable logic device of the backplane after a data stream transmitted by the controller is received; transmitting, by the controller, hard disk lamp lighting information of a corresponding disk position to the programmable logic device of the backplane, if a VPP address analyzed by the backplane is the same as the VPP address transmitted by the controller; and performing logical conversion on the hard disk lamp lighting information, to convert a serial data stream on the VPP signal wires into a parallel signal, lighting a backplane lamp at a corresponding port, and uploading information of a position of the hard disk to the controller.

Abstract: Disclosed are a method and a structure for layout and routing of a PCB. The method includes: arranging signal lines, a power plane and a ground plane of the PCB in combination, where a portion of a reference plane for the signal lines is configured as a ground plane for providing a reference plane and return paths for the signal lines, to save routing spates. Layout of regions for the power supply, the ground and signal lines is appropriately designed, thereby improving the design density of a board, reducing the number of layers of the PCB, and saving cost.

Abstract: A GPU Box server cascade communication method, device, and system. The method includes: detecting an i2c communication bus through a baseboard management controller (BMC) in a powered-up GPU Box server to determine whether a next-stage GPU Box server corresponding to the GPU Box server exists, and if yes, reading an IP address and location information of the next-stage GPU Box server from the i2c communication bus by means of the BMC in the GPU Box server; and storing the IP address and the location information of the next-stage GPU Box server into a data structure of the GPU Box server so that a master control server reads the data structure of the GPU Box server, and establishing network communication with the next-stage GPU Box server according to the IP address and the location information stored in the data structure.

Abstract: Provided is a hard disk peak shift starting system, including: a power supply unit, a mainboard and a hard disk backplane. The power supply unit provides power to hard disks via a first power connector, a second power connector, E-Fuse chips and hard disk connectors. A Complex Programmable Logic Device (CPLD) unit sets a power-up starting sequence of the hard disks and a power-up starting time interval between the hard disks, and the CPLD unit is connected to a logical control end of each of the E-Fuse chips to control, based on the set power-up starting sequence and the set power-up starting time interval, on-off of a power supply end of each of the E-Fuse chips, to realize control of peak shift powering up and starting of the hard disks.

Abstract: A tool-less quick assembly and disassembly device for a hard disk module, including a mounting rack, a hard disk accommodation cavity being provided on the mounting rack, a multilayer hard disk support structure being provided on the mounting rack inside the hard disk accommodation cavity, and a baffle being provided on the mounting rack at a position corresponding to each layer of the hard disk support structure, the baffle being provided at the end part of one end of the mounting rack, and the other end of the mounting rack being an opening end; elastic positioning mechanisms are provided on both sides of the mounting rack; elastic clamping mechanisms are provided at the bottom of the mounting rack. The invention can enable multiple hard disks to be completely assembled and disassembled without tools, has a simple structure, is easy to assemble and disassemble.

Abstract: A server power supply device and method are provided. The server power supply device includes: a filter capacitor, a voltage collecting unit and a processing unit. One terminal of the filter capacitor is connected to a mains electricity input terminal, the other terminal of the filter capacitor is grounded, and a capacitance of the filter capacitor is greater than a preset standard capacitance. The voltage collecting unit is connected to the mains electricity input terminal and the processing unit, and the voltage collecting unit is configured to collect a first voltage inputted from the mains electricity input terminal. The processing unit is configured to process a current inputted from the mains electricity input terminal based on the first voltage collected by the voltage collecting unit, to generate a first current and supply power to a server with the first current.

Abstract: A new discharge circuit and method are provided. The new discharge circuit includes: a voltage regulation chip; a discharge control circuit a discharge switch circuit a discharge bootstrap circuit and an output circuit. An input voltage is regulated by the voltage regulation chip, and an output voltage of the voltage regulation chip is outputted to a load end via the output circuit. The voltage regulation chip is connected to the discharge switch circuit via the discharge control circuit. The output circuit is connected to the discharge switch circuit via the discharge bootstrap circuit.

Abstract: A PCB and a signal transmission system are provided. The PCB includes a connection module, and at least two signal layers and at least two reference layers spaced apart. The connection module comprises a first connection terminal and a second connection terminal. The first connection terminal is connected to at least one first signal layer and is connectable to an external optical interface. The second connection terminal is connected to at least one second signal layer and is connectable to an external electrical interface. Each reference layers is provided with a through-hole, and for each reference layers, there is an overlapping region between a projection region of an orthogonal projection of the connection module onto the reference layer and a hole region of the through-hole arranged on the reference layer.

Abstract: Disclosed are a method and a structure for layout and routing of a PCB. The method includes: arranging signal lines, a power plane and a ground plane of the PCB in combination, where a portion of a reference plane for the signal lines is configured as a ground plane for providing a reference plane and return paths for the signal lines, to save routing spates. Layout of regions for the power supply, the ground and signal lines is appropriately designed, thereby improving the design density of a board, reducing the number of layers of the PCB, and saving cost.

Abstract: An analysis method and an analysis system for optimization of a high-speed signal connector are provided. The method includes: setting an excess portion of each of a pin and a pad in the high-speed signal connector to be different lengths; equating the excess portion of each of the pin and the pad with an inductor and a capacitor; analyzing performance of connectors having different lengths of the excess portion of the pin and different lengths of the excess portion of the pad, and comparing performance parameters of the connectors; and obtaining a length of the excess portion of the pin and a length of the excess portion of the pad in a case of an optimal performance parameter, and cutting the pin and the pad based on the obtained lengths.

Abstract: A method for lighting a backplane lamp of multiple NVMe hard disks is provided. The method includes: transmitting a VPP address to the backplane in a cyclic manner by the controller, and analyzing the address transmitted by the controller by a programmable logic device of the backplane after a data stream transmitted by the controller is received; transmitting, by the controller, hard disk lamp lighting information of a corresponding disk position to the programmable logic device of the backplane, if a VPP address analyzed by the backplane is the same as the VPP address transmitted by the controller; and performing logical conversion on the hard disk lamp lighting information, to convert a serial data stream on the VPP signal wires into a parallel signal, lighting a backplane lamp at a corresponding port, and uploading information of a position of the hard disk to the controller.

Abstract: The present invention relates to the field of servers, and disclosed thereby is a peripheral component interconnect express (PCIE) structure capable of tool-free disassembly/assembly, including: a node base and a PCIE support, a board card being mounted on the node base, and the board card being provided thereon with a PCIE insertion slot; a Riser card is mounted on the PCIE support, and a PCIE card is mounted within the PCIE slot by means of the Riser card; the PCIE support is detachably mounted on the node base, and the node base on which the PCIE support is mounted may be steadily placed into a machine case. The PCIE structure provided by the present invention may simultaneously lock two adjacent PCIE supports within a node, and no tools are required for the entire assembly and disassembly process.

Abstract: A signal processing apparatus, a signal processing system and a signal processing method are provided. The signal processing apparatus includes at least one analog channel and an analog-to-digital conversion unit. Each of the at least one analog channel is configured to, in response to receiving a first analog signal inputted from outside, condition the first analog signal to generate a second analog signal, and send the second analog signal to the analog-to-digital conversion unit. The analog-to-digital conversion unit is configured to convert the second analog signal sent from any of the at least one analog channel into a digital signal.

Abstract: A tool-less quick assembly and disassembly device for a hard disk module, including a mounting rack, a hard disk accommodation cavity being provided on the mounting rack, a multilayer hard disk support structure being provided on the mounting rack inside the hard disk accommodation cavity, and a baffle being provided on the mounting rack at a position corresponding to each layer of the hard disk support structure, the baffle being provided at the end part of one end of the mounting rack, and the other end of the mounting rack being an opening end; elastic positioning mechanisms are provided on both sides of the mounting rack; elastic clamping mechanisms are provided at the bottom of the mounting rack. The invention can enable multiple hard disks to be completely assembled and disassembled without tools, has a simple structure, is easy to assemble and disassemble.

Abstract: A buffer bracket for multi layers of expansion cards is provided, which includes: an elastic base, a first supporting plate and a plurality of second supporting plates which are sequentially arranged from bottom to top, wherein the first supporting plate is fixedly connected to the elastic base, the first supporting plate is slidably connected to the adjacent second supporting plate, and the adjacent second supporting plates are slidably connected.

Abstract: Disclosed is a rack server noise monitoring system, said system comprising a sound pressure function acquiring device and a noise monitoring device; the sound pressure function acquiring device including a semi-anechoic chamber, a 4U fixture (1) being provided at the center of the semi-anechoic chamber, several microphones (2) being provided above the 4U fixture (1), and the 4U fixture (1) being located at the center of all the microphones (2.1-2.4); the microphones (2) are used for measuring sound pressure values of the 4U fixture (1) under the control of the PWM input signals of different duty ratios; and the noise monitoring device comprises a server rack and a rack management center (RMC) (6), several node mid-planes (7.1-7.3, 8.1, 8.2) being provided in the server rack, each node mid-planes (7.1-7.3, 8.1, 8.2) being connected to a fan control board (3), each fan control board (3) being connected to a fan unit (5), each fan unit (5.1-5.3) including several fans (12.1-12.15), and each node mid-plane (7.