Abstract: A SOI wafer is disclosed. The SOI wafer may be characterized by surface roughness of a top silicon layer of the SOI wafer is less than 4 ?, thickness uniformity of the top silicon layer is within ±1%, and a total number of particles on a surface of the top silicon layer of the SOI wafer, measured with setting of 37 nm of SPx detection threshold, is less than 100.

Abstract: The present application provides a method for detecting temperature of thermal chamber comprising: conducting a thermal treatment at a predicted temperature to a selected silicon wafer within a thermal chamber, wherein the predicted temperature comprises plural temperature points set in order; obtaining a haze value corresponding to the predicted temperature; obtaining a linear relationship I between the temperature and the haze; polishing and washing the silicon wafer; conducting a thermal treatment at a predicted temperature to the polished silicon wafer within the thermal chamber; obtaining a linear relationship II between the temperature and the haze; calculating a difference of the haze at same temperature point between the two thermal treatments, and obtaining an actual temperature difference of the thermal chamber based on the difference of the haze.

Abstract: The present application provides a method for detecting temperature of thermal chamber comprising: conducting a thermal treatment at a predicted temperature to a selected silicon wafer within a thermal chamber, wherein the predicted temperature comprises plural temperature points set in order; obtaining a haze value corresponding to the predicted temperature; obtaining a linear relationship I between the temperature and the haze; polishing and washing the silicon wafer; conducting a thermal treatment at a predicted temperature to the polished silicon wafer within the thermal chamber; obtaining a linear relationship II between the temperature and the haze; calculating a difference of the haze at same temperature point between the two thermal treatments, and obtaining an actual temperature difference of the thermal chamber based on the difference of the haze.

Abstract: The present invention provides a method of growing a single-crystal silicon, comprising: loading a batch of polysilicon material in a crucible of a furnace, heating the crucible to melt the polysilicon material into a mass of silicon melt, confirming a liquid surface of the mass of silicon melt, applying a superconducting magnetic field to the mass of silicon melt with a magnetic field generator and adjusting a position of the magnetic field generator to position a maximum point of the superconducting magnetic field within a predetermined range under the liquid surface, and dipping a seed crystal into the silicon melt, and pulling the seed crystal during rotation of the seed crystal to crystallize the single crystal under the seed crystal until forming an ingot of single-crystal silicon. Oxygen content in the ingot is controlled through positioning the maximum point of the superconducting magnetic field under the liquid surface.

Abstract: The present invention provides standard wafers, a method of making the same and a calibration method. The method of making a standard wafer comprise providing a silicon substrate having a first conductive type; forming a reverse epitaxy layer having a second conductive type; forming a target epitaxy layer having the first conductive type; measuring a measurement of a resistivity of the target epitaxy layer with four point probing, the measurement being utilized as a standard resistivity of the standard wafer.

Abstract: The present application provides a semiconductor substrate and a preparation process thereof. In the present application, the polysilicon layer includes the first polysilicon layer and the second polysilicon layer formed separately to generate the less stress, the more random grain orientation and the smaller grain size, maintain the high grain boundary density, and enhance the charge capture. By the combination of different deposition temperature and the combination of two cooling steps after each isothermal annealing treatment, the rate of contraction between the first polysilicon layer and the second polysilicon layer and the initial semiconductor substrate is decreased, and the thermal mismatch of semiconductor substrate is reduced. The stretch between the polysilicon layer and the initial semiconductor substrate can be reduced to prevent the warpage of the semiconductor substrate. Thereby, the stress generated during the growth process of the polysilicon layer can be further reduced.

Abstract: The present invention provides a method for calculating the liquid-solid interface morphology during growth of the ingot. The method comprises providing a wafer, selecting plural sampling locations on the wafer and detecting electrical resistivity at the plural sampling locations, calculating height differences between the sampling locations based on the detected electrical resistivity, and illustrating the morphology of the liquid-solid interface based on the calculated height differences. The method of the invention has advantages including easy operation and low cost.

Abstract: The present application provides a process of surface treatment of a silicon-on-insulator (SOI) wafer comprising: providing a SOI wafer comprising a back substrate, a top silicon layer and an insulating buried layer, wherein the insulating buried layer is located between the back substrate and the top silicon layer, and the top silicon layer has a surface roughness of larger than 10 ?; conducting a first planarization to a surface of the top silicon layer by conducting a batch annealing process at a first target temperature, and conducting a second planarization to a surface of the top silicon layer by conducting a rapid thermal annealing process at a second target temperature. The present application combines the batch annealing process and the rapid thermal annealing process to optimize the SOI wafer, especially the surface roughness of the SOI wafer. The SOI wafer planarized by the two thermal annealing processes has a good surface roughness of the top silicon layer which satisfies process requirements.

Abstract: A SOI structured semiconductor silicon wafer and a method of making the same is disclosed, comprising: loading a semiconductor silicon wafer in a first batch vertical furnace, and conducting a long-time thermal treatment; conducting a sacrificial oxidation process in a second batch vertical furnace after the long-time thermal treatment; conducting a rapid thermal annealing treatment after the second step ; wherein during the long-time thermal treatment, the semiconductor silicon wafer is kept in a protection atmosphere of pure , heated-up until meet a target temperature after changing the atmosphere of pure argon into a mixture gas of 1-n % Ar and n % H2, and then annealed in the atmosphere of a mixture of 1-n % Ar and n % hydrogen gas or pure Ar, and n is a value no greater than 10.

Abstract: A SOI wafer and a method of final processing the same is disclosed. Rapid thermal annealing comprises a first heating process in an atmosphere of a mixture of argon gas and hydrogen gas, volume of the hydrogen gas being less than 10% of whole volume of the mixture, and a first annealing process in an atmosphere of argon gas and optionally hydrogen gas, volume of the hydrogen gas being no greater than 10% of whole volume of the mixture. Long-time thermal annealing comprises a second heating process in an atmosphere of a mixture of argon gas and hydrogen gas, volume of the hydrogen gas being less than 10% of whole volume of the mixture, and a second annealing process in an atmosphere of argon gas and optionally hydrogen gas, volume of the hydrogen gas being no greater than 10% of whole volume of the mixture.

Abstract: The present application provides a method of surface treatment of a SOI wafer comprising: providing a SOI wafer comprising a substrate, atop silicon layer and an insulating buried layer, wherein the insulating buried layer is located between the back substrate and the top silicon layer, and the top silicon layer has a surface roughness of larger than 10 ?; removing a native oxide layer from a surface of the top silicon layer by conducting a first isothermal annealing process at a first target temperature, wherein the first isothermal annealing process is under atmosphere of a mixture of argon and hydrogen; and planarizing the surface of the top silicon layer by conducting a second isothermal annealing process at a second target temperature, wherein the second target temperature is higher than the first target temperature, and the second isothermal annealing process is under atmosphere of argon.

Abstract: The present invention provides a method and an apparatus of monocrystal growth. The method comprises providing an apparatus comprising a crucible, a first lifting device for lifting the crucible, a deflector tube and a second lifting device for lifting the deflector tube; setting a theoretical distance between the deflector tube and the melt surface, determining a theoretical ratio of the crucible lifting rate relative to the monocrystal lifting rate based on sizes of the crucible and the monocrystal, and starting to grow the monocrystal. During the growth, the position of one or more of the crucible, the deflector tube and the monocrystal is adjusted, the actual distance between the deflector tube and the melt surface is real-time detected, the deviation value between the theoretical and the actual distances is calculated, a variation of the ratio is obtained by the deviation value, and the theoretical ratio is adjusted based on the variation.

Abstract: The invention provides a measuring method of resistivity of a wafer, comprising: choosing a wafer to be measured, conducting a thermal treatment for the wafer to remove a thermal doner in the wafer, conducting an oxidation process for the wafer to form an oxidized surface on the wafer, and measuring resistivity of the wafer. In the method, firstly, the wafer is oxidized to get the oxidized surface, so as to restrict surface variation when placing the wafer in a later process. Therefore, the resistivity measurement of the wafer surface only slightly varies.

Abstract: The present application provides a method for verification of conductivity type of a silicon wafer. The method comprises measuring the resistivity of the silicon wafer to obtain a first resistivity, placing the silicon wafer under atmosphere of air for a predicted time period, measuring the resistivity of the silicon wafer to obtain a second resistivity, and determining conductivity type of the silicon wafer by comparing the first resistivity and the second resistivity. The method can be applied to a silicon wafer having a high resistivity such as higher than 500 ohm-cm to rapidly and accurately determine conductivity type of the silicon wafer. Advantages of the method of the present application include accurate test results, easy operation, simple device requirement, and reduced cost.

Abstract: The invention provides a method for positioning a wafer and a semiconductor manufacturing apparatus, which are applied to thin film processes. The method includes: Step S1: Obtain the state distribution of the first surface of the first wafer after the thin film process is performed on the first wafer, wherein the first surface is the surface opposite to a surface that the thin film formed thereon in the thin film process; Step S2: Determine whether the first wafer is located at the ideal positioning center according to the state distribution of the first surface, when the first wafer is not located at the ideal positioning center, according to the state distribution of the first surface adjusts the positioning position of the second wafer to be subjected to the thin film process, so that the second wafer is positioned at the ideal positioning center during the thin film process.

Abstract: The invention provides a semiconductor crystal growth device comprising a furnace body; a crucible; a pulling device; a horizontal magnetic field applying device; and a deflector, being barrel-shaped and disposed above the silicon melt in the furnace body in a vertical direction, and the pulling device pulls the silicon ingot through the deflector in the vertical direction; wherein the bottom of the deflector has different thermal reflection coefficients at different positions, and the thermal reflection coefficient of the bottom of the deflector in the direction of the horizontal magnetic field is smaller than that in the direction perpendicular to the horizontal magnetic field. According to the semiconductor crystal growth device of the present invention, the temperature distribution inside the melt silicon and quality of the semiconductor crystal are improved.

Abstract: The invention provides a method of detecting crystallographic defects, comprising: sampling wafer of an ingot in complying with a predetermined wafer sampling frequency; identifying crystallographic defects of the wafer to show the crystallographic defects of the wafer; characterizing observation of the crystallographic defects of the wafer and extracting a value characterizing the crystallographic defects; through a result of characterizing the crystallographic defects, obtaining a radial distribution of density of the wafer and categorizing the crystallographic defects; and obtaining an isogram of the crystallographic defects of the wafer to show a crystallographic defect distribution of the whole ingot according to the value characterizing the crystallographic defects and categories of the crystallographic defects.

Abstract: The present invention provides a polishing pad, a polishing apparatus and a polishing method for a silicon wafer. The polishing pad comprises a polishing surface in contact with the silicon wafer. The polishing surface is provided with at least one groove. When polishing the silicon wafer, the edge of the silicon wafer is at least partially suspended above the groove. The polishing pad, polishing apparatus and silicon wafer polishing method according to the present invention can reduce the polishing rate at the edge of the silicon wafer while keeping the polishing rate of the entire wafer basically unchanged, thereby improving the flatness of the edge thickness of the silicon wafer as well as improving the production yield.

Abstract: The present application provides a method for characterizing defects in silicon crystal comprising the following steps: etching a surface of the silicon crystal to remove a predicted thickness of the silicon crystal; conducting a LLS scanning to a surface of the etched silicon crystal to obtain a LLS map of the surface, a LSE size of defects, and defect bulk density; based on at least one of the LLS map of the surface, the LSE size of defects and the defect bulk density, determining a type of defect existing in the silicon crystal and/or a defect zone of each type of defect on the surface. By applying the method, the characterizing period and the characterizing cost can be reduced, plural defects such as vacancy, oxygen precipitate and dislocation can be characterized simultaneously, the characterizing accuracy can be enhanced, and the defect type and the defect zone can be determined with high reliability.

Abstract: A method of making a silicon on insulator structure comprises: providing a bonded structure, the bonded structure comprises the first substrate, the second substrate and the insulating buried layer, the insulating buried layer is positioned between the first substrate and the second substrate; peeling off a layer of removing region of the first substrate from the bonded structure to obtain a first film; at a first temperature, performing a first etching to etch the first film to remove a first thickness of the first film; at a second temperature, performing a second etching to etch the first film to planarize the first film and remove a second thickness of the first film, the first temperature being lower than the second temperature, the first thickness being greater than the second thickness, and a sum of the first thickness and the second thickness being a total etching thickness of the first film.