Abstract: A technique for determining the slope of a field pixel is described. According to the technique, one or more sets of diagonal field pixels are downscaled (or downsampled) before they are provided to respective edge detector circuits. By downscaling the sets of diagonal field pixels before they are provided to respective detector circuits, the edge detector circuits detect diagonal edges and, in particular, shallow diagonal edges with greater accuracy. As such, the slopes assigned to the field pixels are more likely to be correct. This ultimately results in a high quality progressive video signal that can be used to generate an image that is completely or substantially free from objectionable artifacts.

Abstract: A system and method for decoding and displaying a video bitstream representing video images and displaying the video images. The present invention discloses a split memory manager design which is particularly adapted to display MPEG-2 format video images. In addition, the present invention discloses a novel way of managing the video memory used in a video decode and display system. Finally, an intraframe video data compression system and method is disclosed to complement the disclosed video decoding and displaying system.

Abstract: A self-tuning clock recovery phase-locked loop (PLL) includes a programmable divide-by-M, a phase-frequency detector, a programmable voltage-controlled oscillator (VCO), a programmable divide-by-N, and a PLL tuning circuit, which in normal mode operation, perform as a conventional PLL. When the frequency of an input clock signal to the PLL changes by more than a threshold value, however, the PLL tuning circuit causes the PLL to be retuned for the new frequency by adjusting offset and gain parameters in the PLL such that the input voltage to the VCO is mid-way in its input voltage range when the output clock frequency of the PLL is approximately equal to the input clock frequency multiplied by a closed loop gain of the PLL, so that the VCO is operating in a linear region having wide dynamic frequency range.

Abstract: A method of bit rate control and block allocation for discrete cosine transform (DCT) image signal compression includes the steps of (a) partitioning the image signals in blocks representing portions of the total image, (b) calculating DCT coefficients for image data in all blocks, (c) obtaining a measure of block activity (BACT) for each block based on DCT coefficients and for the total image activity (ACT) as a sum of the measures of all block activity, and (d) determining a code allocation factor (AF) for each block based on the ratio of block activity (BACT) to target code volume (TCV data) for the coded image data. Thereafter, step (e) includes allocating bits for each block using the allocation factor (AF) for each block and the target code volume (DCV data).

Abstract: Disclosed is an image compression coding device in which time domain image data is transformed to frequency domain data and then compressed by multiplying the frequency domain data by quantization coefficients scaled by a scale factor based on a non-linear relationship of log(ACVdata) versus log(SF). One or more statistical passes are made through the frequency domain data using initial scale factors in which ACV data is obtained based on the newly defined relationship. The New Scale Factor (NSF) is then calculated based on the initial scale factors (ISF1, ISF2), the accumulated code volumes for the two scale factors (ACVdata1, ACVdata2), and the target code volume (TCV) of the compressed file.

Abstract: A frequency controlled clock circuit for use in a television receiver utilizes a detected sound intermediate frequency (IF) signal for use in controlling a voltage controlled oscillator and thereby provide immunity from ghost signals in the transmitted video signal. A phase locked loop responds to phase errors detected from the voltage controlled oscillator and a reference signal from the sound IF signal to control the frequency of the voltage controlled oscillator.

Abstract: A ghost cancellation system for filtering out ghosts in a received video signal including an active filter having a filtering function defined by a first set of coefficients (ak.sub.old) and having a input and a output. A transmitted ghost cancellation reference (GCR) signal is applied to the input of the active filter during a vertical blanking period to generate a filtered GCR signal at the output of the active filter. The filtered GCR signal is compared with a ghostless GCR signal to obtain an error signal, and the filter coefficients are adjusted based on the error signal to obtain a set of new coefficients (ak.sub.new). The active filter includes a feedforward FIR filter and an adder serially connected between the input and the output, a feedback IIR filter and a switch serially connected between the output and-the adder, the feedforward FIR filter and the feedback IIR filter having filtering functions defined by the coefficients.

Abstract: Encoding and decoding speed in using DCT and IDCT algorithms is enhanced by parallel operation of coding and decoding devices. A frame of image data can be vertically sliced with each slice operated on by a dedicated encoding device and with the encoded slice data concatenated to form the encoded frame of data. Decoding speed is increased by using a plurality of decoding devices in parallel with each decoder having a Huffman decoder and a coefficient dequantizer through which all coded data flows. Only assigned blocks of data are operated on by the IDCT unit in each decoder. Each decoder device can have a plurality of IDCT units for operating on assigned blocks of data.

Abstract: Disclosed is a television ghost cancellation system based on digital filtering. A baseband video signal at the output of the demodulator is lowpass filtered before being digitized at an analog-to-digital converter. The signal is then processed in digital filters to remove the ghosts. The clean digital signal is then passed to a digital-to-analog converter and lowpass filter to become a clean baseband video signal. The digital filters consist of a feedforward section and a feedback section. The coefficients of the digital filters are calculated by digital signal processor, which processes the data stored in First-In-First-Out buffers (FIFOs). The FIFOs are used as outputs, while one FIFO is used as input to the feedback section. The FIFO stores the standard ghost canceler reference (GCR) signal. Switches are controlled by a synchronization separation circuitry. The coefficients of the feedforward section are estimated by processing data stored in the FIFO.

Abstract: A concurrent vector signal processor includes a resource manager for utilization of captive signal processing resources. The first instructions in a temporary instruction queue are predecoded and the signal processing resources are selected to execute those first instructions.Arbitration system is provided for external buses connected to a concurrent vector signal processor. A processor arbiter supervises on a priority basis both captive processor resources and independent processor resources. A bus arbiter supervises on a priority basis external and internal buses.

Abstract: Multiple special purpose processing units are provided in a vector signal processor for concurrent, parallel processing, particularly of complex vectors. The principal processing units are an execution unit, a data movement unit, a control/register unit, a vector buffer unit, an instruction fetch unit, and a bus interface unit.

Abstract: A memory matrix comprises a plurality of word lines, a plurality of bit lines, and a stacked diode and voltage-variable resistor structure interconnecting bit lines to word lines. The stacked diode and voltage-variable resistor structure includes a doped region in a semiconductor substrate defining a work line, a doped polycrystalline silicon layer over said word line and forming a p-n junction therewith, and an amorphized region in the doped polycrystalline silicon layer having increased resistance over the non-amorphized portion of the doped polycrystalline silicon layer. A contact is made to the amorphized polycrystalline silicon material which preferably includes a titanium-tungsten barrier layer and an aluminum layer over the barrier layer.

Abstract: A discrete cosine transform/inverse discrete cosine transform or DCT/IDCT integrated circuit capable of performing both DCT and IDCT, includes a processor for processing DCT/IDCT data including, input buffer and arithmetic logic unit for processing incoming data and first pass processed data, multiplier and accumulator unit for performing mathematical operations on DCT/IDCT data, and output buffer and arithmetic logic unit for processing first pass processed data and outgoing data. Also provided is an interleaved random access memory for storing DCT/IDCT data during various stages of processing.

Abstract: An arithmetic unit for a vector signal processor implements IEEE Standard 754 for Floating-Point Arithmetic. The arithmetic unit includes three pipelined floating-point computational blocks: a multiplier, an adder-subtracter, and an adder to provide for high computation throughput for digital signal processing (DSP) operations. The adder-subtracter and the adder have the same input operands, so that the sum and difference of these input operands can be computed simultaneously. A first and a second internal data bus are provided for transferring data and instructions within the arithmetic execution unit. The input/output operands and partial results are stored in a set of auxiliary registers. Most of these registers can be organized in pairs that for complex arithmetic computations are used to store the real and the imaginary parts of a complex operand. A register-pair can also simultaneously handle two different real operands.

Abstract: Voltage on a circuit ground terminal in an output buffer is controlled by limiting induced voltage on a circuit ground pad as the output makes a transition from a high voltage level to a low voltage level thereby minimizing deleterious effects on other circuits connected to the common circuit ground terminal. A ground bounce circuit controls the bias on a transistor connecting the output to the circuit ground terminal with power saver circuitry limiting actuation of the ground bounce circuitry except during the high to low transitional phase.

Abstract: Memory address generation circuitry includes two binary counters for generating addresses for application to an address bus. The least significant bits of one counter are connected to the address bus in bit positions corresponding to the most significant bits of the other counter whereby the two counters increment addresses in opposite directions. The mode of address generation permits addresses for data in normal order, data within data blocks in normal order and data blocks in reverse-bit order, and data within data blocks in bit-reverse order and data blocks in normal order. The circuitry has particular applicability in memory address generation when operating on data with algorithms for FFT operations in one or more dimensions.

Abstract: A voltage-programmable device in which the programming voltage V.sub.p and the "off" resistance R.sub.i are separately controlled. The device includes a body of semiconductor material having a doped region therein, and an amorphized layer in the doped region and abutting a surface, and a surface layer in the amorphized layer with the surface layer having a resistivity higher than the resistivity of the amorphized layer prior ot programming of the device. The surface layer has a miniscule thickness (on the order of 50-150 Angstroms) and does not affect the programming of the device. Moreover, the final resistance of the programmed device is not significantly affected by the presence of the first layer. The amorphized layer is formed by ion implantation, and the or by oxygen plasma treatment.

Abstract: Circuitry for use in operating on block floating-point data where all data in a block has a scale factor associated therewith including a maximum scale register for storing the maximum scale factor of the data in a block, a subtractor for obtaining a difference value between the maximum scale factor and a data scale factor as the data is retrieved for operation, and a computer for adjusting the scale of retireved data by the difference prior to operation on the data. As the data in a block is operated on scale overflow is stored and used to adjust subsequent data as read from memory prior to operation thereon. A counter is provided for counting all scale overflow as a result of operations on all data in a block with the maximum scale register being updated based on the total count following operations on all data in the block.

Abstract: An electrically programmable element is fabricated in a P-N junction isolated region of a semiconductor body by first extending the depth of the region in the body by introducing dopants through the region into the body by ion implantation or by diffusion and drive-in, and thereafter forming an amorphotized layer in the first region overlying the extended portion. The increased depth of the first region provided by the second region prevents damage to the P-N junction between the semiconductor body and the first region during formation of the amorphotized layer.

Abstract: A digital filter processor employs four multiplier-accumulator cells and an output accumulator for receiving and accumulating all cell outputs. Data is provided to all cells in parallel, and finite impulse coefficients are applied serially to all cells. A plurality of registers and at least one multiplexer interconnect the cells for transmitting the coefficients between cells. The registers can be employed for sample rate reduction or decimation. A plurality of processors can be cascaded for processing an increased number of coefficients without a reduction in sample time. Alternatively, data can be recycled in a processor to accommodate a number of coefficients greater than the number of cells at a reduced sampled sample rate. A cell address is provided for selecting cell outputs during the reading of the filtered/processed data.