Abstract: An electronically programmable gate array comprises a plurality of rows of logic cells with each cell having a plurality of inputs, at least one output, and a plurality of electronically programmable voltage levels for configuring the cell. A plurality of sets of interconnect lines are formed in the array with one set of interconnect lines provided between adjacent rows of logic cells with electronically programmable contacts connecting inputs and an output of each cell in a row of cells with two adjacent sets of interconnect lines. Each row of logic cells preferably includes alternating three-input cells and two-input cells. Each electronically programmable voltage level comprises two voltage alterable resistors serially connected between first and second voltage potentials. Each electronically programmable interconnect comprises a voltage alterable resistor.

Abstract: Vector dot multiplication is facilitated in a multiplier in which pipelining techniques are employed. Two vectors u(i), v(i), each having the same number of components (L), the components of the vector u(i) having m bits, and the components of the other vector v(i) having n bits per component. For example, a classical positive integer dot multiplier includes m-1 multiplier rows with each multiplier row having n+1 multiplying stages, each stage including an adder and latches. A latch interconnects the carry-out of each adder in a row to the carry-in of another adder in the same row, and a latch interconnects the sum output of each adder in a row to an input of another adder in another row. The result is accumulated in an adder according to the length of the vectors to be processed. 2's compliment number multiplication is accommodated by stretching each multiplier row by connecting two full adders serially therewith.

Abstract: A semiconductor structure with ohmic contacts and variable resistance contacts has an interconnection pattern to the contacts including a first barrier metal in contact with the variable resistance contacts and a second metal contacting the barrier metal and the ohmic contacts. The barrier layer protects the amorphotized crystalline structure of the variable resistance contacts. Fabrication processes are described.

Abstract: A programmable logic gate includes first and second complementary field effect transistors having gate terminals connected to receive a first input signal. A first variable resistance is connected in series with the first transistor, and a second variable resistance is connected in parallel with the second transistor. The variable resistances can be fusible links or variable resistance semiconductor devices. By increasing the resistance of the first variable resistance and decreasing the resistance of the second variable resistance, the input signal becomes ineffective in the logic gate. Conversely, by decreasing the resistance of the first variable resistance and increasing the resistance of the second variable resistance, the input signal becomes effective in operation of the logic circuit. In programming the transistors, one transistor is effectively disconnected from the gate and the complementary transistor is effectively shorted.

Abstract: A programmable read only memory (PROM) includes voltage programmable structures which are readily fabricated to provide predictable and selectable programming voltages. The resistor structure includes a body of semiconductor material having high electrical conductance and a surface contact region having a crystalline structure characterized by relatively high electrical resistance. The relatively high electrical resistance can be established by amorphotizing the surface region or by forming lattice defects in the crystalline structure such as by ion implantation. In programming the PROM, a sufficient voltage is applied across, or sufficient current is applied through, selected structures whereby the surface regions thereof are heated sufficiently to reduce the relatively high electrical resistance.