Abstract: Within a data processing system, a pool of facilities are allocated to an operating system, where each facility within the pool of facilities has an associated real address. The operating system allocates from the pool at least one bypass facility to a first process that the first process is permitted to directly access by its associated real address without first obtaining translation of a non-real address. The operating system also allocates from the pool at least one protected facility to a second process that the second process accesses only by translation of a non-real address to obtain the real address associated with the protected facility. Accesses to the facilities are either protected or unprotected based upon the state of a bypass field within a request address.

Abstract: A magnetic head having read and write elements is provided according to one embodiment. The head includes a substrate. An undercoating is coupled to the substrate. The undercoating has a preferred thickness of between about 1.5 and 0.5 microns or less in a direction perpendicular to the planar surface of the substrate engaging the undercoating. Preferably, the undercoating is reduced to a desired thickness during fabrication using chemical mechanical polishing. The undercoating is constructed of a material having a thermal conductivity greater than that of amorphous Al2O3. An electric contact pad is operatively coupled to a layer positioned between the pad and the undercoating. Electric contact pads of read and write elements are preferably separated from the undercoating by insulation planarization layers. A write element is coupled to the undercoating. The write element has an electrically conductive coil.

Abstract: A passive optical marker for use in accordance with an electronic whiteboard system that selectively allows a reflector associated with the optical marker to be exposed to a light emitting source. Thus, the optical marker of the present invention selectively provides information pertaining to the location of the optical marker and pen-up/pen-down states.

Abstract: An optical switch comprises input channels with input optical free-space elements, an intermediate optical free-space element, and input tunable optical lenses with adjustable projection characteristic for projecting lightwaves received from the input optical free-space elements into the intermediate optical free-space element. The switch further comprises output channels with output optical free-space elements, and output tunable optical lenses with adjustable reception characteristic for capturing the lightwave from the intermediate optical free-space element and for feeding the lightwave to the output optical free-space elements. The optical switch can be integrated into a substrate. The tunable lens can be implemented with an individually tunable heater. By adjusting the heaters one can control the projection characteristic of the light beam emitted into a free-space element. Also an asymmetrical switch arrangement is possible.

Abstract: A method, mold and apparatus for encapsulating and underfilling an integrated circuit chip assembly. The mold has a first portion and a second portion with the first portion having first and second cavities and at least one channel interconnecting said first and second cavities. The first cavity is adapted to enclose said integrated circuit chip on said substrate. A clamping force is applied to the first and second portions of the mold to clamp the substrate between them with the integrated circuit chip located in the first cavity. Vents exhaust air from the first cavity. Encapsulant is injected into the first cavity of the first portion at a location in the first portion remote from the point of connection of the channel such that encapsulant flows around and underneath the integrated circuit chip and through the channel into the second cavity to thereby underfill and encapsulate the integrated circuit assembly.

Abstract: A memory system for a computational circuit having a pipeline includes at least one functional unit and an address generator that generates a memory address. A coherent cache memory is responsive to the address generator and is addressed by the memory address. The cache memory is capable of generating a cache memory output. A non-coherent directory-less associative memory is responsive to the address generator and is addressable by the memory address. The associative memory receives input data from the cache memory. The associative memory is capable of generating an associative memory output that is delivered to the functional unit. A comparison circuit compares the associative memory output to the cache memory output and asserts a miscompare signal when the associative memory output is not equal to the cache memory output.

Abstract: An apparatus and method for transferring files between a plurality of computers in a virtual network is disclosed. The present invention allows the selective transference of files between designated computers in a virtual network. The computers contain a VNRS program that allows a computer to display another computer's desktop next to its own. Although the two computers are not physically connected, the present invention allows files to be transferred from the first computer to the second computer and vice versa by merely dragging and dropping icons from one desktop to another.

Abstract: The present invention automatically links web documents to other, existing web documents. Specifically, when a web document is requested, the content therein will be compared to an index of references and addresses to determine whether any related web documents exist. If any of the content matches any of the references in the index, a related web document does exist. The address corresponding to the related web document will then be bound to the matching content of the requested web document. This process occurs before the web document is displayed to the user and alleviates the problems associated with hyperlinks to non-existing web documents.

Abstract: A move engine and operating system transparently reconfigure physical memory to accomplish addition, subtraction, or replacement of a memory module. The operating system stores FROM and TO real addresses in unique fields in memory that are used to virtualize the physical address of the memory module being reconfigured and provide the reconfiguration in real-time through the use of hardware functionality and not software. Using the FROM and TO real addresses to select a source and a target, the move engine copies the contents of the memory module to be removed or reconfigured into the remaining or inserted memory module. Then, the real address associated with the reconfigured memory module is re-assigned to the memory module receiving the copied contents, thereby creating a virtualized physical mapping from the addressable real address space being utilized by the operating system into a virtual physical address space.

Abstract: A handle having a handle body, a latching arm, and a pivot block is provided. The handle body has a release finger and a pivot leg. The latching arm is slideably secured to the handle body. The pivot block is connectable to a device having at least one movable component. The pivot block is also connected to a first portion of the pivot leg so as to allow the handle body to rotate in the pivot block about the first portion between a first position and a second position. The first position is a locked position and the second position is a latched position.

Abstract: A process for planarizing a patterned metal structure for a magnetic thin film head includes the steps of applying an encapsulation/planarizing material on a substrate, spinning the substrate in a photoresist spinner or similar machine, curing the encapsulation/planarizing layer by energetic particles such as an electron beam. The planarizing process further comprises the step of polishing the entire structure using a conventional chemical-mechanical polishing step. The curing step takes place at the substrate temperature less than 200° C., which prevents the damages of the thin film head structures such as MR and GMR sensors. This process is cheap, efficient and easy to apply.

Abstract: Described is a method for erasing data recorded in a data storage device in which a data bit is written onto a surface by applying a first combination of energy and force to the surface via a tip to form a pit in the surface representative of the data bit by local deformation of the surface. The method comprises applying a second combination of energy and force via the tip to prerecorded deformations of the surface to be erased to substantially level the surface.

Abstract: A processor contains a move engine and mapping engine that transparently reconfigure physical memory to accomplish addition, subtraction, or replacement of a memory module. A mapping engine register stores FROM and TO real addresses that enable the engines to virtualize the physical address of the memory module being reconfigured and provide the reconfiguration in real-time through the use of hardware functionality and not software. Using the FROM and TO real addresses to select a source and a target, the move engine copies the contents of the memory module to be removed or reconfigured into the remaining or inserted memory module. Then, the real address associated with the reconfigured memory module is re-assigned to the memory module receiving the copied contents, thereby creating a virtualized physical mapping from the addressable real address space being utilized by the operating system into a virtual physical address space.

Abstract: A method and system for reducing noise in a power grid of an integrated circuit, which optimizes the placement and sizing of decoupling capacitors in the power grid. Logic cells are located in a first layout of the integrated circuit with empty spaces between the adjacent cells, and the placement of the cells is changed to a second layout wherein the size of the empty spaces between the adjacent cells also change. The decoupling capacitors are placed in the empty spaces of the second layout. In the example of a row-oriented cell structure, the empty spaces may be uniformly distributed along each row for the initial layout. An adjoint sensitivity analysis is performed of the sensitivity of a noise function of the integrated circuit with respect to sizes of the empty spaces between adjacent cells, and an original noise waveform is convolved with an adjoint noise waveform. The convolution may use piecewise linear compressions of the original and adjoint noise waveforms.

Abstract: A data processing system includes a global promotion facility containing a plurality of promotion bit fields, an interconnect, and a plurality of processing units coupled to the global promotion facility and to the interconnect. A first processing unit includes an instruction sequencing unit, an execution unit that executes an acquisition instruction to acquire a particular promotion bit field within the global promotion facility, and a promotion awareness facility. In response to the first processing unit snooping a request by a second processing unit for the particular promotion bit field, the first processing unit records an association between the second processing unit and the particular promotion bit field in the global promotion facility.

Abstract: The present invention relates to a method of operating a crossbar switch (1) having a control logic (2) and n input ports (i—0, . . . , i_n-1) and m output ports (o—0, . . . , o_m-1), wherein information packets of p different priority levels are routed from said n input ports (i—0, . . . , i_n-1) to said m output ports (o—0, . . . , o_m-1). Within said control logic (2), a pool (CRA) of buffers (CRA—0, CRA—1, . . . ) is provided for each crosspoint (4) for temporarily storing address information related to said information packets.

Abstract: A method and system for modeling effective capacitance of logic circuits provides accuracy without iteration and an improved understanding of logical circuit block performance variation with implementation changes. An effective output capacitance of a logical circuit output node is calculated. The equivalent resistance of the output node is determined by modeling at least one of the output transistors using a transfer conductance model relating the input voltage function to the output current. The values in a pi-network model of the output impedance are determined from circuit design parameters relating the distributed resistance to the equivalent resistance of the output transistor and relating the distributed capacitance of the output transistor and relating the distributed capacitance to the two capacitances in the pi-network. The effective output then capacitance is determined by equating the time delays of the pi-network model and a simple parallel RC combination.

Abstract: Methods, systems and apparatus which resample a primal mesh signal composed of primal points associated with primal mesh vertices of a primal mesh connectivity of a primal mesh producing a dual mesh signal composed of dual points associated with primal mesh faces of said primal mesh connectivity. The dual points are computed by minimizing a quadratic energy function. The quadratic energy function is composed of a sum of square terms. The invention also constructs a dual mesh from a primal mesh, with the dual mesh signal constructed with the resampling method. It also smoothes a primal mesh signal of a primal mesh. It also constructs a primal-dual mesh from a primal mesh, with the primal-dual mesh connectivity of said primal-dual mesh constructed using a prior art method, and the primal-dual mesh signal constructed by concatenating said primal mesh signal and a dual mesh signal computed with the resampling method.

Abstract: A data processing system includes a global promotion facility and a plurality of processing units coupled by an interconnect. At least one processing unit among the plurality of processing units includes one or more second caches having cache arrays in which instructions and operand data are cached, an instruction sequencing unit, an execution unit that executes an acquisition instruction to acquire a promotion bit field within the global promotion facility exclusive of at least one other processing unit, and a promotion cache separate from the one or more second caches. In response to acquisition of the promotion bit field by the first processor, the promotion cache of the first processor stores the promotion bit field separately from instructions and operand data.

Abstract: Server performance is monitored by inserting code into servlets running on the server. Code is inserted at the servlet beginning to record start time, servlet name and input parameters in a table in memory on the server. Code is also inserted at the exit and exception points of the servlet to record stop time in the table and to determine whether to add this information in the table to an array in a web page a log file. The web page or log file is then examined to determine server performance.

Abstract: A process for controlling focus parameters in a lithographic process used in manufacture of microelectronic circuits. The process comprises initially providing a lithographic mask having a target mask portion containing a measurable dimension sensitive to defocus, projecting an energy beam through the target mask portion onto a first location of a substrate at a first focus setting, and lithographically forming a first target on the substrate corresponding to the first focus setting, the first target containing a measurable dimension sensitive to defocus. The process then includes projecting an energy beam through the target mask portion onto a second location of the substrate at a second focus setting, lithographically forming a second target on the substrate corresponding to the second focus setting, the second target containing a measurable dimension sensitive to defocus, and measuring the defocus sensitive dimension for each of the first and second targets on the substrate.

Abstract: A 64-bit adder implemented in partially depleted silicon on insulator technology and having two levels of lookahead uses a dynamic eight-bit carry module containing a cascode evaluation tree employing a chain of source followers that feeds a sense amplifier, thereby obtaining benefits from high initial drive, low variation in body voltage, resulting in low variation in history-dependent delay, reduced noise sensitivity and noise-based delay.

Abstract: A circuit arrangement and method are used in connection with a data latch that is coupled to a data source over a source synchronous communications interface to disable the data latch from latching data whenever the data source is not driving the source synchronous data strobe signal. As such, when the data source is not driving the source synchronous data strobe signal, undesired and/or inadvertent latching by the data latch can be avoided. Moreover, in implementations where a data strobe signal line is bidirectional, and capable of being driven either by the data source or by another circuit used to access the data source (e.g., a memory controller), disabling data latching as described herein can minimize the risk of driver damage resulting from conflicting attempts to drive the data strobe signal line at both ends.

Abstract: A Virtual Network Resource Sharing (VNRS) system having a CPU and RAM offloading and sharing program is disclosed. The CPU and RAM offloading and sharing program modifies CPU and RAM utilization among participating machines. The VNRS program analyzes the CPU and RAM usage on a plurality of machines connected via a virtual network, specifically the applications running on those machines. The VNRS program reorganizes the applications amongst the participating computers such that the optimum performance is achieved for the network.

Abstract: A multiprocessor data processing system includes first and second processors coupled to an interconnect and to a global promotion facility containing at least one promotion bit field. The first processor initiates execution of a branch-type instruction to request acquisition of a promotion bit field exclusive of at least the second processor. In response to the branch-type instruction, the first processor issues an access request to acquire the promotion bit field. After the accessing request, a register of the first processor receives a register bit indicating whether or not the promotion bit field was successfully acquired by the access request. As a part of executing the branch-type instruction, the first processor selects among a first execution path and a second execution path in response to the register bit.

Abstract: A visual query system, and associated method and computer program product enhance and accelerate content-based querying, and present a new image similarity measure using known or available software applications and hardware components of video compression systems. The present system encodes images as consecutive frames in a video sequence and uses the ratio between the file length of the compressed sequence and the original file length as a distance measure. The system considers the compression ratio to be an estimate of the entropy of the combined images, which can be used to estimate the amount of new information introduced from one image to the other.

Abstract: A pulse generator circuit is disclosed including a delay element coupled to a logic circuit. The delay element receives a clock signal CLK and a signal X and produces a signal XN dependent upon the clock signal CLK and the signal X. The logic circuit receives the clock signal CLK and the signal XN and produces a signal ACLK such that ACLK=CLK·XN′. The signal ACLK may include a series of positive pulses. The delay element may be, for example, one of multiple delay elements coupled in series, and signal X may be an output of a preceding one of the delay elements. A semiconductor device is described including the above pulse generator circuit and a self-resetting logic circuit. The self-resetting logic circuit receives the signal ACLK and one or more input signals and performs a logic operation using the one or more input signals during the positive pulses.

Abstract: A method of copying an operating system image in a cluster computing environment that has virtually unlimited scale does not require the strict amounts of control over installation that current methods have, but rather causes operating system images to propagate themselves in a cluster environment, spreading from one node to the next until the entire cluster is installed. Broadcast storms and response storms during installation are avoided by employing a regulation method that automatically delays installation during busy periods. The method does not require any prior knowledge of the number of nodes in the cluster, or the cluster network configuration.

Abstract: Method of accessing Internet resources provided by at least a content server in a data transmission system including a proxy connected to an Internet network, the proxy being provided with authentication means for authenticating a user when receiving a request for Internet resources therefrom, and wherein the proxy transmits the user request to the content server which sends back a response to the proxy together with at least one cookie containing information about the user's session. The proxy receiving the response with the cookie stores the cookie in a user context database and transmits this response to the user after the cookie(s) has (have) been removed from the response, so that the user can send all requests for accessing the Internet resources contained in the content server to the proxy.

Abstract: A method of inducing phase changes in a FIR filter is provided. The FIR filter consists of a concatenation of tunable couplers and tunable delay lines made of planar waveguides fabricated in SiON technology, forming a plurality of interferometers, at least one of which carries a heater on at least one of its waveguide arms. The method includes the step of exposing at least one of the arms of the interferometers to an irradiation at UV or a smaller wavelength, thereby inducing a change in the refractive index of the waveguide arms which induces the phase difference change. The method provides a procedure that will lead to temperature-stable changes of the refractive index of the waveguides. The resulting device is temperature-stable such that it can be afterwards be heated with chromium heaters to dynamically tune its spectral response without destroying the UV-induced changes.

Abstract: A system, method and article of manufacture are provided for securing data. Security rules are defined for fields and/or field values. The security rules specify one or more users to which the rules apply. A query is examined for content and a determination is made as to whether security action is required based on the content (e.g., a field and/or a value of the field) and user-specific data.

Abstract: A method and computer system is described for designing a conflict-free altPSM layout by first constructing a planar interlock graph without predefining phase shift shapes. Feature nodes of the graph represent critical elements, while connection nodes of the graph represent phase shape interactions. A pattern analysis of the interlock graph is performed to identify layout violations. Solutions for resolving layout conflicts are applied to the layout resulting in at least one conflict-free altPSM layout. Phase shapes are then applied to the conflict-free altPSM layout. Selection of an optimal solution can be made based on cost analysis.

Abstract: A method of operating a request FIFO of a system on a chip (SoC) in which a requests in a first position that has been granted and which subsequently receives a retry from the intended target is automatically re-ordered with respect to the other requests below it in the request FIFO. Each issued requests is tagged to either enable or disable a re-order feature. When a request that is tagged as re-order enabled is granted, the FIFO logic monitors the response provided for the request. If the response is a retry, the request is removed from the first position of the request FIFO and the next sequential request is moved into the first position. The removed requests may be re-ordered within the request FIFO or sent back to the initiator. In the former implementation, controller logic reorders the first request within the request FIFO.

Abstract: A keyboard having keys in or on which are situated changeable display elements, e.g., LCD, LED, LEP or the like, so that an image displayed on the display element is viewable on the keycap surface by a user.

Abstract: The present invention generally is directed to a system, method and article of manufacture for generating a reusable query component. The reusable query component may include one or more query conditions and may be used to facilitate building a database query including the one or more query conditions. Reusable query components may also include reusable query subcomponents, each including one or more query conditions. The query subcomponents may be statically or dynamically linked to the reusable query component.

Abstract: A common interface (API) is provided which permits a single diagnostic probe manager to communicate with and to control a plurality of diagnostic probes. Through this interface the diagnostic probes are enabled to pass information concerning dependencies between software levels present in a hierarchical stack. This information is particularly useful in that it permits the probe manager to direct diagnostic efforts at the lowest desirable level so as to avoid the problems that occur when problems are indicated at a high level but which are actually caused by lower level software components.

Abstract: An alert system and associated method protect against accidental loss or intentional theft of personal valuables. Users may define a set of corrective actions associated with each satellite item registered with the alert system. The alert system is generally comprised of a plurality of alert devices, a plurality of remote sensors, and at least one processing unit. When a satellite item provided with the alert device becomes separated from its user, the item alerts the user of an impending loss or separation prior to the occurrence of such an event.

Abstract: A system and method for processing documents, such as XML documents, wherein the method includes the steps of: receiving a query comprising search criteria; receiving at least a portion of a document; modifying the search criteria such that constraints specifying a backward relation may be reformulated into constraints specifying a forward relation; processing the document using the modified criteria; and locating one or more nodes that satisfy the search criteria; and, emitting the selected nodes as output.

Abstract: A device has one or more memories that store a set of position points defining respective locations within one or more physical areas. A communication interface on the device communicates with one or more signal sources located at one or more of the respective locations proximate to the position detection device. Each of the signal sources responds to the device with information about the respective location. A path process defines one or more paths connecting one or more of the position points in response to a user query. The path process accesses the information from one or more of the signal sources and determines the progress of the device user through the physical area as defined by the path. A user interface communicates the progress through the physical area to the user.

Abstract: Document-searching using a compiling device for generating a two-state input automaton for enabling a state transition by storing an input query expression, performing parsing, and reading at least two states from different types of nodes in an element identifier, and a storage device for storing the two-state input automaton. Also included is an automaton-evaluating device for enabling three state transitions by reading out a two-state input automaton from the storage device and storing the automaton, while reading in a document and identifying the input two states.

Abstract: A method, computer program product, and data processing system for automatically designing routing paths in an integrated circuit is disclosed. The present invention allows for the design of paths that are optimal in terms of the signal delay in circuits that may require registers for signal to travel over multiple clock cycles or in circuits that may contain multiple clock domains.

Abstract: A data processing system with a snooper that is capable of dynamically enabling and disabling its snooping capabilities (i.e., snoop detect and response). The snooper is connected to a bus controller via a plurality of interconnects, including a snooperPresent signal, a snoop response signal and a snoop detect signal. When the snooperPresent signal is asserted, subsequent snoop requests are sent to the snooper, and the snooper is polled for a snoop response. Each snooper is capable of responding at different times (i.e., each snooper operates with different snoop latencies). The bus controller individually tracks the snoop response received from each snooper with the snooperPresent signal enabled. Whenever the snooper wishes to deactivate its snooping capabilities/operations, the snooper de-asserts the snooperPresent signal. The bus controller recognizes this as an indication that the snooper is unavailable.

Abstract: This invention describes a new method for forming and depositing thin films of crystalline dielectric materials. The present technique uses chemical synthesis to control the granularity and thickness of the dielectric films. This method has several key advantages over existing technologies, and facilitates the integration of crystalline dielectric materials into high-density memory devices.

Abstract: An anonymous peer-to-peer network has a security protocol that allows hosts in the network to determine whether data received from the network is valid. The requesting host can explicitly determine the data transfer route in packet header information. Each host address on route is encrypted with a public key of a directly preceding host. Consequently, the requesting host can exclude from the data transfer route any host through which the requesting host does not wish to route data. Error detecting codes are used to validate the transmitted data.

Abstract: A method and apparatus for managing data structures associated with large files are provided. With the apparatus and method, region control blocks for a data file are allocated on demand from an array of control blocks and are organized into a tree data structure. The tree data structure includes a base region control block and zero or more extended region control blocks. The base region control block includes a pointer to a root of the tree data structure and information about the data file. The extended region control blocks have pointers to the base region control block, to a successor region control block, and pointers to zero to four child region control blocks. Using this tree data structure, the operating system may perform various operations on the region control blocks with improved performance.

Abstract: To detect alignment and/or absence of a tape leader pin in an opening of a tape cartridge, a light source scans the opening. Detection logic analyzes the detected reflection waveform signal for deviation from a cylindrical surface reflection of the tape leader pin, if any, such as elliptical or conical, representing tilt angle misalignment of the pin. Further, both ends of the pin are scanned for difference in displacement and for difference in amplitude, displacement representing tilt in the direction of scan, and amplitude representing that one end or the other is likely to have been pulled into the cartridge. Low amplitude of both represents absence of the pin.

Abstract: In part, and in addition to apparatus and methods presented, an expansion board to be connected/disconnected to/from its mother board easily is provided. A face of a CDC (Communication Daughter Card), which is an expansion board to be connected to the mother board of a computer system is covered by an insulating sheet. In the CDC, an edge of one end of this insulating sheet is extended so as to form a projection. A user can take this projection with fingers, thereby carrying and connecting/disconnecting the CDC to/from the mother board easily.

Abstract: A container selector for use in a Web services architecture can include an application container query tool operably configured to query individual application containers for a list of supported libraries and associated configuration information. A comparator can be programmed to compare the list with another list of requisite libraries and associated configuration information specified for use by a requested Web service. Finally, a Web service clone requestor can be operably configured to request an instantiation of the Web service within a particular application container. Specifically, the particular container can be a new container where the comparator cannot identify an existing container having libraries and associated configuration information which match the requisite libraries and associated configuration information.

Abstract: A method and a corresponding system for use in a resource management infrastructure conforming to the WMI architecture are proposed. The WMI architecture includes a framework, known as CIM Object Manager (or CIMOM), which exploits WMI providers of dynamic services for the managed objects; in the WMI architecture, the CIM providers must be implemented as Common Object Model (COM) objects and must comply with a specific WMI provider interface (named “IWbemServices”).

Abstract: A chip repair system designed for automated test equipment independent application on many unique very dense ASIC devices in a high turnover environment is disclosed. During test, the system will control on chip built-in self-test (BIST) engines collect and compress repair data, program fuses and finally decompress and reload the repair data for post fuse testing. In end use application this system decompresses and loads the repair data at power-up or at the request of the system.