Abstract: A data link includes a transmit side having a physical layer circuit including a serial pin interface and a data link circuit layer coupled by one or more parallel multi-bit data lanes to the physical layer circuit. The data link layer circuit transfers parallel data to the physical layer circuit responsive to a parallel clock signal. The data link layer circuit includes a pseudo-random bit sequence generator circuit configured to generate, based on the parallel clock signal, a pseudo-random bit sequence having a width of M bits, where M is greater than 1. The data link layer circuit further includes a hold circuit coupled to receive and hold the pseudo-random bit sequence for a selected number of cycles of the parallel clock signal determined by a hold signal and a timing circuit configured to assert the hold signal based on multiple cycles of the parallel clock signal.

Abstract: A computer-implemented method of generating an Artificial Intelligence (AI) driven prescriptive policy and executing a function includes obtaining interdependent operational information about the function. A model is trained with the interdependent operational information about the function to dynamically generate a plurality of candidate decision paths from a group of all feasible decision paths for a plurality of interrule logical conditions and one or more dynamic constraints of the operational information. A prescriptive policy is generated from the plurality of candidate decision paths to execute the function that satisfies to a threshold degree of confidence the interrule logical conditions and the one or more dynamic constraints of the operational information. The function is executed based on the generated prescriptive policy.

Abstract: Mechanisms are provided for automatic identification of a reconciliation computer tool for producing coherent reconciled data from base data generated by a computer model. A machine learning training operation is executed on one or more performance prediction computer model(s) (PPCMs) based on first input features of at least one hierarchical dataset, and second input features of a plurality of different reconciliation computer tools. The PPCM(s) generate a prediction of performance of a corresponding reconciliation computer tool based on the first and second input features. Features are extracted from a runtime hierarchical dataset and input into the trained PPCM(s) which generate predictions of performance of a plurality of reconciliation computer tools based on the extracted features of the runtime hierarchical dataset. The reconciliation computer tools are ranked relative to one another based on the predictions of performance.

Abstract: At least one processor determines bounding boxes in an image using a neural network. At least one processor extracts an initial bounding box for an object in the image. At least one processor selects a cluster center of the bounding boxes and circumscribes a cluster box around the cluster center. At least one processor rotates the initial bounding box and contents of the initial bounding box according to a rotation angle determined based on the cluster box. At least one processor detects the object in the rotated initial bounding box using a trained machine learning model.

Abstract: A semiconductor structure includes a plurality of gate-all-around field effect transistors. Each of the gate-all-around field effect transistors includes first and second source-drain regions; at least one channel region interconnecting the first and second source-drain regions; and a gate structure surrounding the at least one channel region. A direct backside contact is located below one of the first and second source-drain regions. The direct backside contact has an upper portion. A dielectric liner is wrapped around the upper portion of the direct backside contact.

Abstract: A semiconductor device is provided. The semiconductor device includes a stacked field effect transistor (FET) structure. The stacked FET structure includes a bottom FET device and a top FET device. The bottom FET device has a vertically stacked gate-all-around (GAA) nanosheet (NS) structure and a first channel orientation. The top FET device is isolated from the bottom device and has a horizontally stacked structure and a second channel orientation differing from the first channel orientation.

Abstract: A semiconductor device includes a frontside including first metal structures, transistors disposed between the frontside and a backside opposite the frontside, each transistor including a source/drain positioned within a stack of nanolayers, the stack of nanolayers forming a gate structure and a power circuit on the backside and connected to the transistors by backside contacts. A backside dielectric isolation has a horizontal portion along a backside of the gate structure and a vertical portion substantially perpendicular to the backside and self-aligned to selected source/drains to electrically isolate the power circuit from the transistors.

Abstract: Controlling data locality in a Kubernetes computing environment by establishing a Kubernetes computing environment including a controller and at least one executor pod for running an application, and receiving a request for a task to be run in the Kubernetes computing environment. The controller dispatches a sidecar to collect resource data from the at least one executor pod for an input to a directed acyclic graph (DAG) feature analyzer. The directed acyclic graph (DAG) feature analyzer identifies from the at least one executor pod a best dynamic resource that are available to execute. The at least one executor pod meeting the best dynamic resource that is available executes the task to be run in the Kubernetes computing.

Abstract: A system includes a processor that executes computer executable components stored in a memory. The computer executable components include an identification component that identifies a user associated with a complaint and queries a database for historical data pertaining to the user. The computer executable components further include an analysis component that analyzes the complaint. The computer executable components also include an issue component that determines an issue from the user complaint, based at least in part on the analysis. The computer executable components further include a mapping component that identifies, based on the determined issue, one or more similar complaints from the historical user data, and extracts an inference context from a knowledge graph. The computer executable components also include a resolution component that generates a solution to the determined issue.

Abstract: A method and system for making a prediction with a recurrent neural network (RNN) of a discrete-time linear time-invariant system can receive, as an input into a recurrent neural network cell, a memory flow, an external input, a state flow and a hidden output flow. The RNN can compute an updated state flow by a linear combination of the external input and the memory flow constrained by a first matrix and a second matrix, wherein the first matrix and the second matrix correspond to a Laguerre orthogonal basis. The RNN can further compute, from the updated state flow using a coordinate matrix, an updated memory flow. The RNN can then apply an activation function on the hidden output flow to produce an updated hidden output flow and an output flow from a weighted sum of the hidden output flow, the updated state flow and the updated memory flow.

Abstract: A method, system and computer program product for generating optimal samples in quantum optimization algorithms. A quantum error mitigation technique is used to generate samples of a resulting probability distribution from random quantum circuits. Examples of such quantum error mitigation techniques include probabilistic error cancellation (PEC) and zero noise extrapolation (ZNE). An objective (ƒ(x)) for every generated sample (|x) is then computed. A conditional value at risk (CVaR) at a particular level of the computed objective functions corresponding to an optimal sample in a quantum optimization algorithm, such as a variational quantum optimization algorithm, is then computed. In this manner, optimal samples in quantum optimization algorithms are generated using quantum error mitigation techniques, such as probabilistic error cancellation and zero noise extrapolation.

Abstract: Systems and techniques that facilitate quantum-enhanced features for classical machine learning are provided. In various embodiments, a system can comprise a receiver component that can access a classical dataset. In various aspects, the system can further comprise a feature component that can generate one or more machine learning input features based on a quantum transformation of the classical data set. In various instances, the system can further comprise an execution component that can execute a classical machine learning model on the one or more machine learning input features.

Abstract: Systems and techniques for concurrently performing a fill and byte merge operation in a data processing system are described. An example technique includes receiving a memory access request from a user interface. A determination is made that the memory access request has encountered a cache miss within a cache directory in the computing system. In response to the determination, a fetch request is transmitted to an upper level cache within the computing system for a cache line associated with the memory access request. Dirty portions of the cache line are concurrently written and merged, based on the memory access request, with fill data of the cache line obtained from the upper level cache into a line buffer of a line engine within the computing system.

Abstract: An example system includes a processor to receive a non-homomorphic encryption (HE)-friendly analytics model including a non-polynomial element. The processor is to train a substitution model in which the non-polynomial element of the non-homomorphic encryption (HE)-friendly analytics model is replaced with a sub-network including a polynomial replacement element.

Abstract: An interconnect structure that in one embodiment can include a first metal line level having a first metal line, a second metal line level having a second metal line, and a via line level present between the first and second metal line levels. The via line level includes a via interlevel dielectric surrounding a via stack. The via stack may include an interface metal portion that is in contact with the first metal line, a via intralevel dielectric on the interface metal portion, and a cap metal portion in contact with the second metal line and extending through the via intralevel dielectric into contact with the interface metal portion. In some embodiments, the length of the interface metal portion of the via is greater than a width of the interface metal portion of the via stack.

Abstract: One or more systems, devices, and/or methods of fabrication provided herein relate to isolated self-aligned super vias. According to one embodiment, a super via device can comprise a super via structure, a metallic line and a dielectric fill material located between the sidewalls of the super via structure and the metallic line.

Abstract: Provided is a method for fabricating an interconnect. The method comprises forming a topological semi-metal layer. The method further comprises patterning the topological semi-metal layer to form one or more interconnects. The method further comprises forming a dielectric layer between the one or more interconnects. The method further comprises forming a hermetic dielectric cap layer on top of the one or more interconnects and the dielectric layer.

Abstract: Double gate/gate-all-around and variable threshold voltage MOSFET devices and techniques for fabrication thereof in a single backside process are provided. In one aspect, a MOSFET device includes: a channel in between source/drain regions; at least one first gate disposed on a first side of the channel at a frontside of the MOSFET device; gate spacers offsetting the source/drain regions from the at least one first gate; and at least one second gate disposed on a second side of the channel directly opposite the at least one first gate at a backside of the MOSFET device. At least one gate contact can be present in direct contact with the at least one first gate and the at least one second gate. A method of forming a MOSFET device is also provided.

Abstract: Systems and techniques that facilitate amplitude-driven at-speed control of digital-to-analog converters are provided. In various embodiments, a system can comprise a digital-to-analog converter that is configured to generate an analog waveform based on a digital amplitude indicator sequence. In various aspects, the system can comprise a processor that is configured to reset an operating characteristic of the digital-to-analog converter in response to detection of a defined digital amplitude indicator subsequence in the digital amplitude indicator sequence. In various instances, the operating characteristic can be operation of a numerically controlled oscillator of the digital-to-analog converter.

Abstract: A semiconductor structure includes a semiconductor structure. The semiconductor structure may include a top transistor, a bottom transistor stacked below the top transistor, a back-end-of-line (BEOL) memory device electrically coupled to and above the top transistor, and a backside memory device electrically coupled to and below the bottom transistor.

Abstract: Embodiments of present invention provide a resistor structure. The resistor structure includes a first layer of electrically insulating material; and a second layer of resistive material directly adjacent to the first layer, wherein thermal conductivity of the first layer is equal to or larger than 100 W/m/K. In one embodiment, the first layer of electrically insulating material has a band gap equal to or larger than 4 eV and is selected from a group consisting of aluminum-nitride (AlN), boron-nitride (BN), and diamond (C).

Abstract: Techniques facilitating automatic non-linearity correction for analog hardware are provided. A system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise an adjustment component that determines a non-linear correction term for an output of an array of analog memories based on a result of a matrix vector multiplication performed on the array of analog memories. The computer executable components can also comprise a rectification component that applies the non-linear correction term to additional outputs of the array of analog memories.

Abstract: Methods and systems for sentence acceptability judgment. A word frequency distribution for a predetermined textual data set is obtained. A replacement rate is determined based on an obtained word frequency distribution for a predetermined textual data set and every occurrence of a word having a frequency lower than the replacement rate is replaced in text of a training data set with a corresponding tag to generate revised text of the training data set (the training data set comprising at least a portion of the predetermined textual data set). A plurality of language models are trained with the revised text and a best performing trained language model of the plurality of trained language models is selected. An acceptability of each sentence of a plurality of candidate sentences is rated using the selected trained language model and a best sentence of the plurality of candidate sentences is selected based on the ratings.

Abstract: A computer implemented method manages a topology for a network computing system. A number of processor units determines tasks for a workload to be performed by computing devices in the network computing system. The number of processor units creates the topology for performing the tasks in the workload. The topology comprises nodes representing the tasks assigned to the computing devices. The nodes are connected to each other based on an execution order for the tasks, and the topology has alternative paths for performing the tasks for the workload. The number of processor units determines energy consumption for the alternative paths in the topology. The number of processor units selects a particular path from the alternative paths for performing the tasks for the workload based on the energy consumption for the alternative paths.

Abstract: A method and system for generating a three-dimensional (3D) virtual scene are disclosed. The method includes: identifying a two-dimensional (2D) object in a 2D picture and the position of the 2D object in the 2D picture; obtaining the three-dimensional model of the 3D object corresponding to the 2D object; calculating the corresponding position of the 3D object corresponding to the 2D object in the horizontal plane of the 3D scene according to the position of the 2D object in the picture; and simulating the falling of the model of the 3D object onto the 3D scene from a predetermined height above the 3D scene, wherein the position of the landing point the model of the 3D object in the horizontal plane is the corresponding position of the 3D object in the horizontal plane of the 3D scene.

Abstract: Embodiments are disclosed for a method. The method includes determining a correlation list of missing value predictors. The method also includes generating a cluster model having multiple clusters. The cluster model is based on a target value and predictor values. The method further includes determining an imputed value for a missing value of a row of original training data based on a linear regression model for multiple non-missing value predictor values for the clusters.

Abstract: An approach for generating actionable explanations of change request classifications may be presented. A model may generate features associated with a change request may be disclosed. The model may be trained with historical change requests that have been labeled risky or not risky. The change request may be classified as risky or not risky. Candidate historical change requests with the same classification as the change request and occupying similar feature space as the change request may be identified from a historical change request repository. One or more features which had the most significant impact on the classification may be identified. A candidate historical change request with at least one significant feature impacting classification may be identified.

Abstract: A computer-implemented method, a computer program product, and a computer system for recommending model contributions based on federated learning lineage. The computer system retrieves information of model checkpoints. The computer system trains data analytic models for monitoring activities of training rounds in a federated learning system, based on the information of the model checkpoints. The computer system sends to a user summary statistics of the model checkpoints. The computer system receives from the user natural language instructions of modifying a federated learning plan for future training rounds in the federated learning system. The computer system translates the natural language instructions into updates for the federated learning system. The computer system forwards the updates to the federated learning system.

Abstract: Embodiments herein described techniques for calling an OS service to resolve a storage access exception in OS memory space. To do so, the hardware can use an exception indicator to indicate when an access exception has been detected and then the application program can use the exception indicator to instruct an OS service to resolve the exception on behalf of the application program. In one embodiment, the exception occurs when performing an interruptible instruction issued by the application program where the instruction is performed at different times. When executing the counter update step of the interruptible instruction, the hardware can determine whether an exception is detected, and if so, update an exception indicator. The application program calls the OS service which resolves the access exception in OS memory space on application program's behalf.

Abstract: According to one embodiment, a method, computer system, and computer program product for adaptive user interface amelioration during a screen sharing session is provided. The embodiment may include receiving shared content during a screen sharing session. The embodiment may also include identifying one or more device characteristics for a user device associated with a user and one or more user profile characteristics for the user. The embodiment may further include extracting topical elements within the received shared content. The embodiment may also include identifying a location of one or more objects and/or one or more text elements in the shared content. The embodiment may further include modifying a viewing area of the shared content on a display screen of the user device.

Abstract: A testing device that includes a resistance measuring device electrically communicating across connection points which electrically includes an electrical connector. The testing device also includes a threshold monitor analyzing the resistance being measurable using the resistance meter to determine when the resistance exceeds a threshold for contact resistance. Finally, the testing device also includes a warning indicator. The warning indicator triggered in response to the resistance exceeding the threshold indicates to replace the connector.

Abstract: Mechanisms are provided for generating a holistic view of an event processing pipeline of an event driven architecture. Curation of runtime information from components of an event processing pipeline is performed, where the runtime information comprises real-time runtime metrics, aggregated logs, event tracing/recording data structures, and configuration information. The curated runtime information is correlated to generate correlated runtime data. Predictive models and predictive analytics process the correlated runtime data to predict anomalies in the components of the event processing pipeline. A fault circuit interrupt machine (FCIM) processes the predicted anomalies based on user resiliency configurations to determine recommended event resiliency remediation actions for addressing the predicted anomalies.

Abstract: Described are techniques for a re-analysis of assignments of terms to assets. The techniques include detecting a change in a term ontology comprising a plurality of terms, and determining at least one selected from a group consisting of: a domain feature change vector (DFCV) for a domain of the term ontology affected by the change, and a term feature change vector (TFCV) for the term affected by the change. The techniques further include identifying assets for the re-analysis of the assignments of terms, wherein each of the identified assets is associated with an impact score value based on the DFCV and/or the TFCV, and performing the re-analysis of the assignments of terms for the identified assets ordered by the impact score value.

Abstract: Exploratory network analysis aided by an artificial intelligence recommender includes determining one or more current activities in response to detecting one or more processor-executable instructions input to a computer system by a user. A best next activity is predicted in response to matching the one or more current activities with an electronically stored pattern of activities. The predicting is performed using a machine learning model trained with knowledge components generated from patterns of past activities. A recommendation based on the best next activity is output, the recommendation recommending to the user one or more additional processor-executable instructions to input to the computer system.

Abstract: A system, method, and computer program product for implementing deep learning software model modification is provided. The method includes monitoring operational performance of a software model. An expected confidence level associated with the operational performance is first determined and it is determined that an inference associated with the expected confidence level is below a selected range of inferences associated with assigning new feature data as candidate video data. A candidate sequence comprising video data associated with the candidate video data is received and a similarity between frames of the candidate sequence is determined. A frame comprising a highest similarity with respect to segments of candidate video data is selected and it is detected that the frame is not associated with additional frames stored within a full cache structure. The software model is retrained such that the operational performance is modified.

Abstract: A system and method can be provided for constructing and training a decision tree for machine learning. A training set can be received. The decision tree can be initialized by constructing a root node and a root solver can be trained with the training set. A processor can grow the decision tree by iteratively splitting nodes of the decision tree, where at a node of the decision tree, dimension reduction is performed on features of data of the training set received at the node, and the data having reduced dimension is split based on a routing function, for routing to another node of the decision tree. The dimension reduction and the split can be performed together at the node based on solving a nonlinear optimization problem.

Abstract: Computer implemented methods, systems, and computer program products include program code executing on a processor(s) (in the confidential computing environment), obtaining, from an untrusted computing resource, via a secure channel between the confidential computing environment and the untrusted computing resource, a debugging command in a command request packet. The processor(s) analyzes the packet to determine a security level for the debugging command and a security level for the confidential computing environment, wherein the analyzing comprises comparing a quantitative value of the security level for the debugging command to a quantitative value of the security level for the confidential computing environment. The processor(s) generates a command reply packet, wherein contents of the command reply packet and based on the comparing. The processor(s) transmits the command reply packet to the untrusted computing resource via the secure channel.

Abstract: A method, system, and computer program product that is configured to: receive a meeting agenda, a meeting time, a speaker, and an audience of a meeting; analyze the meeting agenda and the meeting time for an outcome of the meeting; categorize the meeting agenda and the meeting time into a tier level architecture using natural language processing (NLP); create a knowledge corpus using the categorized tier level architecture and the outcome of the meeting; dynamically adjust the categorized tier level architecture based on a conversation between the speaker and the audience during the meeting; train a tier level model using the created knowledge corpus; and dynamically adjust the categorized tier level architecture based on the trained tier level model.

Abstract: A method, computer system, and a computer program product are provided. A visual inspection machine learning model is trained using a generative adversarial network. Within the generative adversarial network a vector bypass is implemented. By transmitting a vector embedding representation of an unlabeled image through the vector bypass, the vector embedding representation is transmitted around the visual inspection machine learning model and to a generator to assist with image reconstruction.

Abstract: A quantum noise mitigation system can comprise a memory that stores, and a processor that executes, computer executable components comprising a pulse calibration component that, for controlling execution of a quantum gate of a quantum circuit, calibrates an echo extender tone parameter for a set of echo extender tones of an echo pulse sequence, wherein the pulse calibration component inserts the set of echo extender tones into the echo pulse sequence of an initial pulse sequence resulting in generation of a modified pulse sequence for use in controlling the execution of the quantum gate, and a parameterizing component that parameterizes the set of echo extender tones using a scalable stretch factor for stretching respective durations of the set of echo extender tones.

Abstract: An embodiment for dynamically modifying print codes to accommodate printing errors. The embodiment may track print data associated with a printing operation against a set of desired specifications. The embodiment may identify a defect in the printing operation based on the tracked print data. The embodiment may, in response to identifying the defect associated with the printing operation, pause the printing operation. The embodiment may generate remediating g-code alterations based on the identified defect and the set of desired specifications. The embodiment may generate a first digital twin corresponding to the set of desired specifications, and a second digital twin corresponding to the generated remediating g-code alterations. The embodiment may rebase the paused printing operation based on the generated remediating g-code alterations and the first and second digital twins. The embodiment may leverage the generated remediating g-code alterations to resume the rebased paused printing operation.

Abstract: One or more systems, devices, computer program products and/or computer-implemented methods of use provided herein relate to n-best based label smoothing techniques for improving generalization of DNN acoustic models. A computer-implemented system can comprise a memory that can store computer executable components. The computer-implemented system can further comprise a processor that can execute the computer executable components stored in the memory, wherein the computer executable components can comprise a generation component that can generate one or more n-best hypotheses of a ground truth label sequence, using one or more acoustic models, wherein the one or more n-best hypotheses of the ground truth label sequence can represent one or more competing labels that can be used to smooth out the ground truth label sequence.

Abstract: Embodiments herein describe techniques for providing interrupts from a shared network adapter to a host operating system or control program. A register can store an interrupt state of the host that indicates whether an interrupt is required. For example, the host may still be busy processed previous received data (e.g., a packet received from a network), which means no interrupt is required. When the host has processed each of the requests from the shared network adapter, the interrupt state in the register can be changed that if any additional data is received, an interrupt is required. Moreover, the register can include a bitmask to indicate which of a plurality of receive data queues has data ready for the host to process.

Abstract: One or more systems, devices, and/or methods of use provided herein relate to a semiconductor device with separate power supplies for front side and backside stacked power distribution. A semiconductor device can include one or more circuits, a first power supply, a second power supply, and a third power supply. The first power supply can be disposed on a first side of the one or more circuits. The second power supply can be disposed on the first side of the one or more circuits. Further, the third power supply can be disposed on a second side of the one or more circuits. Additionally, the first side of the one or more circuits can be opposite to the second side of the one or more circuits.

Abstract: A semiconductor device includes a first gate stack disposed over an active region and a second gate stack disposed over a shallow trench isolation (STI) region such that the first gate stack is taller than the second gate stack. The second gate stack includes a plurality of gates formed over a non-active region. The nanosheet stacks in the active region include first inner spacers and second inner spacers. The first inner spacers are vertically aligned with the second inner spacers. Further, the first inner spacers directly contact lower sidewalls of a source/drain epitaxial region to isolate the second gate stack from the STI region.

Abstract: Integrated circuits and related logic circuits and structures employing VTFET logic devices. In particular, during middle-of-line (MOL) processing, method steps are employed for forming two-level MOL contact connector structures below first (M1) metallization level wiring formed during subsequent BEOL processing. Using damascene and subtractive metal etch techniques, respective MOL contact connector structures at two levels are formed with a second level above a first level contact. These contact connector structures at two levels below M1 metallization level can provide cross-connections to VTFET devices of logic circuits that enable increased scaling of the logic circuit designs, e.g., especially for multiplexor circuit layouts due to wiring access.

Abstract: An example operation may include one or more of receiving a digital token that is created by software application of a blockchain network and which comprises a predefined data structure, determining, via a network node, an assessed value of the digital token based on an assessment of a plurality of attributes of the digital token, embedding, via the network node, the assessed value and an identifier of the blockchain network of the network node within a data container that is included in the predefined data structure of the digital token, and storing the digital token with the embedded assessed value at a blockchain memory address.

Abstract: Techniques for generating a clarification to distinguish among retrieved content in interactive systems are provided. In one aspect, a method for generating a clarification prompt in an interactive system includes: obtaining a training dataset for generating the clarification prompt from existing question-answering datasets by modifying original queries in the existing question-answering datasets to obtain training examples of under-specified queries; and training a machine learning model using the training dataset how to select latent differentiating factors in content candidates obtained from an under-specified query from a user and, based on the latent differentiating factors, generate the clarification prompt to clarify an intent of the user.

Abstract: A computer-implemented method, a computer program product, and a computer system for global vertical auto-scaling for processing units. A computer periodically learns one or more functions, based on resource consumption metrics samples of processing units. A computer uses the one or more functions to obtain a predicted maximal resource consumption value per resource and a predicted minimal resource consumption value per resource for a processing unit. A computer determines a global priority of the processing unit. A computer calculate a prioritized predicted consumption value per resource for the processing unit, based on the global priority, the predicted maximal resource consumption value, and the predicted minimal resource consumption value. A computer uses the prioritized predicted consumption value for vertical auto-scaling of the processing unit by a processing unit management system.

Abstract: An embodiment includes responsive to receiving from an issuer a credential by a digital wallet of a holder on a holder device, determining a dependency between the credential and a verifier. The embodiment includes provisioning a dataset based on the credential. The embodiment includes deciding to send the dataset to the verifier wherein at least one attribute of the credential is sent to the verifier. The embodiment also includes determining a dependency between the credential and the verifier wherein the verifier subscribes to the credential.