Abstract: A technique for managing hard failures in a memory system employing a locking is disclosed. An error count is maintained for units of memory within the memory system. When the error count indicates a hard failure, the unit of memory is locked out from further use. An arbitrary set of error counters are assigned to record errors resulting from access to the units of memory. Embodiments of the present invention advantageously enable a system to continue reliable operation even after one or more internal hard memory failures. Other embodiments advantageously enable manufacturers to salvage partially failed devices and deploy the devices as having a lower-performance specification rather than discarding the devices, as would otherwise be indicated by conventional practice.

Abstract: Program disturb error logging and correction for a flash memory including a computer implemented method for storing data. The method includes receiving a write request that includes data and a write address of a target page in a memory. A previously programmed page at a specified offset from the target page is read from the memory. Contents of the previously programmed page are compared to an expected value of the previously programmed page. Error data is stored in an error log in response to contents of the previously programmed page being different than the expected value of the previously programmed page, the error data describing an error in the previously programmed page and the error data used by a next read operation to the previously programmed page to correct the error in the previously programmed page. The received data is written to the target page in the memory.

Abstract: An identity of a user performing an operation with respect to an application is propagated, from a point at which the user authenticates, to one or more other applications in a multi-product environment. The application may be a management console associated with an information cluster. In an embodiment, an administrator logs on to a management console (using an identity) and invokes a management operation. The management console then performs a programmatic remote access login (e.g., using SSH/RXA) to one or more nodes using a system account, invokes an application, and passes in the identity. As the application performs one or more management operations, audit events are logged, and these events each contain the identity that has been passed in by the management console during the SSH/RXA login.

Abstract: A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.

Abstract: A vertical probe tip rotational scrub and method is described. The vertical probe includes a wafer prober chuck; a wafer positioned on the wafer prober chuck; and at least one probe having a probe tip, the at least one probe tip rotatably mounted such that the probe tip provides a rotational scrub on a surface of a wafer surface. A method for wafer probing is also described, the method includes: determining a vertical location of a wafer surface relative to at least one probe having a probe tip; retracting the probe tip; and imparting an upward motion on the at least one probe in response to the retracting of the probe tip, wherein the upward motion results in a rotational scrub of the wafer surface.

Abstract: A method for providing assisted business analysis to users is disclosed herein. In one embodiment, such a method includes providing a list of one or more predefined managed reports to a user. Each predefined managed report has specific metadata associated therewith. The method further provides functionality to enable the user to select a specific managed report from the list. Once a managed report is selected from the list, the method enables the user to generate a new ad hoc report from the selected managed report. Generating this new ad hoc report includes automatically extracting all or part of the metadata from the selected managed report to build the new ad hoc report. A corresponding computer program product and apparatus are also disclosed and claimed herein.

Abstract: Application context changes associated with instantiated applications are monitored at a context tracking device. In response to each application context change, relationship context dependency properties between the instantiated applications and application resources associated with the instantiated applications are evaluated. At least one relationship context dependency property that is used by at least one of the instantiated applications is determined to have changed as a result of an application context change. The at least one relationship context dependency property is updated during runtime based upon the application context change.

Abstract: A computer specifies a substrate comprising a first side opposite a second side. The computer specifies a first plurality of flexible pins protruding from the first side of the substrate, the first plurality of pins for installing in a first plurality of pad connectors of a pinless socket. The computer specifies a second plurality of flexible pins protruding from the second side of the substrate, the second plurality of pins for installing in a second plurality of pad connectors of a pinless integrated circuit component, wherein the first selection of flexible pins are for electrical connection to the second plurality of flexible pins through the substrate to provide electrical contact points between the pinless socket and the pinless integrated circuit component.

Abstract: An information processing system which includes: a storage controlling module in any of computer apparatuses that runs a clone origin virtual machine, where the storage controlling module controls: booting up the clone origin virtual machine when the clone origin virtual machine is detached from a virtual network interface; acquiring running state information indicating a running state of the clone origin virtual machine; and storing an image including the running state information and virtual disk information in a storage apparatus; and a boot controlling module in any of computer apparatuses that creates a clone virtual machine, where the boot controlling module controls: resuming at least one of the clone virtual machines with the image when each of the clone virtual machines is detached from the virtual network interface; and attaching the virtual network interface to the at least one clone virtual machine.

Abstract: A method for decoding encoded data comprising integrated data and header protection is disclosed herein. In one embodiment, such a method includes receiving an extended data array. The extended data array includes a data array organized into rows and columns, headers appended to the rows of the data array, column ECC parity protecting the columns of the data array, and row ECC parity protecting the rows and headers combined. The method then decodes the extended data array. Among other operations, this decoding step includes checking the header associated with each row to determine whether the header is legal. If the header is legal, the method determines the contribution of the header to the corresponding row ECC parity. The method then reverses the contribution of the header to the corresponding row ECC parity. A corresponding apparatus (i.e., a tape drive configured to implement the above-described method) is also disclosed herein.

Abstract: A substrate has a top side and a bottom side. A solar cell is secured to the top side of the substrate and has an anode and a cathode. A heat transfer element is secured to the bottom side of the substrate. An anode pad is formed on the top side of the substrate and is coupled to the anode of the solar cell; similarly, a cathode pad is formed on the top side of the substrate and is coupled to the cathode of the solar cell. The substrate coefficient of thermal expansion and the solar cell coefficient of thermal expansion match within plus or minus ten parts per million per degree C.

Abstract: A high-k gate dielectric layer and a metal gate layer are formed and patterned to expose semiconductor surfaces in a bipolar junction transistor region, while covering a CMOS region. A disposable material portion is formed on a portion of the exposed semiconductor surfaces in the bipolar junction transistor area. A semiconductor layer and a dielectric layer are deposited and patterned to form gate stacks including a semiconductor portion and a dielectric gate cap in the CMOS region and a cavity containing mesa over the disposable material portion in the bipolar junction transistor region. The disposable material portion is selectively removed and a base layer including an epitaxial portion and a polycrystalline portion fills the cavity formed by removal of the disposable material portion. The emitter formed by selective epitaxy fills the cavity in the mesa.

Abstract: A FET inverter is provided that includes a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant and the source and drain regions of one or more other of the device layers are doped with a p-type dopant; a gate common to each of the device layers surrounding the nanowire channels; a first contact to the source regions of the one or more device layers doped with an n-type dopant; a second contact to the source regions of the one or more device layers doped with a p-type dopant; and a third contact common to the drain regions of each of the device layers. Techniques for fabricating a FET inverter are also provided.

Abstract: Algorithm selection for data communications in a parallel active messaging interface (‘PAMI’) of a parallel computer, the PAMI composed of data communications endpoints, each endpoint including specifications of a client, a context, and a task, endpoints coupled for data communications through the PAMI, including associating in the PAMI data communications algorithms and bit masks; receiving in an origin endpoint of the PAMI a collective instruction, the instruction specifying transmission of a data communications message from the origin endpoint to a target endpoint; constructing a bit mask for the received collective instruction; selecting, from among the associated algorithms and bit masks, a data communications algorithm in dependence upon the constructed bit mask; and executing the collective instruction, transmitting, according to the selected data communications algorithm from the origin endpoint to the target endpoint, the data communications message.

Abstract: An electronically scannable multiplexing device is capable of addressing multiple bits within a volatile or non-volatile memory cell. The multiplexing device generates an electronically scannable conducting channel with two oppositely formed depletion regions. The depletion width of each depletion region is controlled by a voltage applied to a respective control gate at each end of the multiplexing device. The present multi-bit addressing technique allows, for example, 10 to 100 bits of data to be accessed or addressed at a single node. The present invention can also be used to build a programmable nanoscale logic array or for randomly accessing a nanoscale sensor array.

Abstract: A selection of a service domain policy definition is received in a service repository. A service policy document is created from the service domain policy definition. At least one user change to the service policy document is received in accordance with the selected service domain policy definition. The service policy document is saved in the service repository.

Abstract: Disclosed embodiments include a method for receiving, at a configuration information server, an encrypted password associated with a configuration item, where the encrypted password is encrypted using an encryption key. The method further includes encrypting a decrypted password to generate a reencrypted password, where the decrypted password is derived from the encrypted password. The method further includes transmitting the reenrypted password to the configuration item and removing the decrypted password from the configuration information collection server.

Abstract: Variation of a parameter of interest is reduced over a field of interest in, for example, an object design, such as a circuit design. The field of interest is divided into tiles. A parameter value is found for each tile and for a group of tiles around each tile. Using these values, variation of the parameter is determined. An adjusted value of the parameter for each tile is determined taking limits into account, iterating until variation is below a threshold value. Parameter uniformity is improved in some applications by over 30% with runtime reduced by an order of magnitude.

Abstract: Various embodiments for reducing communication between cluster nodes and optimizing failover processing in a distributed shared memory (DSM)-based application by at least one processor device are provided. In one embodiment, for a data structure operable on a DSM, a read-mostly portion is maintained in a single copy sharable between the cluster nodes while an updatable portion is maintained in multiple copies, each of the multiple copies dedicated to a single cluster node.

Abstract: A method, system, and computer program product for reversibly instrumenting a computer software application is described. The method may comprise creating a map indicating a plurality of locations of application instruction sections within instructions of a computer software application. The method may further comprise inserting a plurality of instrumentation sections into the computer software application instructions. The method may also comprise updating the map to indicate the locations of the instrumentation sections within the computer software application instructions, where the indications in the map of the locations of the instrumentation sections are distinguishable from the indications in the map of the locations of the application instruction sections.

Abstract: MEMS switches and methods of fabricating MEMS switches. The switch has a vertically oriented deflection electrode having a conductive layer supported by a supporting layer, at least one drive electrode, and a stationary electrode. An actuation voltage applied to the drive electrode causes the deflection electrode to be deflect laterally and contact the stationary electrode, which closes the switch. The deflection electrode is restored to a vertical position when the actuation voltage is removed, thereby opening the switch. The method of fabricating the MEMS switch includes depositing a conductive layer on mandrels to define vertical electrodes and then releasing the deflection electrode by removing the mandrel and layer end sections.

Abstract: A method dynamically determines the contents of a Boot Logical Volume from within a System Management Service menu. Responsive to receiving the scan request, a system dynamically scans a root volume group to identify special files associated with the various base operating systems stored on the boot logical volumes of the root volume group. The system then maps the files to a specific operating systems version, and presents a list of the available operating systems on the various boot logical volumes to a user.

Abstract: A method and system for cooling an electrical heat source is disclosed. A heat exchanger has two principal sub-assemblies. A closed-loop fluid flow is provided through a second sub-assembly, disposed next to a heat source. An open-loop fluid flow is provided though a first sub-assembly in communication with a second sub-assembly. Each of the first and second sub-assemblies has a rotational element. The fluid flow entering the first sub-assembly rotates the first rotational element, and magnetic communication between the rotational elements causes movement of the second rotational element, thereby achieving fluid movement within the second sub-assembly. Operationally, the closed-loop sub-assembly removes heat from the heat source and transfers it to the open-loop sub-assembly for subsequent heat transfer in a downstream fluid flow.

Abstract: A computer implemented method invokes a business application in response to receipt of a request Simple Object Access Protocol (SOAP) message. The request SOAP message requests an operation that is defined in a Web Services Description Language (WSDL) service. To implement the operations defined in the WSDL service, the WSDL service is provided as input to a tool that generates a business application which corresponds to the supplied WSDL service. The SOAP BODY from the request SOAP message is converted into an unformatted data structure for inputting to the business application, while information from the SOAP HEADER is retained in order to generate a reply SOAP message that contains execution results.

Abstract: A method, computer program product and system for improving the localization of a wireless communication device within an area covered by a transceiver infrastructure includes triggering the wireless communication device to emit a positioning signal. A positioning signal is received from the wireless communication device by a further wireless communication device at a known position within the area covered by the transceiver infrastructure. The transceiver infrastructure includes at least three transceivers. A forwarding positioning signal is transmitted from the further wireless communication device to at least one of the transceivers. The wireless communication device is located based on the forwarding positioning signal.

Abstract: A server can efficiently distribute images for a web page as groups of images. The server receives a request from a client for a group of images associated with a web page. The request encodes an image group identifier and a retrieving function. The server executes the retrieving function with the image group identifier to obtain the group of images. In response to the request, the group of images are transmitted over a number of data communication connections between the client and the server that are less than a number of images in the group of images.

Abstract: Systems and methods to manage memory are provided. A particular method may include selecting one of a plurality of compression modes to perform memory compression operations at a server computer. The plurality of compression modes may include a first memory compression mode configured to perform a first memory compression operation using a compression engine, and a second compression mode configured to perform a second memory compression operation using the compression engine. At least one of the first compression operation and the second compression operation may be performed according to the selected compression mode.

Abstract: A method for clearing a fault condition at a target device is disclosed herein. In selected embodiments, such a method includes detecting a fault condition at a target device and receiving N instructions before the fault condition is cleared, where the N instructions are unexecutable due to the fault condition. N fault condition indicators are transmitted in response to the N instructions. Clearing of the fault condition is detected when the fault condition no longer exists. Acknowledgments corresponding to the fault condition indicators are received, where each acknowledgment indicates that one of the fault condition indicators has been received. A fault clear indicator is transmitted only after both all N fault condition indicators have been received and clearing of the fault condition has been detected. A corresponding system and computer program product are also disclosed herein.

Abstract: A method of performing a static timing analysis based on slack values to verify and optimize a logic design includes: selecting one or more circuits within the logic design having at least two inputs taking on a known value; identifying a critical input that controls an output arrival time of the selected circuit from among the inputs that take on the known value; determining one or more non-critical input of the circuit a required arrival time based on the difference between the arrival times of the critical and non-critical inputs; and computing the slack at a critical input based on the difference between the AT of the critical and non-critical inputs. The design optimization based on the slack defined by arrival time differences preferably uses a reverse merge margin design metric. The metric determines the exact required amount of improvement in the input arrival time of non-critical signals of a clock shaping circuit.

Abstract: A method, a computer program product, and a computer system for managing requests to send messages are presented. Header information associated with a set of incoming messages on a server data processing system is retrieved in response to receiving a request to send a drafted message from a client data processing system to the server data processing system. The header information is searched to determine whether an incoming message in the set of incoming messages is related to the drafted message. An indication that the incoming message is related to the drafted message is presented at the client data processing system in response to determining that the incoming message is related to the drafted message.

Abstract: A semiconductor device is provided that includes a semiconductor substrate having a well region located within an upper region thereof. A semiconductor material stack is located on the well region. The semiconductor material stack includes, from bottom to top, a semiconductor-containing buffer layer and a non-doped semiconductor-containing channel layer; the semiconductor-containing buffer layer of the semiconductor material stack is located directly on an upper surface of the well region. The structure also includes a gate material stack located directly on an upper surface of the non-doped semiconductor-containing channel layer. The gate material stack employed in the present disclosure includes, from bottom to top, a high k gate dielectric layer, a work function metal layer and a polysilicon layer.

Abstract: Embodiments of the present invention provide a method, system and computer program product for concurrent workload simulation for application performance testing. In an embodiment of the invention, a method for concurrent workload simulation for application performance testing is provided. The method includes loading a list of recorded workloads for different tasks of a computing application under test in a workload simulator executing in memory by at least one processor of a host computer. The method also includes grouping the recorded workloads by common task in a corresponding block. Finally, the method includes generating loads for simulating performance of the computing application under test from the grouped workloads so as to require serial execution of workloads in a common block in order of appearance in the common block, but to allow concurrent execution of workloads in different blocks.

Abstract: A lateral heterojunction bipolar transistor (HBT) is formed on a semiconductor-on-insulator substrate. The HBT includes a base including a doped silicon-germanium alloy base region, an emitter including doped silicon and laterally contacting the base, and a collector including doped silicon and laterally contacting the base. Because the collector current is channeled through the doped silicon-germanium base region, the HBT can accommodate a greater current density than a comparable bipolar transistor employing a silicon channel. The base may also include an upper silicon base region and/or a lower silicon base region. In this case, the collector current is concentrated in the doped silicon-germanium base region, thereby minimizing noise introduced to carrier scattering at the periphery of the base. Further, parasitic capacitance is minimized because the emitter-base junction area is the same as the collector-base junction area.

Abstract: A compact, low-power, asynchronous, resistor-based memory read circuit includes a memory cell having a plurality of consecutive memory states, each of said states corresponding to a respective output voltage. A sense amplifier reads the state of the memory cell. The sense amplifier includes a voltage divider configured to receive the output voltage of the memory cell and to output a settled voltage an amplifier having a voltage threshold between the settled voltages associated with two of said consecutive memory states, configured to discriminate between said two consecutive memory states.

Abstract: Algorithm selection for data communications in a parallel active messaging interface (‘PAMI’) of a parallel computer, the PAMI composed of data communications endpoints, each endpoint including specifications of a client, a context, and a task, endpoints coupled for data communications through the PAMI, including associating in the PAMI data communications algorithms and ranges of message sizes so that each algorithm is associated with a separate range of message sizes; receiving in an origin endpoint of the PAMI a data communications instruction, the instruction specifying transmission of a data communications message from the origin endpoint to a target endpoint, the data communications message characterized by a message size; selecting, from among the associated algorithms and ranges, a data communications algorithm in dependence upon the message size; and transmitting, according to the selected data communications algorithm from the origin endpoint to the target endpoint, the data communications message.

Abstract: Methods of forming through wafer vias (TWVs) and standard contacts in two separate processes to prevent copper first metal layer puddling and shorts are presented. In one embodiment, a method may include forming a TWV into a substrate and a first dielectric layer over the substrate; forming a second dielectric layer over the substrate and the TWV; forming, through the second dielectric layer, at least one contact to the TWV and at least one contact to other structures over the substrate; and forming a first metal wiring layer over the second dielectric layer, the first metal wiring layer contacting at least one of the contacts.

Abstract: Various embodiments for rewriting data in a deduplication storage environment by a processor device are provided. A dynamic layer above a sequential deduplication file system (denoted as DFS) implements the rewrite functionality. A user file is composed of one or more DFS files. As incoming data is written into a user file, the data is written by the dynamic layer sequentially into DFS files, created one by one. For each user file this dynamic layer creates and maintains a dynamic metadata file, in a regular, non deduplicated file system. This metadata file contains entries pointing to sections of DFS files.

Abstract: A data processing system and method are disclosed. The system comprises an instruction-fetch stage where an instruction is fetched and a specific instruction is input into decode stage; a decode stage where said specific instruction indicates that contents of a register in a register file are used as an index, and then, the register file pointed to by said index is accessed based on said index; an execution stage where an access result of said decode stage is received, and computations are implemented according to the access result of the decode stage.

Abstract: Various embodiments are provided for facilitating construction of a synthetic backup in a deduplication storage system. In one embodiment, a deduplication storage system enables new input data to be deduplicated with data of synthetic backups already constructed, and for this purpose efficiently calculates deduplication digests for synthetic backups being constructed, based on already existing digests of data referenced by the synthetic backups. For each input data segment of the plurality of input data segments of a synthetic backup being constructed, a plurality of deduplication digests of stored data segments, referenced by the input data segment, is retrieved from an index. Each input data segment is partitioned into each of a plurality of fixed-sized data sub-segments.

Abstract: A system and method to reduce roundoff error of Fast Fourier transform (FFT) operation. Data which comes out as an irrational number (a square root) out of twiddle factors on a complex plane, included in a butterfly operation (8p) is preserved intentionally without being calculated in one stage of multiple stages of a multi-stage pipelined FFT, and when it occurs again in a later stage, an operation to multiply the two twiddle factors with each other is performed. This enables to eliminate roundoff errors during the butterfly operation 8p of radix-8. Other applications are also possible such as by overlaying a further stage by a butterfly operation of radix-2 or radix-4.

Abstract: A semiconductor structure is provided that includes a material stack including an epitaxially grown semiconductor layer on a base semiconductor layer, a dielectric layer on the epitaxially grown semiconductor layer, and an upper semiconductor layer present on the dielectric layer. A capacitor is present extending from the upper semiconductor layer through the dielectric layer into contact with the epitaxially grown semiconductor layer. The capacitor includes a node dielectric present on the sidewalls of the trench and an upper electrode filling at least a portion of the trench. A substrate contact is present in a contact trench extending from the upper semiconductor layer through the dielectric layer and the epitaxially semiconductor layer to a doped region of the base semiconductor layer. A substrate contact is also provided that contacts the base semiconductor layer through the sidewall of a trench. Methods for forming the above-described structures are also provided.

Abstract: Provided is a document creation assisting method, a document creation assisting system, and a document creation assisting program suitable to ensure consistent use of terms in document creation. Client processing is monitored to enable extracting one or more terms from a writing field of a document created by a user, and a terminology file is stored, where this terminology file includes a list of one or more standard terms that are the one or more terms thus extracted. Editing input assistance is provided, comprising extracting a term from a different writing field of a document being created by a user, locating from the terminology file a standard term that completely or partially matches the extracted term, and teaching the user the presence of the standard term located from the terminology file.

Abstract: Incident data for an insurance claim associated with an incident can be received by an incident application executing within a computing device. The incident can be an insurable event associated with an insurance policy of an insurance carrier. The incident data can be simultaneously conveyed to an independent third party entity as a serialized data format and as an insurance claim to the insurance carrier. The third party entity can automatically verify the incident data and generate a verification report. The verification report can be associated with the incident claim. The verification report can be communicated to the insurance carrier which can be utilized to determine the validity of the insurance claim.

Abstract: A mechanism is provided for resolving uplift or coupling timing problems and slew violations without sacrificing late mode timing in integrated circuit (IC) designs. Responsive to a request being received to generate a new IC design, for each net in a plurality of nets in the new IC design, a determination is made as to whether the net is rentable through a cell in a plurality of cells using a cost function associated with the cell such that a coupling capacitance associated with the net is equal to or below a predetermined coupling capacitance threshold. Responsive to net being able to be routed through the cell with the coupling capacitance being equal to or below the threshold, the net is assigned to at least one track within the cell. Responsive to all nets in the new IC design being routed, a new IC design is generated.

Abstract: Some embodiments of the inventive subject matter are directed to detecting a modification of a portion of content presented on a display. The detecting of the modification of the portion of content is in response to user input. Some embodiments are further directed to generating a screen capture of at least the portion of the content presented on the display in response to detecting the modification of the portion of the content. Some embodiments are further directed to generating an indicator (e.g., an annotation) in response to generating the screen capture. The indicator specifies (e.g., highlights) the modification (e.g., a difference in appearance) of the portion of the content that occurred via the user input. Some embodiments are further directed to associating the indicator with the screen capture.

Abstract: A method of making a semiconductor structure includes patterning a barrier layer metallurgy (BLM) which forms an undercut beneath a solder material, and forming a repair material in the undercut and on the solder material. The method also includes removing the repair material from the solder material, and reflowing the solder material.

Abstract: A method for implementing systematic, variation-aware integrated circuit extraction includes inputting a set of processing conditions to a plurality of variation models, each model corresponding to a separate systematic, parametric variation associated with semiconductor manufacturing of an integrated circuit layout; generating, for each variation model, a netlist update attributable to the associated variation, wherein the netlist update is an update with respect to an original netlist extracted from the integrated circuit layout; and storing the netlist updates generated for each of the processing conditions.

Abstract: A method to read information from an information storage medium using a read channel, where that read channel includes a data cache, where the method generates an analog waveform comprising the information, provides that analog waveform to a read channel generates a digital signal from that analog waveform using one or more first operating parameters, corrects that digital signal at an actual error correction rate, determines if the actual error correction rate is greater than an error correction rate threshold. If the actual error correction rate exceeds the error correction rate threshold, then the method captures the digital signal, stores that captured data in a data cache, reads that digital signal from the cache, generates one or more second operating parameters, provides those one or more second operating parameters to the read channel.

Abstract: Semiconductor structures, methods of manufacture and design structures are provided. The structure includes at least one offset crescent shaped solder via formed in contact with an underlying metal pad of a chip. The at least one offset crescent shaped via is offset with respect to at least one of the underlying metal pad and an underlying metal layer in direct electrical contact with an interconnect of the chip which is in electrical contact with the underlying metal layer.

Abstract: A method, system, and computer program product for using documentation plans for service oriented architecture governance. In an example embodiment, the method includes implementing a structured documentation plan in a SOA governance tool using a computer processor. The structured documentation plan includes a set of documentation types and a set of governance policies for at least one documentation type from the set of documentation types.