Abstract: A method, system and apparatus for selective macro event recording. In accordance with the present invention, events can be selectively included in a macro recording process, even where the events occur across different contexts such as different application windows in different applications. Specifically, once a macro recording session has been initiated for a particular application or application window, events occurring in different applications or application windows can be selected for inclusion in the macro through an append recording operation. Notably, the selective macro recording facility can be included as part of an operating environment, or as part of the individual applications executing within the operating environment.

Abstract: A system and method for generating web services from an existing web site having web page based business processes or transactions. A script is generated representative of a user navigation sequence involved to perform the transaction. The script elements include the web application calls, input/output parameters, and/or the interrelation between the elements of the transaction. A WSDL file, web service interface code, and web service implementation code are generated from the navigation script, and may be published locally to the web site or on a remote site.

Abstract: Conductive sidewall spacer structures are formed using a method that patterns structures (mandrels) and activates the sidewalls of the structures. Metal ions are attached to the sidewalls of the structures and these metal ions are reduced to form seed material. The structures are then trimmed and the seed material is plated to form wiring on the sidewalls of the structures.

Abstract: A complementary metal oxide semiconductor (CMOS) device, e.g., a field effect transistor (FET), that includes at least one one-dimensional nanostructure that is typically a carbon-based nanomaterial, as the device channel, and a metal carbide contact that is self-aligned with the gate region of the device is described. The present invention also provides a method of fabricating such a CMOS device.

Abstract: A multiprocessor data processing system (MDPS) with a weakly-ordered architecture providing processing logic for substantially eliminating issuing sync instructions after every store instruction of a well-behaved application. Instructions of a well-behaved application are translated and executed by a weakly-ordered processor. The processing logic includes a lock address tracking utility (LATU), which provides an algorithm and a table of lock addresses, within which each lock address is stored when the lock is acquired by the weakly-ordered processor. When a store instruction is encountered in the instruction stream, the LATU compares the target address of the store instruction against the table of lock addresses. If the target address matches one of the lock addresses, indicating that the store instruction is the corresponding unlock instruction (or lock release instruction), a sync instruction is issued ahead of the store operation.

Abstract: A method for reducing the size of a patterned semiconductor feature includes forming a first layer over a substrate to be patterned, and forming a photoresist layer over the first layer. The photoresist layer is patterned so as to expose portions of the first layer, and the exposed portions of the first layer are removed in a manner so as to create an undercut region beneath the patterned photoresist layer. The patterned photoresist layer is reflowed so as to cause reflowed portions of the patterned photoresist layer to occupy at least a portion of the undercut region.

Abstract: A method of clustering ordered data sets, wherein the method comprises forming n-dimensional curvilinear representations from an ordered data set; formulating a n+1-dimensional curvilinear representation from a pair of ordered data sets; computing a similarity of the pair of ordered data sets using a similarity between the n-dimensional curvilinear representations and the n+1-dimensional curvilinear representation; and clustering ordered data sets based on the similarity between the n-dimensional curvilinear representations and the n+1-dimensional curvilinear representation. In the n-dimensional curvilinear representations, a first dimension of space corresponds with a common ordering dimension and the remaining dimension of space corresponds with the ordered data set. The process of computing the similarity comprises comparing a shape of the n+1-dimensional curvilinear representation to a shape of each component n-dimensional curvilinear representation.

Abstract: Interconnect structures possessing an organosilicate glass based material for 90 nm and beyond BEOL technologies in which a multilayer hardmask using a line-first approach are described. The interconnect structure of the invention achieves respective improved device/interconnect performance and affords a substantial dual damascene process window owing to the non-exposure of the OSG material to resist removal plasmas and because of the alternating inorganic/organic multilayer hardmask stack. The latter feature implies that for every inorganic layer that is being etched during a specific etch step, the corresponding pattern transfer layer in the field is organic and vice-versa.

Abstract: A calibrated magnetic random access memory (MRAM) current sense amplifier includes a first plurality of trim transistors selectively configured in parallel with a first load device, the first load device associated with a data side of the sense amplifier. A second plurality of trim transistors is selectively configured in parallel with a second load device, the second load device associated with a reference side of the sense amplifier. The first and said second plurality of trim transistors are individually activated so as to compensate for device mismatch with respect to the data and reference sides of the sense amplifier.

Abstract: A dynamic predictive and/or exact caching mechanism is provided in various stages of a microprocessor pipeline so that various control signals can be stored and memorized in the course of program execution. Exact control signal vector caching may be done. Whenever an issue group is formed following instruction decode, register renaming, and dependency checking, an encoded copy of the issue group information can be cached under the tag of the leading instruction. The resulting dependency cache or control vector cache can be accessed right at the beginning of the instruction issue logic stage of the microprocessor pipeline the next time the corresponding group of instructions come up for re-execution. Since the encoded issue group bit pattern may be accessed in a single cycle out of the cache, the resulting microprocessor pipeline with this embodiment can be seen as two parallel pipes, where the shorter pipe is followed if there is a dependency cache or control vector cache hit.

Abstract: A method of reducing hot carrier degradation and a semiconductor structure so formed are disclosed. One embodiment of the method includes depositing a silicon nitride layer over a transistor device, ion implanting a species into the silicon nitride layer to drive hydrogen from the silicon nitride layer, and annealing to diffuse the hydrogen into a channel region of the transistor device. The species may be chosen from, for example: germanium (Ge), arsenic (As), xenon (Xe), nitrogen (N), oxygen (O), carbon (C), boron (B), indium (In), argon (Ar), helium (He), and deuterium (De). The ion implantation modulates atoms in the silicon nitride layer such as hydrogen, nitrogen and hydrogen-nitrogen bonds such that hydrogen can be controllably diffused into the channel region.

Abstract: A method and structure for fabricating a strained semiconductor on a relaxed SiGe substrate which has dopant diffusion control and defect reduction are provided. Specifically, the dopant diffusion control and defect reduction is achieved in the present invention by providing a SiGe buffer layer between the strained semiconductor and the underlying relaxed SiGe substrate. In accordance with the present invention, the SiGe buffer layer has a Ge content that is less than the Ge content which is present in the relaxed SiGe substrate.

Abstract: A database optimizer collects statistics regarding applications accessing a database, and makes one or more changes to the database schema to optimize performance according to the collected statistics. In a first embodiment, the optimizer detects when a certain type of application accesses the database a percentage of time that exceeds a predefined threshold level, and if the data in the database is stored in a less-than-optimal format for the application, the data type of one or more columns in the database is changed to a more optimal format for the application. In a second embodiment, the optimizer detects when one type of application accesses a column a percentage of time that exceeds a first predefined threshold level and is less than a second predefined threshold level, and creates a new column in the database so the data is present in both formats.

Abstract: A computing system is provided which includes a processor having a cache memory. The cache memory includes a plurality of independently configurable subdivisions, each subdivision including a memory array. A service element (SE) of the computing system is operable to cause a built-in-self-test (BIST) to be executed to test the cache memory, the BIST being operable to determine whether any of the subdivisions is defective. When it is determined that one of the subdivisions of the cache memory determined defective by the BIST is non-repairable, the SE logically deletes the defective subdivision from the system configuration, and the SE is operable to permit the processor to operate without the logically deleted subdivision. The SE is further operable to determine that the processor is defective when a number of the defective subdivisions exceeds a threshold.

Abstract: The present invention broadly contemplates addressing QoS concerns in overlay design to account for the last mile problem. In accordance with the present invention, a simple queuing network model for bandwidth usage in the last-mile bottlenecks is used to capture the effects of the asymmetry, the contention for bandwidth on the outgoing link, and to provide characterization of network throughput and latency. Using this characterization computationally inexpensive heuristics are preferably used for organizing end-systems into a multicast overlay which meets specified latency and packet loss bounds, given a specific packet arrival process.

Abstract: A method, computer program product, and a data processing system for performing data replication in a multi-mastered system is provided. A first data processing system receives a replication command generated by a second data processing system. A conflict is identified between a first entry maintained by the first data processing system and a second entry of the second data processing system. Responsive to identifying the conflict, a one of the first entry and the second entry is determined to be a most recently modified entry and a remaining entry of the first and second entries is determined to be a least recently modified entry. The least recently modified entry is replaced with the most recently modified entry, and the least recently modified entry is logged.

Abstract: Situation detection systems and methods are provided, in which the capabilities of standard event stores and relational systems are enhanced by augmented event-oriented algebraic operators. Rules involving the event-oriented operators are combined with conventional relational algebraic techniques, and applied to an event database in order to detect more complex patterns, indicative of composite events or situations.

Abstract: Methods, systems, and computer programs for servicing and/or providing spontaneous collaboration between a shopper and consultants concerning a shopping goal. Information about the shopper's physical or logical proximity to a particular product category, combined with the current contents of his or her shopping cart is used to determine one or more shopping goals. Information about each potential consultant, including physical proximity, willingness to consult, areas of expertise and recent experience is used to rank each consultant in terms of relevance to one or more shopping goal. Communication is established between the shopper and one or more consultants in order that consulting services be provided. Consultants' evaluations are maintained persistently for use in future ranking. In some cases collaboration is coordinated by a service bureau.

Abstract: The invention broadly and generally provides, in a computer-controlled display, a method of simplifying a graphical representation of a set of connected nodes comprising the steps of: (a) selecting a subset of the aforesaid set; and (b) under computer program control, hiding representations of all nodes except (i) nodes within the aforesaid subset and (ii) at least one node having a defined relationship to the aforesaid subset.

Abstract: A wireless device connects to one or more network node devices that are in turn connected to one or more wirelines. The wireless device has one or more wireless signal generators supporting one or more of the wireless connections and one or more memories to store an identifier. One or more negotiators negotiate with the network node device in order to establish a connection to one or more wirelines connected to the network node and a requesting process requests bridging to a call in progress.

Abstract: A database is queried with on demand database query reduction A query document includes global variables selectively set off by first tags identifying a first global variable as a complete replacement variable and by second tags identifying a second global variable as a complete removal string. An agent is provided for building from the query document an expanded query by replacing any variables set off by first tags with runtime strings, setting off any unions in the query document, and selectively replacing any variables set off by second tags and removing the second tags without replacing variables set off by second tags.

Abstract: A communication system (100) has a portal (110), a subscriber (108), a plurality of content providers (112), and a communication network for providing communication between the portal, the subscriber and the plurality of content providers. The components of the communication system are programmed to transmit to the subscriber from the portal an available selection of the plurality of content providers, select at the subscriber a select one of the plurality of content providers, and transmit content provider registration corresponding to the selected content provider from the portal to the selected content provider.

Abstract: A method includes determining whether or not a statement in a design has any functionality. The functionality includes impact on the operation of the design. Also included in the invention is in impact checker to determine the impact of portions of the design on the operation of the design.

Abstract: A chip is provided in which an on-chip matching network has a first terminal conductively connected to a bond pad of the chip and a second terminal conductively connected to a common node on the chip. A wiring trace connects the on-chip matching network to a circuit of the chip. The on-chip matching network includes an electrostatic discharge protection (ESD) circuit having at least one diode having a first terminal conductively connected to the bond pad and a second terminal connected in an overvoltage discharge path to a source of fixed potential. The matching network further includes a first inductor coupled to provide a first inductive path between the bond pad and the wiring trace, a termination resistor having a first terminal connected to the common node, and a second inductor coupled to provide a second inductive path between the wiring trace and a second terminal of the termination resistor.

Abstract: A fanning route generation technique is provided for multi-path networks having a shared communications fabric. The technique includes selecting a source node-destination node (S-D) group having common starting and ending sets of links from the network of interconnected nodes. Within this group, selecting the shortest routes between the S-D nodes of the group so that: selected routes substantially uniformly fan out from the source node to a center of the network and fan in from the center of the network to the destination node, thereby achieving local balance; and global balance of routes passing through links that are at a same level of the network is achieved.

Abstract: A system, method and program storage device for providing wireless connectivity to a user on a communications network including a plurality of users, each user having wireless connection capability and wired connection capability to a network server, including determining if a valid wired address is assigned to a first user; determining if a valid wireless address is assigned to the first user; responsive to the first user having both a valid wired address assigned and a valid wireless address assigned, the first user releasing one of the valid addresses for assignment to a second user. Requests from a user for first or second priority level address assignment are selectively granted by releasing and reassigning third or second priority level address assignments.

Abstract: A system and method for maintaining checkpoints of a keyed data structure using a sequential log are provided. The system and method are built upon the idea of writing all updates to a keyed data structure in a physically sequential location. The system and method make use of a two-stage operation. In a first stage, various values of the same key are combined such that only the latest value in a given checkpoint interval is maintained for writing to persistent storage. In a second stage of the operation, a periodic write operation is performed to actually store the latest values for the key-value pairs to a persistent storage. All such updates to key-value pairs are written to the end of a sequential log. This minimizes the physical storage input/output (I/O) overhead for the write operations. Data structures are provided for identifying the most current entries in the sequential log for each key-value pair.

Abstract: A method of automatically and intelligently maintaining business systems, including information technology assets. A management system automatically maintains a business system based on relationships among resources within the business system and/or on a priority rank that establishes the value or importance of a particular resource. The management system, and optionally the user, can also create rules for maintaining relationships among resources and for maintaining relationships among different business systems. The management system automatically adapts to a change in rules by maintaining relationships among resources and business systems based on a change in the rules.

Abstract: Disclosed are a method and a system for redistributing white space on an integrated circuit. The method comprises the steps of providing a series of circuit blocks for the integrated circuit, and placing the blocks on the integrated circuit to obtain a predefined optimal wire length. In accordance with the preferred embodiment of the invention, we first show that the problem of placing the blocks to obtain an optimal wire length, can be formulated as linear programming. Then, we find it can be solved by efficient min-cost flow implementation instead of general and slow linear programming. The approach guarantees to obtain the minimum total wire length for a given floorplan topology. We also show that the approach is capable of handling various constraints such as fixed-frame (fixed area), IO pins, pre-placed blocks, boundary blocks, range placement, alignment and abutment, rectilinear blocks, cluster placement, and bounded net delay, without loss of optimality.

Abstract: System and method for distinguishing between foreground content and background content in an image presentation. An initial background model is provided, and a final background model is constructed from the initial background model using the image presentation. The foreground content and background content in the image presentation are then distinguished from one another using the final background model. The present invention permits foreground content and background content to be separated from one another for further processing in different types of computer-generated image presentations such as digital slide presentations, video presentations, Web page presentations, and the like.

Abstract: The present invention provides for a method for memory array verification. Initialization commands are received and memory array initialization settings are generated based on received initialization commands. The memory array initialization settings are stored in a memory array. A deterministic read output function for the memory array is identified and a logic built-in self test scan on the memory array is performed based on the identified deterministic read output function.

Abstract: A method for indexing a plurality of documents, that includes a plurality of duplicate documents, first identifies one or more duplicate groups of documents from among the plurality of documents. Then, one index of content for the duplicate group is created instead of indexing the content from every document within the duplicate group. However, in contrast to the content index, an index of metadata for each of the documents in the duplicate group is created. Thus the content of each duplicate group is indexed only once, while a search engine using such indexing techniques retains the capability to answer queries as if the duplicated content was indexed for each document of the group.

Abstract: A structure and method where C is incorporated into the collector region of a heterojunction bipolar device by a method which does not include C ion implantation are provided. In the present invention, C is incorporated into the collector by epitaxy in a perimeter trench etched into the collector region to better control the carbon profile and location. The trench is formed by etching the collector region using the trench isolation regions and a patterned layer over the center part of the collector as masks. Then, Si:C is grown using selective epitaxy inside the trench to form a Si:C region with sharp and well-defined edges. The depth, width and C content can be optimized to control and tailor the collector implant diffusion and to reduce the perimeter component of parasitic CCB.

Abstract: A method and apparatus are provided for implementing AC power dissipation control during scan operations in scannable latch designs. A scannable latch has a functional data output and a scan data output. A switching control is provided with the functional data output. The switching control is driven to prevent switching of the functional data output during at least part of the scan operations. Then the switching control is disabled enabling switching of the functional data output during functional data operations.

Abstract: A method, system, and program for automatically distributing a bid request for a grid job to multiple grid providers and analyzing responses to select a winning grid provider are provided. A user at a grid client enters at least one bid criteria for a particular grid job intended for submission to an external grid environment. The grid client automatically selects at least one grid provider for the external grid environment to query for availability to process the particular grid job to meet the criteria for the particular grid job. Then, the grid client automatically distributes the criteria in a bid request for the particular grid job to the selected grid providers. The grid client stores bid responses received from the grid providers, and responsive to reaching a deadline for return of responses for the bid request, the grid client selects a winning bid response from the particular grid job from among the received responses.

Abstract: A method for verifying correctness of an Information Technology (IT) structure instance D of an IT structure R, a method for detecting an unauthorized change in an operating instance X of an IT structure R, a method for verifying conformance of an IT structure to an IT delivery environment, associated computer program products, and associated processes for integrating computing infrastructure. The method for verifying correctness of an IT structure instance D determines whether a reverse specification RD for D differs from R. The method for detecting an unauthorized change in an operating instance X of an IT structure R determines whether authorized changes in R have occurred. The method for verifying conformance of an IT structure to an IT delivery environment verifies compliance of the IT structure relating to: product standard compliance, compliance of software elements of the IT structure primitive composition, software application type compliance, and network traffic compliance.

Abstract: A method for generating an offset field for a magnetic random access memory (MRAM) device includes forming a first pinned layer integrally with a wordline, and forming a second pinned layer integrally with a bitline. An MRAM cell is disposed between the wordline and the bitline, the MRAM cell including a reference layer, an antiparallel free layer and a tunnel barrier therebetween. The first pinned layer is formed with an internal magnetization in a manner so as to create a first external field generally perpendicular to a long axis of the wordline, and the second pinned layer is formed with an internal magnetization in a manner so as to create a second external field generally perpendicular to a long axis of the bitline.

Abstract: An exhaust system is provided for a plurality of machines, each machine having an exhaust stream connected to a local branch of the system. The system includes a stabilizer connected to an exhaust line in parallel to the exhaust stream of a machine. The stabilizer controls an exhaust pressure in the exhaust stream by opening and closing in response to variations in the exhaust pressure; the stabilizer opens to admit gas flow into the exhaust line when the exhaust pressure is less than a predetermined value, and closes when the exhaust pressure is greater than that predetermined value. The stabilizer unit thus provides a constant static exhaust pressure. The stabilizer provides relief flow in the exhaust stream, causing the gas flow into the exhaust line to increase when an exhaust flow in the exhaust stream decreases.

Abstract: Fully silicided planar field effect transistors are formed by avoiding the conventional chemical-mechanical polishing step to expose the silicon gate by etching the sidewalls down to the silicon; depositing a sacrificial oxide layer thinner on the top of gate and sidewall of spacers, but thicker over the S/D areas, etching the oxide to expose the top of stacked gate while protecting the S/D; recessing the silicon; stripping the oxide; depositing metal and annealing to form silicide over the gate and S/D.

Abstract: A method for post lithographic critical dimension shrinking of a patterned semiconductor feature includes forming an overcoat layer over a patterned photoresist layer, and removing portions of the overcoat layer initially formed over top surfaces of the patterned photoresist layer. The remaining portions of the overcoat layer on sidewalls of said patterned photoresist layer are reacted so as to chemically bind the remaining portions of the overcoat layer on the sidewalls.

Abstract: The present invention provides a method, system, and computer program product for checking for viruses by adding a virus scanning capability to a data transfer device. In a method of the present invention a real-time virus checker is stored on a controller. The virus checker scans data as it is being written to a file. If a virus is detected, the suspected file is flagged. Anti-virus software is then invoked to perform a scan of the entire suspected file. In this manner, demands on CPU resources to perform scans will be greatly reduced as only those files marked as possibly containing a viruse need to be scanned, rather than scanning all the files on the entire data transfer device.

Abstract: A recorder system contains a media key block (MKB) and selectively writes protected content into a recording medium according to the following content protection logic, to combat theft of the protected content: If the medium does not have a MKB, then the recorder writes its stored MKB into the medium and writes protected content into the medium. If the medium has a MKB that is older than the stored MKB in the recorder, then the recorder writes its stored MKB into the medium before re-encrypting and writing protected content into the medium. If the medium has a MKB that is newer than the stored MKB, then the MKB in the medium is used for content protection. The recorder may store the newer MKB in non-volatile memory, effectively updating its previous stored MKB, so the recorder will have the most recently observed MKB for content protection use.

Abstract: A magnetic random access memory (MRAM) device includes a reference magnetic region having a resultant magnetic moment vector generally maintained in a desired orientation without the use of exchange coupling thereto. A storage magnetic region has an anisotropy easy axis and a resultant magnetic moment vector oriented in a position parallel or antiparallel to that of the reference magnetic region. A tunnel barrier is disposed between the reference magnetic region and the storage magnetic region, with the reference magnetic region, storage magnetic region and tunnel barrier defining a storage cell configured for a toggle mode write operation. The storage cell has an offset field applied thereto so as to generally maintain the resultant magnetic moment vector of the reference magnetic region in the desired orientation.

Abstract: Method and apparatus for reformatting instructions in a pipelined processor. An instruction register holds a plurality of instructions received from a cache memory external to the processor. A predecoder predecodes each of the instructions and determines from an instruction operation field where the instruction fields should be placed. A multiplexer reformats architecturally aligned instructions into hardware implementation aligned instructions prior to storing into L1 cache, so that the instructions are ready for dispatch to the pipeline execution units.

Abstract: A method of manufacturing fin-type field effect transistors (FinFETs) forms a silicon layer above a substrate, forms a mask pattern above the silicon layer using a multi-step mask formation process, patterns the silicon layer into silicon fins using the mask pattern such that the silicon fins only remain below the mask pattern, removes the mask pattern to leave the fins on the substrate, and forms gate conductors over the fins at a non-perpendicular angle to the fins.

Abstract: Methods of manufacturing a semiconductor structure are disclosed including a deep trench isolation in which a channel stop is formed in the form of an embedded impurity region in the substrate prior to the deep trench etch and formation of transistor devices (FEOL processing) on the substrate. In this fashion, the FEOL processing thermal cycles can activate the impurity region. The deep trench isolations are then formed after FEOL processing. The method achieves the reduced cost of forming deep trench isolations after FEOL processing, and allows the practice of sharing of a collector level between devices to continue. The invention also includes the semiconductor structure so formed.

Abstract: A method, apparatus, and computer instructions for selecting and recommending of clustering indexes are provided. Baseline run time cost estimates are calculated based on database designs. Workload benefit of a candidate clustering design is calculated and compared to the baseline costs. If the workload benefit outweighs the baseline costs, clustering dimension solutions originated from the record identifier (RID) based index are identified. A clustering design is selected based on the identified clustering dimension solutions and the total number of recommended clustering dimensions for a given table. Based on the number of dimensions observed, either a multidimensional clustering solution or a RID based clustering index is recommended.

Abstract: A method for implementing a temperature cycling operation for a biochemical sample to be reacted includes applying an infrared (IR) heating source to the sample at a first infrared wavelength selected so as to generate a first desired temperature for a first duration and produce a first desired reaction within the sample. Following the first desired reaction, applying the infrared (IR) heating source to the sample at a second infrared wavelength selected so as to generate a second desired temperature for a second duration and produce a second desired reaction within the sample.

Abstract: A method, system, and computer program product that provide for more uniform pricing of utility computing resources, such as a computing grid. One aspect of the present invention is a method of calculating costs in a utility computing environment comprising receiving a request to process a work unit from a requester, generating at least one performance metric associated with the work unit, and debiting the requestor for processing the work unit based at least in part on the performance metric. The performance metric in this embodiment is related to an amount of resources required to process the work unit under predetermined conditions.

Abstract: In one aspect, a method is provided. The method includes the steps of (1) sharing memory bandwidth between a processor and one or more direct memory access (DMA) engines; (2) providing memory bandwidth to a DMA engine; (3) starting a data transfer between a memory and the DMA engine, via the memory bandwidth, based on a first preemption boundary value, wherein the data transfer may be preempted after transferring an amount of data equal to an integral multiple of the first preemption boundary value; (4) while transferring data between the memory and DMA engine, determining whether a request for memory bandwidth is received from the processor, wherein the processor is in an interrupt state; and (5) if so, adjusting the first preemption boundary value such that the adjusted preemption boundary value enables the processor to receive memory bandwidth sooner than the first preemption boundary value. Numerous other aspects are provided.