IBM Patents
The International Business Machines Corporation provides IT infrastructure and services to enterprise customers.
IBM Patents by Type- IBM Patents Granted: IBM patents that have been granted by the United States Patent and Trademark Office (USPTO).
- IBM Patent Applications: IBM patent applications that are pending before the United States Patent and Trademark Office (USPTO).
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Patent number: 7072849Abstract: A method for presenting advertising in an interactive service provided on a computer network, the service featuring applications which include pre-created, interactive text/graphic sessions is described. The method features steps for presenting advertising concurrently with service applications at the user terminal configured as a reception system. In accordance with the method, the advertising is structured in a manner comparable to the service applications enabling the applications to be presented at a first portion of a display associated with the reception system and the advertising presented at a second portion. Further, steps are provided for storing and managing advertising at the user reception system so that advertising can be pre-fetched from the network and staged in anticipation of being called for presentation.Type: GrantFiled: November 26, 1993Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Robert Filepp, Alexander W. Bidwell, Francis C. Young, Allan M. Wolf, Duane Tiemann, Mel Bellar, Robert D. Cohen, James A. Galambos, deceased, Kenneth H. Appleman, Sam Meo
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Patent number: 7072841Abstract: The invention considers a widely applicable method of constructing segmentation-based predictive models from data that permits constraints to be placed on the statistical estimation errors that can be tolerated with respect to various aspects of the models that are constructed. The present invention uses these statistical constraints in a closed-loop fashion to guide the construction of potential segments so as to produce segments that satisfy the statistical constraints whenever it is feasible to do so. The method is closed-loop in a sense that the statistical constraints are used in a manner that is analogous to an error signal in a feed-back control system, wherein the error signal is used to regulate the inputs to the process that is being controlled.Type: GrantFiled: April 29, 1999Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventor: Edwin Peter Dawson Pednault
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Patent number: 7072805Abstract: Disclosed are a method and system for predicting future values of a target metric associated with a task executed on a computer system. The method includes the steps of, over a given period of time, measuring at least one defined metric, transforming that measurement into a value for a predictor source metric, and using the value for the predictor source metric to obtain a predicted future value for said target metric. The preferred embodiment of this invention provides a flexible performance multi-predictor to solve the problem of providing accurate future behavior predictions for adaptive reconfiguration systems. The multi-predictor makes predictions about future workload characteristic by periodically reading available hardware counters. Also disclosed is a method and system for periodically reconfiguring an adaptive computer system by rescheduling tasks based on future behavior predictions.Type: GrantFiled: October 17, 2003Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Gheorghe C. Cascaval, Evelyn Duesterwald, Sandhya Dwarkadas
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Patent number: 7072900Abstract: A system and method for developing topography based management systems is presented. A software system is designed using a layered approach that provides a topography that is suitable to a particular management philosophy or particular customer requirements. The topography can be viewed as a fabric that provides an infrastructure that supports the customer's management philosophy and other requirements. The topography addresses deployment mechanisms, such as interfaces between applications and users, security infrastructure, such as what control is asserted and maintained for the topography, component interaction defining how components installed on the topography interact with one another, and operation conduits that determine where and how processing is performed within the infrastructure. These same capabilities are addressed by other topographies that are developed. Common topography-neutral application components are designed and built to be installed on any topography.Type: GrantFiled: November 28, 2001Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: John William Sweitzer, Douglas Andrew Wood
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Patent number: 7072131Abstract: A storage device in which file data is divided into multiple blocks for storage on a recording medium. The storage device includes an additional data storing section for storing additional data to be recorded on the recording medium in association with the data to be written, a position determining section for determining recording positions on the recording medium where the blocks should be respectively written, based on the additional data, and a block writing section for writing the respective blocks on the recording positions on the recording medium determined by the recording position determining section. The additional data thus defines a gap length between blocks of recorded data. During a read operation, if the gap length does not comport with the additional data, then an error is assumed.Type: GrantFiled: October 20, 2003Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Tomoaki Kimura, Satoshi Tohji
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Patent number: 7073135Abstract: A method of information personalization is provided, whereby the information has an associated status indication (such as, an image or picture for example). Firstly, information is displayed (via a Web browser for example). Next, a process to determine the presence of one or more attributes associated with the status indication is carried out. If it is determined that one or more attributes exist, each of the attributes is compared against a respective threshold, whereby each of the thresholds determines rendering of the associated status indication. In response to the comparing, if one or more respective thresholds are met, the associated status indication is displayed as an updated status indication (whereby, the status indication is partially visible or non-visible for example). If one or more respective thresholds are not met, the associated status indication is displayed (whereby, the status indication is unchanged for example).Type: GrantFiled: May 9, 2002Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventor: Robert Harris
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Patent number: 7072867Abstract: A system and method for a third party logging server to keep track of sales by online merchants of copyrighted works. Providers of copyrighted works, such as publishers and authors, register with the third party logging server and acquire an authentication mechanism to use the server, such as a username and password. The providers upload digital works and royalties corresponding to the works to the third party logging proxy server. Online merchants register with the third party logging proxy server and also acquire an authentication mechanism to use the server. The merchant downloads works and royalty rates to the merchant's computer for online sales. The merchant also downloads software that informs the third party logging proxy server whenever the merchant makes a sale. The server keeps track of the sale. The server collects royalty payments from merchants. The server also calculates and sends providers their royalty payments.Type: GrantFiled: November 30, 2000Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventor: Rabindranath Dutta
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Patent number: 7073121Abstract: A method for presenting content from the page in a distributed database. In a preferred embodiment, a server receives a request from a client for a page from the database wherein the page has a plurality of links to linked pages in the database. The server retrieves the page and generates a set of thumbnails of the linked pages in the database. The server then sends the page and the set of thumbnails to the client.Type: GrantFiled: November 26, 2002Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Michael Wayne Brown, Kelvin Roderick Lawrence, Michael A. Paolini
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Patent number: 7070539Abstract: In accordance with the method, system and program of the present invention, at least one type of exercise indicator signal associated with exercise performed by a particular user is received from a particular exercise machine in a common transmittable data format at a portable computer system provided the particular user. Cumulative fitness activity is computed and stored for the particular user at the portable computer system utilizing the at least one type of exercise indicator signal and previously accumulated fitness activity data at the portable computer system, such that an independent portable computer system associated with the particular user monitors the real-time cumulative fitness activity of the particular user from at least one type of exercise indicator signal received from at least one exercise machine over a period of time.Type: GrantFiled: October 14, 2003Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Michael Wayne Brown, Kelvin Roderick Lawrence, Michael A. Paolini
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Patent number: 7071924Abstract: A system and method for providing input to a handheld computing device by provisioning the handheld computing device with a projecting device a projecting device for displaying a graphical representation of a keyboard, the graphical representation including key locations capable of being selected by an object, the graphical image displayed in an area proximate the device; a signal detection system for detecting the presence of an object located at a selected key location within the area; and, a mechanism for determining the selected key in response to detecting an object at a corresponding selected key location and registering the selected key as a keystroke in the computing device.Type: GrantFiled: January 10, 2002Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Tijs Wilbrink, Edward E. Kelley
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Patent number: 7071122Abstract: A method for making an ultrathin high-k gate dielectric for use in a field effect transistor is provided. The method involves depositing a high-k gate dielectric material on a substrate and forming an ultrathin high-k dielectric by performing a thinning process on the high-k gate dielectric material. The process used to thin the high-k dielectric material can include at least one of any number of processes including wet etching, dry etching (including gas cluster ion beam (GCIB) processing), and hybrid damage/wet etching. In addition to the above, the present invention relates to an ultrathin high-k gate dielectric made for use in a field-effect transistor made by the above method.Type: GrantFiled: December 10, 2003Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Katherine L. Saenger, Rajarao Jammy, Vijay Narayanan
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Patent number: 7073004Abstract: The address tenure for PCR synchronization operations is redefined to support inclusion of the synchronization data within the address tenure. The bits of a particular field within the address tenure (e.g., the address field) are re-allocated to synchronization data, which is known to be small enough to fit within the unused bits. The address tenure is then broadcasted as a normal address operation and is snooped by all of the processors. The snooping logic is designed to recognize regular/normal address tenures and these modified address tenures and respond to a receipt of a modified address tenure by removing the synchronization data stored therein and updating the corresponding register location of the PCR.Type: GrantFiled: April 28, 2003Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Ravi Kumar Arimilli, Derek Edward Williams
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Patent number: 7070087Abstract: The present invention relates to improvements in forming and transferring solder bumps for use in mounting integrated circuit substrates on chip carrier packages. A mold having cavities for the solder bumps is held in contact with a substrate and a compressible device. As the temperature is increased to melt the solder in the cavities, at an appropriate time and temperature, the compressible device is caused to decompress resulting in the mold separating from the substrate and leaving formed solder bumps on the contacts on the substrate. Various mechanisms are described to cause the force holding the mold and substrate together to decrease.Type: GrantFiled: December 3, 2003Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Guy Brouillette, David Danovitch, Jean-Paul Henry
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Patent number: 7072299Abstract: A receiver may be adapted to prevent overflow or underflow of its data storage by generating a transmit rate value as a feedback to the sender. Speed adjustments are performed periodically with a fixed time period denoted by Dt. Transmission rates are explicitly 0, Max/2, and Max. The receiver queue is itself drained at a rate R that at any time satisfies 0<=R<=Max. The level of occupancy of the receiver storage queue is denoted by Q. The maximum capacity of the receiving queue is designated Qmax, so at any time, 0<=Q<=Qmax. Two thresholds T1 and T2 (with 0<T1<T2<Qmax) of levels of the receiver queue value Q are determined. A transmit rate is then determined by the level of the receiver queue Q compared to the thresholds. The transmit rate feedback value achieves the desired goal of avoiding overflow and, once the value of Q has been positive at least once, avoiding underflow.Type: GrantFiled: August 20, 2001Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Brian Mitchell Bass, Clark Debs Jeffries, Michael Steven Siegel
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Patent number: 7073112Abstract: An apparatus that improves Built-In-Self-Test (BIST) flexibility. A compilable address magnitude comparator facilitates BIST testing of different size memory arrays without requiring customization of the BIST controller. The compilable address magnitude comparator is compiled within the compilable memory arrays of the ASIC to allow a single BIST controller to test multiple sizes of memory arrays without requiring that the BIST controller be compilable. The compilable magnitude address comparator overrides the self-test signal from the BIST when the BIST attempts to test addresses not existing in the memory. The BIST is prevented from writing to addresses that do not exist, and does not receive error signals from those addresses. The BIST controller is able to test memory arrays without regard for their particular size. A single BIST controller can be used to test multiple memory arrays of different sizes in the ASIC, reducing device complexity.Type: GrantFiled: October 8, 2003Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Chiaming Chai, Jeffrey H. Fischer, Michael R. Ouellette, Michael H. Wood
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Patent number: 7071530Abstract: A method of forming a semiconductor structure, comprising: providing a substrate having a buried insulative layer and a heavily doped layer; forming a first trench within the substrate around a protected area; filling the first trench with an insulative material, wherein the first trench filled with the insulative material and the buried insulative layer combine to form a high impedance noise isolation that surrounds the protected area on all sides except one side of the protected area to isolate noise from the protected area; forming a second trench within the substrate around the first trench; and filling the second trench with a conductive material, wherein the second trench filled with the conductive material and the heavily doped layer combine to form a low impedance ground path that surrounds the high impedance noise isolation on all sides except one side of the high impedance noise isolation to isolate noise from the protected area.Type: GrantFiled: January 27, 2005Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Hanyi Ding, Kai D. Feng, Zhong-Xiang He, Xuefeng Liu
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Patent number: 7071099Abstract: Methods of forming different back-end-of-line (BEOL) wiring for different circuits on the same semiconductor product, i.e., wafer or chip, are disclosed. In one embodiment, the method includes simultaneously generating BEOL wiring over a first circuit using a dual damascene structure in a first dielectric layer, and BEOL wiring over a second circuit using a single damascene via structure in the first dielectric layer. Then, simultaneously generating BEOL wiring over the first circuit using a dual damascene structure in a second dielectric layer, and BEOL wiring over the second circuit using a single damascene line wire structure in the second dielectric layer. The single damascene via structure has a width approximately twice that of a via portion of the dual damascene structures and the single damascene line wire structure has a width approximately twice that of a line wire portion of the dual damascene structures.Type: GrantFiled: May 19, 2005Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Stephen E. Greco, Theodorus E. Standaert
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Patent number: 7072393Abstract: System and method are provided for optimally encoding a sequence of video frames using image statistics collected from multiple encoders connected in parallel, each encoder employing a different set of encode parameters. The image statistics are used to select an optimum set of encode parameters for use in encoding the sequence of video frames in a subsequent encode subsystem stage. As an alternative, multiple buffers are connected to the outputs of the multiple, parallel connected encoders, with the encoded stream from the encoder employing the optimum set of encode parameters selected for output as the bitstream of encoded video data.Type: GrantFiled: June 25, 2001Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Charles Boice, Joseph G Schaefer, Brian J Cascarino, Charles C Stein
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Patent number: 7072901Abstract: An index generator that generates an index, which is data description contents, such as video contents, comprises: an index description device, for defining in advance basic index information concerning an index; a video display device for the input, the display or the output of contents to which an index is to be added; a triggering action input device, for accepting a triggering action in the contents that is displayed or output; and an index determination device, for generating index data based on the basic index information, which is defined by the index description device, and triggering action input history information, which is entered by the triggering action input device.Type: GrantFiled: January 23, 2002Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Masayoshi Teraguchi, Tomio Echigo, Takaaki Murao, Ken Masumitsu
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Patent number: 7072837Abstract: In a speech recognition session, a method of speech processing utilizing a plurality of grammars can include a series of steps. The method can include spawning a separate thread of execution corresponding to each one of a plurality grammars and allocating a post-processing recognition task to each separate thread of execution. Each post-processing recognition task can produce a possible recognition result using the corresponding grammar. A possible recognition result produced by one of the post-processing recognition tasks can be identified.Type: GrantFiled: March 16, 2001Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Kimberlee A. Kemble, James R. Lewis, Vanessa V. Michelini, Margarita Zabolotskaya
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Patent number: 7071532Abstract: An adjustable self aligned low capacitance integrated circuit air gap structure comprises a first interconnect adjacent a second interconnect on an interconnect level, spacers formed along adjacent sides of the first and second interconnects, and an air gap formed between the first and second interconnects. The air gap extends above an upper surface of at least one of the first and second interconnects and below a lower surface of at least one of the first and second interconnects, and the distance between the spacers defines the width of the air gap. The air gap is self-aligned to the adjacent sides of the first and second interconnects.Type: GrantFiled: September 30, 2003Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Robert M. Geffken, William T. Motsiff
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Patent number: 7073062Abstract: In response to initiating a call from a first class to a second class, an instantiation of the second class is initiated. While performing the instantiation of the second class, a class constructor for the second class is called, which determines a codebase for the first class and attempts to verify a digital signature on it. In response to a successful verification, the instantiation of the second class is successfully completed. In response to successfully completing the instantiation of the second class, a codebase for the second class is determined by the first class, and an attempt is made by the first class to verify a digital signature on the codebase for the second class. In response to a successful verification of the digital signature on the codebase for the second class, the call from the instance of the first class to the instance of the second class is performed.Type: GrantFiled: December 19, 2000Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Lok Yan Leung, Anthony Joseph Nadalin, Bruce Arland Rich, Thoedore Jack London Shrader
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Patent number: 7072994Abstract: Provided are a method, system, and program for configuring device addresses used by a source device to communicate with at least one target device. A determination is made of a number of device addresses supported by a target device and an identifier of the source device. The determined identifier and the number of device addresses supported by the target device are used to determine device addresses from the device addresses supported by the target device to communicate with the target device.Type: GrantFiled: March 12, 2002Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventor: Thomas George Britton
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Patent number: 7073145Abstract: A method for signal balancing across multiple random logic macros. The method inserts a programmable delay element into the design before the last buffer level on all signal paths. The random logic macro is then fully designed including cell placement and wiring. With programmable delay buffers in place, the random logic macros may be used within multiple designs, each having varying signal latency requirements.Type: GrantFiled: January 7, 2003Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Thomas W. Fry, Daniel R. Menard, Phillip Paul Normand
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Patent number: 7071047Abstract: Semiconductor structures and method of forming semiconductor structures. The semiconductor structures including nano-structures or fabricated using nano-structures. The method of forming semiconductor structures including generating nano-structures using a nano-mask and performing additional semiconductor processing steps using the nano-structures generated.Type: GrantFiled: January 28, 2005Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, Charles W. Koburger, III
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Patent number: 7070909Abstract: The glass transmittance of UV light having a wavelength of 365 nanometers is reduced by compounding an oxide or salt of at least one of Fe, Cu, Cr, Ce, Mn and mixtures thereof. The fiberglass cloth can be used for providing reinforced prepregs used in producing printed circuit boards or laminated chip carrier substrates.Type: GrantFiled: August 30, 2004Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Robert M. Japp, Pamela Lulkoski, Jeffrey McKeveny, Jan Obrzut, Kenneth Lynn Potter
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Patent number: 7071934Abstract: A technique, system, and computer program for quickly and efficiently navigating through a comparison of different versions of a file. An abstract representation of the detected differences is provided in a separate navigation window or pane. This abstract representation is shown as one or more bars, which are formatted using one color for segments that are the same and a different color for those segments that are different. This allows the user to see, at a high level, the relative size of differences, the relative position of the differences, and how the differences are distributed throughout the files. The user can navigate through the differences using navigation controls that are synchronized between the navigation window (or pane) and a file comparison window. A novel use of hover help is defined. The navigation window and controls can be used with comparisons of any type of ordered data, such as text, audio, video, etc., and with comparisons of any number of versions of a file.Type: GrantFiled: March 20, 1998Date of Patent: July 4, 2006Assignee: International Business Machines Corp.Inventors: Michael Anthony Faoro, Lynn Cleveland Percival, III
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Patent number: 7073043Abstract: Disclosed is a symmetric multiprocessor data processing system (SMP) that implements a TLBI protocol, which enables multiple TLBI operations from multiple processors within a partition to complete concurrently. Thus, a global TLB lock, synchronization, and TLB unlock is not necessary. When a TLBI instruction is executed, the master dynamically manages the behavior of the TLBI operation based on asynchronously snooping another TLBI. If concurrent TLBI management is required, then the master dynamically degrades the TLBI to a “barrier” class instruction.Type: GrantFiled: April 28, 2003Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Ravi Kumar Arimilli, Guy Lynn Guthrie, Kirk Samuel Livingston
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Patent number: 7072939Abstract: A system and method for providing dynamically shared documents to multiple computing devices. In a preferred embodiment, the system includes a hub and a plurality of computing devices in physical proximity with the hub. Each of the plurality of computing devices communicates with the hub via a wireless connection. The hub acts as a pass-through device receiving and transmitting requests from a requesting computing device to other computing devices and receiving and transmitting answers from the other computing devices to the requesting computing device. Each computing device translates requests and shared documents into a system independent language before transmitting the request of the document to the hub and each computing device translates received documents from the system independent language into a data format preferred by that particular computing device.Type: GrantFiled: January 27, 2000Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Hatim Yousef Amro, Elizabeth Silvia
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Patent number: 7071757Abstract: A differential sinusoidal signal pair is generated on an integrated circuit (IC). The differential sinusoidal signal pair is distributed to clock receiver circuits, which may be differential amplifiers. The clock receiver circuits receive the differential sinusoidal signal pair and convert the differential sinusoidal pair to local clock signals. Power consumption and noise generation are reduced as compared to conventional clock signal distribution arrangements.Type: GrantFiled: September 6, 2001Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Anthony Richard Bonaccio, John Maxwell Cohn, Alvar Antonio Dean, Amir H. Farrahi, David J. Hathaway, Sebastian Theodore Ventrone
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Patent number: 7073181Abstract: The invention is a system and method for sharing secure sockets layer (SSL) sessions across multiple processes, comprising: at least one SSL wrapper receiving a request for a shared SSL session from an application program; an SSL daemon process receiving at least one request for a shared SSL session from an SSL wrapper; the SSL daemon calling at least one SSL session; the SSL daemon receiving at least one return code from at least one called SSL session; at least one SSL wrapper receiving at least one return code from the SSL daemon; and at least one SSL wrapper passing a return code to the return code's requesting application.Type: GrantFiled: November 13, 2001Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventor: Mark R. Gambino
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Patent number: 7073139Abstract: A method for determining contact location for embedded dynamic random access memory (eDRAM) formed in a silicon-on-insulator (SOI) substrate includes reviewing contact design data for an eDRAM device and discarding contact locations corresponding to contact shapes within a support area of the eDRAM device. Contact locations corresponding to bitline contacts to storage cells within the eDRAM device are saved and outputted to a custom design level to be used in forming body contacts for the eDRAM formed in the SOI substrate.Type: GrantFiled: June 3, 2003Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Karen A. Bard, Herbert L. Ho
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Patent number: 7073100Abstract: A method and system for testing an embedded DRAM that includes DRAM blocks. The method including: generating a test data pattern in a processor based BIST system, for each DRAM block, performing a write of the test data pattern into the DRAM block, performing a pause for a predetermined period of time, and performing a read of a resulting data pattern from the DRAM block; where for each DRAM block, the write of the test data pattern into the DRAM block is performed before the pause, and the read of the resulting data pattern from each DRAM block is performed after the pause; where at least a portion of the pause of two or more of the DRAM blocks overlap in time; and for each DRAM block comparing the test data pattern to the resulting data pattern.Type: GrantFiled: November 11, 2002Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Laura S. Chadwick, William R. Corbin, Jeffrey H. Dreibelbis, Erik A. Nelson, Thomas E. Obremski, Toshiharu Saitoh, Donald L. Wheater
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Patent number: 7072827Abstract: A method for morphological disambiguation includes receiving an input string and morphologically analyzing the string to generate a list of candidate analyses of the string, each candidate analysis including a respective word and a linguistic pattern of the word. The pattern of each of the analyses is evaluated against a predefined criterion in order to select one or more of the analyses from the list. The method is suitable particularly for computerized analysis and searching in Hebrew and other Semitic languages.Type: GrantFiled: June 29, 2000Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: David Carmel, Yoelle Maarek-Smadja, Victoria Skoblikov
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Patent number: 7072344Abstract: A packet network redistributes excess bandwidth for voice and data sessions applying a Quality of Service (QoS) algorithm. The network includes interacting client stations using H.323 protocol managing bit rate according to an algorithm as voice and data sessions are added or removed from the network. The client stations include codecs coupled to the network. The codecs provide voice sessions at a minimum bandwidth using a voice codec bit rate and preferred bandwidth using another voice codec bit rate. A first algorithm applies the QoS algorithm allocating bandwidth between interacting client stations after the addition of a new voice or data session when there is insufficient bandwidth for the new session to receive preferred bandwidth. A second algorithm is applied when a voice or data session is removed from the interacting client stations. If any session is allocated minimum bandwidth the QoS increases a voice session at minimum bandwidth to preferred bandwidth if excess bandwidth is available.Type: GrantFiled: July 16, 2001Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Youssef Abdelilah, Gordon Taylor Davis, Jeffrey Haskell Derby, Dongming Hwang, Clark Debs Jeffries, Malcolm Scott Ware, Hua Ye
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Patent number: 7071103Abstract: The present invention provides a method for retarding the diffusion of dopants from a first material layer (typically a semiconductor) into an overlayer or vice versa. In the method of the present invention, diffusion of dopants from the first semiconductor into the overlayer or vice versa is retarded by forming a monolayer comprising carbon and oxygen between the two layers. The monolayer is formed in the present invention utilizing a chemical pretreatment process in which a solution including iodine and an alcohol such as methanol is employed.Type: GrantFiled: July 30, 2004Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Huajie Chen, Michael A. Gribelyuk, Judson R. Holt, Woo-Hyeong Lee, Ryan M. Mitchell, Renee T. Mo, Dan M. Mocuta, Werner A. Rausch, Paul A. Ronsheim, Henry K. Utomo
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Patent number: 7072894Abstract: In a cluster of computing nodes having shared access to one or more file systems in data storage using parallel file system software, a method for managing the data storage includes initiating a session of a data management application on a first one of the nodes, while running a user application on a second one of the nodes. A request is submitted to the parallel file system software by the user application on the second node to mount one of the file systems in the data storage. A mount event message is sent from the second node to the first node responsive to the request, for processing by the data management application on the first node. When the file system is to be unmounted, preunmount and unmount events are sent for processing by the data management application on the first node.Type: GrantFiled: June 25, 2001Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Irit Loy, John Marberg, Boaz Shumeli, Zvi Yehudai, Robert Curran, Roger Haskin, Frank Schmuck, James Wyllie
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Patent number: 7071559Abstract: A semiconductor structure comprising a substrate including a first layer comprising a first material having a first modulus of elasticity; a first structure comprising a conductor and formed within the substrate, the first structure having an upper surface; and a stress diverting structure proximate the first structure and within the first layer, the stress diverting structure providing a low mechanical stress region at the upper surface of the first structure when a physical load is applied to the first structure, wherein said low mechanical stress region comprises stress values below the stress values in areas not protected by the stress diverting structure. The stress diverting structure comprises a second material having a second modulus of elasticity less than the first modulus of elasticity, the second material selectively formed over the upper surface of the first structure for diverting mechanical stress created by the physical load applied to the first structure.Type: GrantFiled: July 16, 2004Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Elie Awad, Mariette A. Awad, Kai D. Feng
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Remote administration and monitoring of a service component in a service logic execution environment
Patent number: 7072957Abstract: A method of directly administering a service component through a hypermedia document can include a series of steps. The hypermedia document can provide an interface to a service logic execution environment (SLEE). At least one administrative option embodied in the hypermedia document can be provided. The at least one administrative option can correspond to a function to be performed by the service component. A user specified administrative option can be received in the hypermedia document and a SLEE compatible event can be generated based on the user specified administrative option. The event can be a type which the service component has been registered in the SLEE to receive. Also, the event can be routed to the service component via the SLEE. The service component can process the event and perform an administrative function consistent with the event.Type: GrantFiled: May 31, 2001Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Thomas E Creamer, Zygmunt A Lozinski, Victor S Moore, Glen R Walters -
Patent number: 7073144Abstract: A method of assessing the stability of a placement tool used in designing the physical layout of an integrated circuit chip, by constructing different layouts of cells using the placement tool with different sets of input parameters, and calculating a stability value based on the movement of respective cell locations between the layouts. The stability value can be normalized based on cell locations in a random placement. One stability metric measures absolute movement of individual cells in the layouts, weighted by cell area. The cell movements can be squared in calculating the stability value. Another stability metric measures the relative movement of cells with respect to their nets. Shifting of cells and symmetric reversal of cells about a net center does not contribute to this relative movement, but spreading of cells and rotation of cells with respect to the net center does contribute to the relative movement. Relative cell movements can again be squared in calculating the stability value.Type: GrantFiled: April 15, 2004Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Charles Jay Alpert, Gi-Joon Nam, Paul Gerard Villarrubia, Mehmet Can Yildiz
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Patent number: 7072915Abstract: A copy method is disclosed to provide a duplicate copy of source data where the duplicate copy is consistent with the source data as of a designated time. The method includes creating a copy-on-write relationship between specified source data and an original image cache, utilizing an application outboard of the designated host application to copy all items of source data and their associated locations to a secondary data object without regard to whether the items source data have been updated since creating the copy-on-write relationship, and copying a specified amount of contents of the original image cache to the secondary data object. The specified amount includes contents of the original image cache as of completion of the utilizing operation. In addition, the method includes permitting copy-on-write relationship to continue during the utilizing operation and during at least part of the copying operation.Type: GrantFiled: January 22, 2002Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Michael Allen Kaczmarski, Donald Paul Warren, Jr.
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Patent number: 7073027Abstract: Controlling a cache of distributed data is provided by dynamically determining whether and/or where to cache the distributed data based on characteristics of the data, characteristics of the source of the data and characteristics of the cache so as to provide an indication of whether to cache the data. The data may be selectively cached based on the indication.Type: GrantFiled: July 11, 2003Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Gennaro A. Cuomo, Brian K. Martin
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Patent number: 7070085Abstract: An improved water soluble protective paste and a method for protecting metal circuits and pads on the surface of an electronic board during the manufacturing steps. A densifier is added to the paste making it easier and more efficient the dispensing of the paste. After deposition the layer is dried until a solid protective film is obtained. An additional advantage obtained by the present invention is that the protective layer can be deposited also by means of an offset printing process, avoiding the use of the stencil and of the screening steps. Screening process is a labourious operation which requires very sophisticated equipment and a very high precision in the design of the stencil. Because of these requirements, screening is an expensive process. On the other hand offset printing is a very simple, cheap and reliable method. In addition, the film forming properties allow the material to create a protective film even with a thin deposited film.Type: GrantFiled: January 7, 2004Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventor: Stefano Oggioni
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Patent number: 7073105Abstract: An array built-in, on-chip self test system for testing a memory array and a method of testing the memory array. The memory array has data input ports, data output ports, and address ports, and a data control subsystem, an address control subsystem, and a comparator. The data control subsystem generates and applies deterministic data patterns to the data input ports of the memory array. The address control subsystem generates addresses for application to the memory array in coordination with said data control subsystem, and includes a sequence counter, a count rate controller for the sequence controller, a count rate controller divider to control the number of cycles per address, an address controller to provide granular control of addresses, and an X-OR gate receiving an input from a sequence counter and from the address controller, the X-OR gate outputting an address bit to the memory array.Type: GrantFiled: April 14, 2003Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Thomas J. Knips, James W. Dawson, John D. Davis, Douglas J. Malone
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Patent number: 7073002Abstract: A resource and partition manager of the preferred embodiments includes a lock mechanism that operates on a plurality of locks that control access to individual hardware resources. The resource and partition manager uses the lock mechanism to obtain a lock on a hardware resource when transferring control of the hardware resource to a logical partition that is powering on and when removing the hardware resource from a logical partition that is powering off. The resource and partition manager uses the lock mechanism to remove control of a hardware resource from, or return control to, an operating logical partition in order to facilitate hardware service operations on that hardware resource or on the physical enclosure in which it is contained.Type: GrantFiled: March 13, 2003Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Troy David Armstrong, William Joseph Armstrong, Curtis Shannon Eide, Gregory Michael Nordstrom
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Patent number: 7073022Abstract: The present invention describes a method and system for interfacing a plurality of device controllers to an array of data storage devices by serial connection. The device controllers are coupled to a serial interface by a bus and the devices of the storage array are coupled to the serial interface by a serial connection. The serial interface receives controller signals through the bus and multiplexes the signals onto the serial connections of the storage array. Arbitration between the various device controllers seeking access to the storage array is resolved through bus protocol and through drive based reserve/release registers in the serial interface processor.Type: GrantFiled: May 23, 2002Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Mohamad H. El-Batal, Yoshihiro Fujie, Thomas Sing-Klat Liong, Krishnakumar Rao Surugucchi
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Patent number: 7071031Abstract: A vertically integrated structure includes a micro-electromechanical system (MEMS) and a chip for delivering signals to the MEMS. The structure includes a metal stud connecting a surface of the chip and the MEMS; the MEMS has an anchor portion having a conducting pad on an underside thereof contacting the metal stud. The MEMS is spaced from the chip by a distance corresponding to a height of the metal stud, and the MEMS includes a doped region in contact with the conducting pad. In particular, the MEMS may include a cantilever structure, with the end portion including a tip extending in the vertical direction. A support structure (e.g. of polyimide) may surround the metal stud and contact both the underside of the MEMS and the surface of the chip. A temporary carrier plate is used to facilitate handling of the MEMS and alignment to the chip.Type: GrantFiled: May 28, 2003Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: H. Bernhard Pogge, Michel Despont, Ute Drechsler, Peter Vettiger, Roy Yu
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Patent number: 7071097Abstract: Interconnect dual damascene structure are fabricated by depositing on a layer of at least one dielectric, a mask forming layer for providing the via-level mask layer of the dual damascene structures; creating an elongated via pattern in the via-level mask layer; depositing a layer of line-level dielectric and creating a line pattern through the layer of line-level dielectric, and transferring the line pattern through the projected intersection of the elongated via-level pattern and of the line-level pattern thereby generating an aligned dual damascene structure. A conductive liner layer is deposited in the dual damascene structure followed by filling the dual damascene structure with a conductive fill metal to form a set of metal lines. The metal and liner layers are planarized.Type: GrantFiled: July 9, 2004Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventor: Matthew E. Colburn
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Patent number: 7071720Abstract: An apparatus adapted for use in a field replacement unit that is to be coupled to an electronic module. Included in the apparatus are a cover assembly; a biasing assembly disposed within the cover assembly; and, an aligning and coupling mechanism retained in the cover assembly in juxtaposed relation with the biasing assembly for mounting an interposer assembly in a manner, whereby the interposer assembly is generally self-aligned along in-plane axes with respect to the cover assembly for subsequent coupling to an electronic module. A method for use of the apparatus is disclosed.Type: GrantFiled: June 10, 2004Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: John Lee Colbert, Roger Duane Hamilton, Arvind Kumar Sinha
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Patent number: 7073106Abstract: A method, computer program product and system for testing stuck-at-faults. A first register may be loaded with a first value where the first value may be written into each entry in a memory array. A second register may be loaded with a second value. A third register may be loaded with either the second value or a third value. The second and third values are pre-selected to test selector circuits for stuck-at-faults with a pattern where the pattern includes a set of bits to be inputted to selector circuits and a set of bits to be stored in the memory cells. A value stored in the n-most significant bits in both the second and third registers may be predecoded to produce a predecode value. The predecode value may be compared with the value stored in the n-most significant bits in an entry in the memory array to determine a stuck-at-fault.Type: GrantFiled: March 19, 2003Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Jose A. Paredes, Philip G. Shephard, III, Timothy M. Skergan, Neil R. Vanderschaaf