IBM Patents

The International Business Machines Corporation provides IT infrastructure and services to enterprise customers.

IBM Patents by Type
  • IBM Patents Granted: IBM patents that have been granted by the United States Patent and Trademark Office (USPTO).
  • IBM Patent Applications: IBM patent applications that are pending before the United States Patent and Trademark Office (USPTO).
  • Patent number: 5635847
    Abstract: According to the present invention an improved device and method for testing the integrity of electrical connectors on a substrate and/or for providing for burn-in of a semi-conductor on a substrate is provided. The test unit includes a mounting fixture having a plurality of pins carried thereon preferably spring loaded. At least some of the pins are provided with a plurality of circumferentially spaced conducting members which are electrically insulated from each other. These pins are configured and mounted on the fixture to move into and out of engagement with a portion at least two and preferably four adjacent connectors on the substrate thereby allowing a single pin to contact up to four or more contacts on the substrate.
    Type: Grant
    Filed: May 15, 1995
    Date of Patent: June 3, 1997
    Assignee: International Business Machines Corporation
    Inventor: Victor P. Seidel
  • Patent number: 5636258
    Abstract: A non-contact in-situ temperature measurement apparatus for a single crystal substrate such as a semiconductor wafer using X-ray diffraction. Utilizing the Bragg condition for X-ray diffraction, the lattice constant of the semiconductor substrate can be determined either by measuring the diffraction angle for a monochromatic X-ray (monochromatic approach) or by measuring the wavelength of an X-ray diffracted with a certain scattering angle (polychromatic approach). The lattice constant, as a well-known function of temperature, is finally converted into the temperature of the semiconductor substrate.
    Type: Grant
    Filed: October 24, 1995
    Date of Patent: June 3, 1997
    Assignees: Siemens Aktiengesellschaft, International Business Machines Corporation, Kabushiki Kaisha Toshiba
    Inventors: Katsuya Okumura, James G. Ryan, Gregory B. Stephenson, Hans-Joerg Timme
  • Patent number: 5634973
    Abstract: Epitaxial and polycrystalline layers of silicon and silicon-germanium alloys are selectively grown on a semiconductor substrate or wafer by forming over the wafer a thin film masking layer of an oxide of an element selected from scandium, yttrium, lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium; and then growing the epitaxial layer over the wafer at temperatures below 650.degree. C. The epitaxial and polycrystalline layers do not grow on the masking layer. The invention overcomes the problem of forming epitaxial layers at temperatures above 650.degree. C. by providing a lower temperature process.
    Type: Grant
    Filed: January 16, 1996
    Date of Patent: June 3, 1997
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Kevin K. Chan, Jack O. Chu, James M. E. Harper
  • Patent number: 5635285
    Abstract: A method of exposing a radiation-sensitive medium through a mask and using an imaging system having a given depth of focus to control for pattern dependent distortion. The steps comprise: providing the radiation-sensitive medium within the depth of focus of the imaging system; providing radiation to the radiation-sensitive medium through the mask; providing the radiation-sensitive medium fully outside the depth of focus of the imaging system; and providing radiation to the radiation-sensitive medium through the mask. Corrections are automatically made by providing the radiation-sensitive medium fully outside the depth of focus of the imaging system, since in that regime the mask operates as a grey-scale mask, with the amount of light passing through any region of the mask dependent on the transmission of the masking pattern in that region.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: June 3, 1997
    Assignee: International Business Machines Corporation
    Inventors: Paul E. Bakeman, Jr., Albert S. Bergendahl
  • Patent number: 5636102
    Abstract: A portable information processing apparatus which has a main body having front and rear edge, and a lid pivotally attached to said rear edge of said main body, The lid has an LCD unit having a liquid crystal and a light conducting plate for guiding light through the LCDI to the front surface of the LCD unit, and a cover that extends over the rear face of the LCD unit. A thinner portion is provided at one edge of the light conducting plate than the opposite edge, with the thinner portion being positioned close to the rear edge of the main body. A hinge pivotally attaching the lid to the main body at the rear edge portion has a torque plate wound around a shaft of the hinge to support the lid and is mounted in a space defined by the cover and the thinner portion of the light conducting plate.
    Type: Grant
    Filed: July 31, 1996
    Date of Patent: June 3, 1997
    Assignee: International Business Machines Corporation
    Inventors: Takane Fujino, Yoshifumi Natsuyama, Yoshiharu Uchiyama, Tomoyuki Takahashi
  • Patent number: 5636156
    Abstract: An adder circuit is disclosed having an improved carry lookahead arrangement. The number of carry lookahead stages required is log n, where n is equal to the number of bits in the adder. This arrangement has fanout limit based on the number of sets of propagate and generate signals which can be combined at each bit location of each stage. For example, if two-way merge circuits are used to combine two sets of signals together, then the maximum fanout from the previous stage would be limited to two (2). If four-way merge circuits were used, then the fanout would be limited to four (4). This low fanout is achieved without increasing the number of stages by overlapping the groups that are combined in each step.
    Type: Grant
    Filed: October 15, 1996
    Date of Patent: June 3, 1997
    Assignee: International Business Machines Corporation
    Inventors: Donald G. Mikan, Jr., Martin S. Schmookler
  • Patent number: 5635419
    Abstract: The invention provides a capacitor structure utilizing porous silicon as a first plate of the capacitor structure, thereby greatly increasing the surface area available for the capacitor and thereby the capacitance attainable. The invention also provides a trench structure having a porous silicon region surrounding the sidewalls thereof. Such a trench can then be utilized to form a capacitor according to the subject invention. Methods of producing the capacitor and trench structures according to the subject invention are also provided. Porous silicon is produced utilizing electrolytic anodic etching.
    Type: Grant
    Filed: May 4, 1995
    Date of Patent: June 3, 1997
    Assignee: International Business Machines Corporation
    Inventors: Peter J. Geiss, Donald M. Kenney
  • Patent number: 5636359
    Abstract: A system and method for reducing device wait time in response to a host initiated write operation modifying a data block. The system includes a host computer channel connected to a storage controller which has cache memory and a nonvolatile storage buffer in a first embodiment. An identical system makes up the second embodiment with the exception that there is no nonvolatile storage buffer in the storage controller of the second embodiment. The controller in either embodiment is coupled to a cache storage drawer containing a plurality of DASD devices for implementing a RAID parity data protection scheme, and for permanently storing data. The drawer has nonvolatile cache memory which is used for accepting data destaged from controller cache. In a first embodiment, no commit reply is sent to the controller to indicate that data has been written to DASD. Instead a status information block is created to indicate that the data has been destaged from controller cache but is not committed.
    Type: Grant
    Filed: June 20, 1994
    Date of Patent: June 3, 1997
    Assignee: International Business Machines Corporation
    Inventors: Brent C. Beardsley, Joel H. Cord, Joseph S. Hyde, II, Vernon J. Legvold, Carol S. Michod, Gary E. Morain, Chan Y. Ng, John R. Paveza, Lloyd R. Shipman, Jr.
  • Patent number: 5635849
    Abstract: Disclosed is a Probe Positioning Actuator which is low in cost and mass, capable of high accelerations, relatively long stroke and compact packaging, as well as high in efficiency. The actuator assembly comprises a frame, and at least one pair of spaced apart, laterally extending, conductor carrying, flexible beams attached to the frame. A non-magnetic armature, substantially U-shaped in cross section, is attached adjacent or approximate the extended terminal ends of the beams, and a probe is attached to the base of the "U" of the armature for contacting selected points in the electrical circuit associated with the device being tested. The heart of the actuator includes a coil mounted on the upstanding legs of the U-shaped armature and arranged so that the axis of the coil is perpendicular to the base of the armature but substantially parallel to the probe tip.
    Type: Grant
    Filed: May 6, 1996
    Date of Patent: June 3, 1997
    Assignee: International Business Machines Corporation
    Inventors: Jiann-Chang Lo, Michael Servedio, James M. Hammond, James E. Boyette, Jr., Hans-George H. Kolan
  • Patent number: 5635861
    Abstract: Disclosed is an improved push-pull off-chip driver circuit. The circuit includes a push-pull amplifier including a pull-up transistor and a pull-down transistor, each provided with independent inputs and connected at the output node. The input to the pull-up transistor is provided by a transmission gate having an n-channel transistor connected in parallel with a p-channel transistor. A control transistor is coupled between the output node and the gate of the pull-up transistor to provide a protective bias. A feedback override circuit is coupled between the output node and the gate of the p-channel transmission gate transistor to selectively provide either Vout or a low level potential to that gate. The feedback override circuit improves the response time and noise immunity of a prior art off-chip driver in the active mode in a manner consistent with the objectives of protecting the gate oxides from high voltage stress and prevent leakage currents during the high-impedance mode.
    Type: Grant
    Filed: June 27, 1996
    Date of Patent: June 3, 1997
    Assignee: International Business Machines Corporation
    Inventors: Francis Chan, Bijit T. Patel
  • Patent number: 5636131
    Abstract: An apparatus implemented in a computer aided design (CAD) system automatically generates phase shifted mask designs for very large scale integrated (VLSI) chips from existing circuit design data. The system uses a series of basic geometric operations to design areas requiring phase assignment, resolve conflicting phase assignments, and eliminate unwanted phase edges. This apparatus allows automatic generation of phase shift mask data from any circuit design that allows for phase shifting. Since the dimensional input for all geometric operations is directly linked to the design ground rules given to the circuit designers, any designable circuit layout can also be phase shifted with this algorithm. The autogeneration of phase shift patterns around an existing circuit design is broken down into four major tasks: 1. Define areas that need a phase assignment; 2. Make a first pass phase assignment unique to each critical feature and define "runs" of interrelated critical features; 3.
    Type: Grant
    Filed: May 12, 1995
    Date of Patent: June 3, 1997
    Assignee: International Business Machines Corporation
    Inventors: Lars W. Liebmann, Mark A. Lavin, Pia N. Sanda
  • Patent number: 5636291
    Abstract: A computer-based system and method for recognizing handwriting. The present invention includes a pre-processor, a front end, and a modeling component. The present invention operates as follows. First, the present invention identifies the lexemes for all characters of interest. Second, the present invention performs a training phase in order to generate a hidden Markov model for each of the lexemes. Third, the present invention performs a decoding phase to recognize handwritten text. Hidden Markov models for lexemes are produced during the training phase. The present invention performs the decoding phase as follows. The present invention receives test characters to be decoded (that is, to be recognized). The present invention generates sequences of feature vectors for the test characters by mapping in chirographic space. For each of the test characters, the present invention computes probabilities that the test character can be generated by the hidden Markov models.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: June 3, 1997
    Assignee: International Business Machines Corporation
    Inventors: Eveline J. Bellegarda, Jerome R. Bellegarda, David Nahamoo, Krishna S. Nathan
  • Patent number: 5635000
    Abstract: The present invention relates generally to a new apparatus and method for screening using electrostatic adhesion. More particularly, the invention encompasses an apparatus that uses an electrostatic charge during the screening process for a semiconductor substrate. Basically, a backing layer is adhered to a green ceramic sheet using an electrostatic charge, while the green ceramic sheet is processed.
    Type: Grant
    Filed: December 22, 1995
    Date of Patent: June 3, 1997
    Assignee: International Business Machines Corporation
    Inventors: Jon A. Casey, Cynthia J. Calli, Darren T. Cook, David B. Goland, John U. Knickerbocker, Mark J. LaPlante, David C. Long, Daniel S. Mackin, Kathleen M. McGuire, Keith C. O'Neil, Kevin M. Prettyman, Michael T. Puchalski, Joseph C. Saltarelli, Candace A. Sullivan
  • Patent number: 5636352
    Abstract: A method and apparatus for executing a condensed instruction stream by a processor including receiving an instruction including an instruction identifier and multiple of instruction synonyms within the instruction, generating at least one full width instruction for each instruction synonym, and executing by the processor the generated full width instructions.
    Type: Grant
    Filed: December 16, 1994
    Date of Patent: June 3, 1997
    Assignee: International Business Machines Corporation
    Inventors: Richard Bealkowski, Michael R. Turner
  • Patent number: 5636086
    Abstract: An air bearing slider for use in carrying a transducer adjacent a recording medium exhibits reduced sensitivity to variations in roll, crown, and skew. In one embodiment, the slider comprises an air bearing slider having a pair of substantially coplanar side rails disposed along the sides of the air bearing surface so as to form a recessed section between the side rails. The recessed section is open at both the leading and trailing ends of the slider while each side rail has a tapered section or etched step at the leading edge of the slider. One rail carries the transducer and extends for the entire length of the slider body. The rail without a transducer extends from the leading edge toward the trailing edge, but does not extend all the way to the trailing edge. Under some skew, accessing, and crash stop impact conditions, the resulting slider roll causes the flying height of the inactive rail to drop.
    Type: Grant
    Filed: October 3, 1995
    Date of Patent: June 3, 1997
    Assignee: International Business Machines Corporation
    Inventors: Sanford A. Bolasna, Devendra S. Chhabra, Sridhar Gopalakrishna
  • Patent number: 5636370
    Abstract: A conversion cache circuit, interfacing RISC busses to CISC peripheral circuits, provides master/slave Write and Read operations in a shared memory (130) and in the internal registers of the processor of said peripheral circuits (210). It enables RISC processor to Write and Read in the internal registers of the 8-bit processor in a salve operation while the 32-bit processor may perform the Write or Read operations to the shared memory through the conversion cache circuit in a master mode. The 32-bit processor may have access directly to the memory through its own direct access memory mechanism.
    Type: Grant
    Filed: May 30, 1995
    Date of Patent: June 3, 1997
    Assignee: International Business Machines Corporation
    Inventors: Patrick Sicsic, Alain Benayoun, Jean-Francois LePennec, Patrick Michel
  • Patent number: 5636364
    Abstract: In a cache-to-memory interface, a means and method for timesharing a single bus to allow the concurrent processing of multiple misses. The multiplicity of misses can arise from a single processor if that processor has a nonblocking cache and/or does speculative prefetching, or it can arise from a multiplicity of processors in a shared-bus configuration.
    Type: Grant
    Filed: December 1, 1994
    Date of Patent: June 3, 1997
    Assignee: International Business Machines Corporation
    Inventors: Philip G. Emma, Joshua W. Knight, III, Thomas R. Puzak
  • Patent number: 5635693
    Abstract: A radio frequency (RF) tagging system is used to monitor vehicles passing through an area access to one or more vehicle storage area(s). One or more of the vehicles stored in the storage area is equipped with a RF tag which has vehicle ID information about the vehicle stored in a tag memory contained on the tag. The tag communicates with a base station when passing through the area accesses, (entering or leaving). A central and preferably one or more remote computers accesses status information that might include vehicle identification, customer, lot identification, time of day, and vehicle and lot status. The information is used in security or marketing functions. The security function can include a paging system for sending alarms and/or messages to a manager or security personnel. The marketing function can include determining how long or how many times different makes an model of vehicle are chosen by customers for test drives.
    Type: Grant
    Filed: February 2, 1995
    Date of Patent: June 3, 1997
    Assignee: International Business Machines Corporation
    Inventors: Steven J. Benson, Thomas A. Cofino, Robert J. von Gutfeld
  • Patent number: 5636325
    Abstract: A set of intonation intervals for a chosen dialect are applied to the intonational contour of a phomene string derived from a single set of stored linguistic units, e.g., phonemes. Sets of intonational intervals are stored to simulate or recognize different dialects or languages from a single set of stored phonemes. The interval rules preferably use a prosodic analysis of the phoneme string or other cues to apply a given interval to the phoneme string. A second set of interval data is provided for semantic information. The speech system is based on the observation that each dialect and language possess its own set of musical relationships or intonation intervals. These musical relationships are used by a human listener to identify the particular dialect or language. The speech system may be either a speech synthesis or speech analysis tool or may be a combined speech synthesis/analysis system.
    Type: Grant
    Filed: January 5, 1994
    Date of Patent: June 3, 1997
    Assignee: International Business Machines Corporation
    Inventor: Peter W. Farrett
  • Patent number: 5635836
    Abstract: A positioning apparatus for performing coarse and fine positioning of samples for scanning such as by a scanning microscope system generally and a scanning SQUID microscope especially. The apparatus includes a connecting rod that pivots about a fixed point and a translation mechanism, such as an XYZ translation device, for manipulating one end of the rod to cause motion at the other end by way of the fixed pivot point. At the other end of the rod, a sample may be mounted such that the manipulating mechanism can move the rod in a plurality of directions so the sample can be scanned by a sensing device.
    Type: Grant
    Filed: October 21, 1994
    Date of Patent: June 3, 1997
    Assignee: International Business Machines Corporation
    Inventors: John R. Kirtley, Sarah H. Blanton, Mark B. Ketchen
  • Patent number: 5636361
    Abstract: A multi-processor information handling system employs multiple multi-processor bus/memory subsystem groups wherein the processors may operate programs concurrently, and concurrent memory operations may be performed with the multiple memory subsystems via the associated multi-processor buses responsive to address location directors. The invention expands the system bandwidth and improves overall multi-processor information handling system performance.
    Type: Grant
    Filed: December 22, 1994
    Date of Patent: June 3, 1997
    Assignee: International Business Machines Corporation
    Inventor: Donald Ingerman
  • Patent number: 5636090
    Abstract: A novel inertial actuator latch assembly adapted for use within the compact housing configuration of a very small form factor data storage system comprises an actuator latch and a separate latch spring. A portion of an inertia member of the actuator latch extends over a portion of a surface of the data storage disk and is separated therefrom by a clearance gap having a size typically on the order of tenths of a millimeter. A novel tilt limiting apparatus prevents deleterious contact between the inertia member and the sensitive surface of the data storage disk in response to a strong external rotational shock force being exerted on the data storage system housing. Automatic registration and coupling features provide for easy and efficient installation of the tilt limiting inertial actuator latch assembly in a top-down assembly process.
    Type: Grant
    Filed: October 17, 1994
    Date of Patent: June 3, 1997
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey F. Boigenzahn, Douglas W. Johnson, Richard E. Lagergren, James M. Rigotti
  • Patent number: 5634268
    Abstract: A structure and a method is disclosed for making a laminated circuit carrier card for the purpose of making a Direct Chip Attached Module (DCAM) with low cost and high reliability. The carrier is made using an organic or an inorganic laminated carrier having at least one surface available for direct chip mount. The chip has at least one solder ball with a cap of low melting point metal. The surface of the carrier has electrical features that are directly connected to the low melting point metal on the solder ball of the chip to form the eutectic and this way the chip is directly attached to the carrier.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: June 3, 1997
    Assignee: International Business Machines Corporation
    Inventors: Hormazdyar M. Dalal, Kenneth M. Fallon, Gene J. Gaudenzi
  • Patent number: 5636164
    Abstract: An apparatus for rapidly determining a control parameter t=t.sub.0 at which the sum S of n functions F.sub.i (i=1, . . . n) reaches a minimum, a maximum, or a given value, wherein each function F.sub.i (t) changes its first derivative only at given discrete values t.sub.ij of the control parameter t is described. The apparatus has a random access memory (RAM) addressed by the values t.sub.ij, a circuit for summing the second derivatives of the functions, a circuit to perform a double integration to evaluate S, and a comparator to determine the optimum control value; also disclosed is a new gate array (GA) which rapidly reproduces the addresses used to address the RAM while skipping all others. This gate array is advantageously used as a part of the apparatus for determining a control parameter. Further, the use of the devices in a communication network is described.
    Type: Grant
    Filed: May 23, 1995
    Date of Patent: June 3, 1997
    Assignee: International Business Machines Corporation
    Inventors: Harmen Van As, Hans Schindler, Wolfram Lemppenau
  • Patent number: 5635253
    Abstract: A replenishing solution for a cyanide-based electroless gold plating bath. The solution includes a gold(III) halide such as gold chloride, gold bromide, tetrachloroaurate (and its sodium, potassium, and ammonium salts), and tetrabromoaurate (and its sodium, potassium, and ammonium salts). The replenishing solution also may include an alkali (such as potassium hydroxide, sodium hydroxide, and ammonium hydroxide) to maintain the pH of the solution between 8 and 14. Also provided is a method of replenishing a cyanide-based electroless gold plating bath with the solution of the present invention.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: June 3, 1997
    Assignee: International Business Machines Corporation
    Inventors: Donald F. Canaperi, Rangarajan Jagannathan, Mahadevaiyer Krishnan
  • Patent number: 5635848
    Abstract: A digital and analog controller for controlling a high-speed probe actuator is disclosed. This method and system provide the probe actuator system with improved damping ratio and reduced impact force, so the throughput of the tester is increased with fast settling actuator armature. With this method and system, the steady-state probe force is less sensitive to the servo system, test probe and variation in the probing distance d. An electronic circuit, which consists of analog operational amplifiers, monostable multivibrators, and D flip-flops, is presented for low-cost applications.
    Type: Grant
    Filed: March 10, 1995
    Date of Patent: June 3, 1997
    Assignee: International Business Machines Corporation
    Inventors: James M. Hammond, James C. Mahlbacher, Kenneth G. Roessler, Michael Servedio, Li-Cheng R. Zai
  • Patent number: 5636372
    Abstract: A method of analyzing timing differences between arrival times of distinct signals propagating through a circuit comprising: (i) identifying a first beginning point for a first data path over which data arrival times are propagated to a data endpoint; (ii) identifying a second beginning point for a second data path to the data endpoint, and for a clock path to a clock endpoint, the endpoints constituting an endpoint pair; (iii) identifying at least one common point at which the second data path and the clock path diverge; (iv) propagating data arrival times to the data endpoint from the first and second beginning points, and tagging the data arrival times propagated along the second data path with one of the common points; (v) propagating clock arrival times to the clock endpoint from the second beginning point along the clock path, and tagging the clock arrival times with one of the common points, the data and clock arrival times constituting clock/data arrival time pairs at the endpoint pair; (vi) determini
    Type: Grant
    Filed: September 30, 1994
    Date of Patent: June 3, 1997
    Assignee: International Business Machines Corporation
    Inventors: David J. Hathaway, Janet P. Alvarez, Krishna P. Belkhale
  • Patent number: 5635719
    Abstract: An improved particle lens has an axis which is shifted to follow the central ray as it is deflected through the lens creating, in effect, a variable curvilinear optical axis for the lens. The variable curvilinear optical axis is created for the lens so that the axis varies proportionally to the magnitude of the beam deflection. The optical axis of the lens is shifted by applying a uniform field to the lens to cancel the first term of the radial field with a function that is dependent on the position along the z-axis. This function is the trajectory of the central ray of the electron beam.
    Type: Grant
    Filed: July 23, 1996
    Date of Patent: June 3, 1997
    Assignee: International Business Machines Corporation
    Inventor: Paul F. Petric
  • Patent number: 5635242
    Abstract: A method of maintaining an optimum pressure and purity level in a vessel having an inlet gas flow and an outlet gas flow during shutdown of the vessel that prevents imploding of the vessel when the inlet and outlet gas flows are discontinued. Gas from the vessel is directed to a containment portion in communication with the vessel. The pressure of the gas in the containment portion is monitored; the containment portion is backfilled with a purified inert gas when the monitored pressure drops to a predetermined lower level; and the containment portion is vented when the monitored pressure rises to a predetermined higher level. Apparatus for maintaining an optimum pressure and purity level in a vessel having an inlet gas flow and an outlet gas flow during shutdown of the vessel that prevents imploding of the vessel when the inlet and outlet gas flows are discontinued is also provided.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: June 3, 1997
    Assignee: International Business Machines Corporation
    Inventors: Paul D. Agnello, Thomas O. Sedgwick
  • Patent number: 5634729
    Abstract: A point of sale printer includes a magnetic reader for processing transactions and payment by check at a checkout point of a retail establishment. The printer includes a magnetic or MICR reader located at a predetermined point on the printer's document travel path and a print head located at the same point on the document travel path but laterally offset from the MICR reader to allow the printer to print customer receipts and a journal as well as reading MICR information from checks and endorsing the check after it is cleared. A pressure pad is used with the magnetic read head of the MICR reader which utilizes a pressure film which flexes when a document is inserted between the magnetic read head and the pressure film to provide a spring loading force on the magnetic read head while still allowing the document to be moved smoothly past the magnetic read head.
    Type: Grant
    Filed: March 29, 1996
    Date of Patent: June 3, 1997
    Assignee: International Business Machines Corporation
    Inventors: Michael J. Kinney, Robert W. Kruppa, Robert A. Myers
  • Patent number: 5636144
    Abstract: An apparatus and method for quantitatively ranking the performance of each attribute contributing to a manufacturing process. Various signals representing the measure (i.e., quality or yield) of a manufacturing run and representing the attributes that contributed to each manufacturing run are recorded. An iterative process is commenced whereby numeric weights are assigned to each attribute. In a first iterative step, the weight of each attribute is determined to be the weighted average of the measure of each manufacturing run to which that attribute contributed. In subsequent iteration steps, a refined weight for each attribute is determined by computing the ratio between the normalized measure and the product of all other weights associated with that manufacturing run. The iterations are continued until the weights determined for each attribute converge or become self consistent.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: June 3, 1997
    Assignee: International Business Machines Corporation
    Inventors: Jerome M. Kurtzberg, Menachem Levanoni
  • Patent number: 5635869
    Abstract: A constant-current generator circuit includes an output circuit and a control circuit, with the control circuit producing a control voltage to define a reference current through the output circuit. An important feature is that the control circuit uses a pair of transistors having different threshold voltages in generating the control voltage. The circuit is formed using CMOS technology, and the difference in threshold voltage may be produced by doping the polysilicon gate of an N-channel or P-channel field effect transistor. The step of doping to produce the change in threshold voltage is compatible with the standard processing for the CMOS device. In a preferred embodiment, the control circuit uses two pairs of control transistors, each pair having differing thresholds. One pair is P-channel and the other N-channel. These pairs are in parallel, the P-channel pair connected to the positive supply and the N-channel pair to the negative supply or ground.
    Type: Grant
    Filed: September 29, 1995
    Date of Patent: June 3, 1997
    Assignee: International Business Machines Corporation
    Inventors: Frank D. Ferraiolo, John E. Gersbach, Ilya J. Novof, Edward J. Nowak
  • Patent number: 5636133
    Abstract: An efficient method for modifying a chip or package design allows for the creation of small shapes without excessive expansion of design data. A computer program takes a physical design, represented in a computer data file, and generates a modified version of the design in which fill shapes have been added. Subsequently, when the modified design is processed, the resulting semiconductor chip or package will contain physical images of the added fill shapes, with the effect of making local pattern density more uniform and hence reducing process-induced variations in feature size and shape.
    Type: Grant
    Filed: May 19, 1995
    Date of Patent: June 3, 1997
    Assignee: International Business Machines Corporation
    Inventors: Donald G. Chesebro, Young O. Kim, Mark A. Lavin, Daniel N. Maynard
  • Patent number: 5636320
    Abstract: A reactor is provided for heating a workpiece in a sealed environment. The reactor has a chamber with a gas inlet port, a gas outlet port, and at least one tube for receiving a heat source. The tube passes from outside the chamber into the inside of the chamber without breaking the chamber seal. Alternately, the tubes may be used for treating the workpiece with light, in combination with or instead of heat treatment.
    Type: Grant
    Filed: May 26, 1995
    Date of Patent: June 3, 1997
    Assignee: International Business Machines Corporation
    Inventors: Chienfan Yu, David E. Kotecki, Wesley C. Natzle
  • Patent number: 5635337
    Abstract: A structure of openings is produced in two or more layers of silylated, polyimide photoresist. Openings in subsequent layers, which overlap previous openings, are of larger size. Then the structure is transferred to an organic substrate using oxygen plasma etching with up to 3% CF.sub.4. The smallest opening transferred to the substrate extends through the substrate.
    Type: Grant
    Filed: May 5, 1993
    Date of Patent: June 3, 1997
    Assignee: International Business Machines
    Inventors: Johann Bartha, Johann Greschner, Karl H. Probst, Gerhard Schmid
  • Patent number: 5635761
    Abstract: Thin-film conductor technology is utilized to form resistors of precisely controlled value within the interior of multi-chip modules to properly terminate network circuits which interconnect one or more chips with either output pin connections or other chips on the multi-chip module. By forming and disposing the resistors within the interior of the multi-chip module, the terminating resistors may be manufactured during the multi-chip module manufacturing process. This approach preserves valuable surface area available for interconnecting the computer chips to the multi-chip module rather than consuming scarce surface area with termination resistors and other circuit elements necessary to adapt the multi-chip module and the other computer chips to each other.
    Type: Grant
    Filed: December 14, 1994
    Date of Patent: June 3, 1997
    Assignee: International Business Machines, Inc.
    Inventors: Tai A. Cao, Herbert I. Stoller, Thanh D. Trinh, Lloyd A. Walls
  • Patent number: 5635846
    Abstract: A high density test probe is for testing a high density and high performance integrated circuits in wafer form or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are embedded in an compliant or high modulus elastomeric material. A standard packaging substrate, such as a ceramic integrated circuit chip packaging substrate is used to provide a space transformer. Wires are bonded to an array of contact pads on the surface of the space transformer. The space transformer formed from a multilayer integrated circuit chip packaging substrate. The wires are as dense as the contact location array. A mold is disposed surrounding the array of outwardly projecting wires. A liquid elastomer is disposed in the mold to fill the spaces between the wires.
    Type: Grant
    Filed: April 30, 1993
    Date of Patent: June 3, 1997
    Assignee: International Business Machines Corporation
    Inventors: Brian S. Beaman, Keith E. Fogel, Paul A. Lauro, Maurice H. Norcott, Da-Yuan Shih, George F. Walker
  • Patent number: 5636218
    Abstract: Disclosed is a gateway system and method for controlling same which allows a video conference to be held with a participant (node) being on a plain old telephone system by using a conventional private telephone system and a LAN. The gateway system relays data, via a private branch exchange, to an information processing unit that is on an external plain old telephone system, and an information processing unit that is connected to an extension telephone and a LAN. The system includes a modem for receiving a call from, or transmitting a call to, the plain old telephone system, and for modulating and demodulating a signal. A multiplexer/demultiplexer is used to multiplex voice information and computer data to prepare a packet, or demultiplex a packet to acquire voice data and computer data separately. A LAN adaptor is used for transmitting and receiving computer data via the LAN.
    Type: Grant
    Filed: October 17, 1995
    Date of Patent: June 3, 1997
    Assignee: International Business Machines Corporation
    Inventors: Katsuya Ishikawa, Seita Iida
  • Patent number: 5635931
    Abstract: A system and method for compressing or predicting data information received within an input stream, wherein contextual information is utilized in the selection of dictionaries for encoding or predicting of a next phrase within the information stream. The present invention utilizes contextual information in conjunction with dictionary-based Lempel-Ziv compression processes.
    Type: Grant
    Filed: June 2, 1994
    Date of Patent: June 3, 1997
    Assignee: International Business Machines Corporation
    Inventors: Peter A. Franaszek, Joy A. Thomas, Pantelis G. Tsoucas
  • Patent number: 5636373
    Abstract: An external time source is connected to a partitioned data processing system, having host processors controlled by a host hypervisor, and having operating systems in the partitions. The host processors each have a timer facility comprising a time-of-day (TOD) clock, and a clock comparator. When the hypervisor detects a need for synchronization between the external time source and a host timer facility, it insulates the operating system in the partition on that host from host synchronization, and synchronizes the host timer facility with the external time source. Subsequently, the operating system is placed into normal execution, with an adjustment value used for timer facility references, and with a synchronization interrupt pending if the operating system is aware of the external time source.
    Type: Grant
    Filed: December 15, 1993
    Date of Patent: June 3, 1997
    Assignee: International Business Machines Corporation
    Inventors: Beth A. Glendening, Roger E. Hough, Karen Udy, Stephanie W. W. Zhang
  • Patent number: 5634017
    Abstract: A computer technique for providing a user-friendly environment which simplifies the construction of relativistic models of atoms and ionc. A computer includes a data processing system, a visual display unit and a data entry device. An operating system, a text/graphic interactive user interface and a number of atomic structure programs reside in the data processing system. The atomic structure programs perform atomic computations to calculate and construct mathematical atomic models based on specific atomic data which is input by an operator and retrieved from a stored atomic data base. The text/graphic interactive user interface includes the following programs: SMARTPET (SMART PEriodic Table tool), ATOMGRAF (ATOMic GRAph(F)ics), RASPIE (Relativistic Atomic Structure Program Interactive Environment), and ATOMBAS (ATOMic data BASe). SMARTPET presents atomic data in familiar formats so that a user can select and identify the atom or ion to investigated.
    Type: Grant
    Filed: June 21, 1996
    Date of Patent: May 27, 1997
    Assignee: International Business Machines Corporation
    Inventors: Ajaya K. Mohanty, Farid A. Parpia
  • Patent number: 5634127
    Abstract: A message driven processor operates as middleware between clients and back-end hosts or servers in a large client-server system to reduce the number of concurrent sessions required to be supported by the network and to allow a common client user interface to divergent back-end systems. High level requests from a client in support of a business function are translated into workflows which may involve multiple requests to back-end servers by the message driven processor. Information resulting from workflows and information retrieved from back-end servers may be integrated into a single reply message to the requesting client.
    Type: Grant
    Filed: November 30, 1994
    Date of Patent: May 27, 1997
    Assignee: International Business Machines Corporation
    Inventors: Donald M. Cloud, Kevin F. Kelly, David P. Bonaccorsi, Mark K. Weeks
  • Patent number: 5632438
    Abstract: A direct chip attachment process and apparatus for aluminum wirebonding on copper circuitization are provided. After at least one integrated circuit chip is attached to a carrier, an aqueous cleaning solution containing citric and oxalic acid based additives is applied to the carrier and attached integrated circuit chip. Then a deionized water rinse is applied to the carrier and attached integrated circuit chip, followed drying for a set time period. Next wirebonding on copper circuitization carried by the carrier is performed.
    Type: Grant
    Filed: October 12, 1995
    Date of Patent: May 27, 1997
    Assignee: International Business Machines Corporation
    Inventors: Mark K. Hoffmeyer, Gregg A. Knotts, Connie J. Mathison
  • Patent number: 5634025
    Abstract: In a data processing system, a plurality of primary and secondary prefetch elements are provided for prefetching a primary portion and a secondary portion of instruction words from a group of primary and secondary memory arrays coupled to each primary and secondary prefetch element, respectively. In response to a selected primary or secondary prefetch element receiving a prefetch token, the selected primary or secondary prefetch element sequentially recalls instruction words from the group of primary or secondary memory arrays, respectively. In response to a forthcoming conditional branch instruction, a plurality of prefetch elements may initiate instruction fetching so that the proper instruction may be executed during the cycle time immediately following the conditional branch instruction.
    Type: Grant
    Filed: April 18, 1994
    Date of Patent: May 27, 1997
    Assignee: International Business Machines Corporation
    Inventor: Mauricio Breternitz, Jr.
  • Patent number: 5633195
    Abstract: A method of laser planarizing metallic thin films minimizes the laser fluences required to melt or nearly melt the metalization. This is accomplished by reducing the optical reflectivity of the metallic lines and vias by using textured thin films. This reduction of optical reflectivity, in turn, reduces the minimum fluence needed to melt or nearly melt the metal using a laser, thus improving the process window and minimizing the damage to the surrounding media.
    Type: Grant
    Filed: September 22, 1995
    Date of Patent: May 27, 1997
    Assignee: International Business Machines, Corp.
    Inventors: William L. Guthrie, Naftali E. Lustig
  • Patent number: 5633767
    Abstract: The present invention overcomes the problems that accompany the use of ramps to load and unload transducer carrying sliders in rigid magnetic disk data storage devices. The tracks in the region where the slider loads and unloads are read and the errors recorded following each slider loading operation. One technique is to track the error increase and identify imminent device failure when the rate of error increase during a given number of the most recent slider load cycles exceeds a threshold value. In another mode, a dedicated sequence of tracks is recorded at an increased linear density to assure that read errors occur to enable a more effective comparative evaluation. This makes possible a two stage evaluation, a first threshold number of errors indicative of degrading performance which initiates lower actuator velocity to inhibit further degradation and a second threshold error quantity that indicates imminent catastrophic failure and triggers a warning to the system user.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: May 27, 1997
    Assignee: International Business Machines Corporation
    Inventors: Zine-Eddine Boutaghou, Hal H. Ottesen, Gordon J. Smith
  • Patent number: 5634007
    Abstract: A method and apparatus for performing direct memory address (DMA) operations between a requestor and responder device by prestoring, for each device, a logical token and offset value which is recognizable by the device as an indicia to identify one or more local memory addresses within the device, and initiating a DMA operation within the requestor device by the requestor device transferring the token and offset value to the responder device, the responder device identifying a responder device local memory address by translation of the token and offset value, and the responder device accessing the identified responder local memory address for data transfer, associated with the token and offset, and the requestor device identifying a requestor device local memory address for completing the data transfer.
    Type: Grant
    Filed: March 2, 1995
    Date of Patent: May 27, 1997
    Assignee: International Business Machines Corporation
    Inventors: Salvatore A. Calta, Robert B. Cook, Fernando A. Luiz, Gregory M. Nordstrom, Martin W. Sachs, Caryl A. Thorn
  • Patent number: 5633034
    Abstract: The invention relates to a process for forming a circuit assembly comprising (i) coating onto a substrate a layer of polyamic ester selected from a unique class of polyamic esters; (ii) imidizing the polyamic ester to form a layer of polyimide having an even surface and (iii) forming circuit conductors on the even surface of the polyimide.
    Type: Grant
    Filed: May 9, 1996
    Date of Patent: May 27, 1997
    Assignee: International Business Machines Corporation
    Inventors: Kenneth R. Carter, Richard A. DiPietro, James L. Hedrick, John P. Hummel, Robert D. Miller, Martha I. Sanchez, Willi Volksen, Do Y. Yoon
  • Patent number: 5634026
    Abstract: In a method and apparatus for result forwarding, a source operand compare circuit for a reservation station for a superscalar processor having a plurality of execution units, includes a source identifier for identifying an execution unit that will produce a needed result. The source identifier is included with a rename tag associated with a respective source operand. A multiplexor controlled by the source identifier directs the result of an execution unit to a comparator. The comparator compares the rename tag with a specific reservation station identity. As a result of this comparison, the needed data result is supplied to the respective source operand.
    Type: Grant
    Filed: May 12, 1995
    Date of Patent: May 27, 1997
    Assignee: International Business Machines Corporation
    Inventors: Jay G. Heaslip, Miles G. Canada
  • Patent number: 5634099
    Abstract: There is provided a Direct Access Memory Unit (DAu) that is associated with a remote processor module in a multi-processing system. The DAU performs Direct Memory Access (DMA) operations independently of a Central Processing Unit (CPU) in the remote processor module. The CPU requests a DMA by writing information relevant to the DMA to the remote processor's memory. The address of each control block is written to a circular queue, also in the remote processor's memory. The DAU determines if there are any control blocks to process and if so, the DAU will perform the DMA operation (reading data from or writing data to the memory of the host processor), all without the intervention of the CPU of the remote processor module. The CPU adds a new control block by loading its address in a location in the circular queue that is ahead of the circular queue location that the DAU is processing. The CPU can abort a pending DMA request during DAU operations by setting a skip bit in the control block.
    Type: Grant
    Filed: December 9, 1994
    Date of Patent: May 27, 1997
    Assignee: International Business Machines Corporation
    Inventors: Lawrence P. Andrews, Derrick Arias, Baiju D. Mandalia, Oscar E. Ortega, John C. Sinibaldi, Kevin B. Williams