Abstract: Methods, apparatus, systems and articles of manufacture for loss-error-aware quantization of a low-bit neural network are disclosed. An example apparatus includes a network weight partitioner to partition unquantized network weights of a first network model into a first group to be quantized and a second group to be retrained. The example apparatus includes a loss calculator to process network weights to calculate a first loss. The example apparatus includes a weight quantizer to quantize the first group of network weights to generate low-bit second network weights. In the example apparatus, the loss calculator is to determine a difference between the first loss and a second loss. The example apparatus includes a weight updater to update the second group of network weights based on the difference. The example apparatus includes a network model deployer to deploy a low-bit network model including the low-bit second network weights.

Abstract: A processing apparatus described herein includes a general-purpose parallel processing engine comprising a systolic array having multiple pipelines, each of the multiple pipelines including multiple pipeline stages, wherein the multiple pipelines include a first pipeline, a second pipeline, and a common input shared between the first pipeline and the second pipeline.

Abstract: Techniques described herein address the above challenges that arise when using host executed software to manage vector databases by providing a vector database accelerator and shard management offload logic that is implemented within hardware and by software executed on device processors and programmable data planes of a programmable network interface device. In one embodiment, a programmable network interface device includes infrastructure management circuitry configured to facilitate data access for a neural network inference engine having a distributed data model via dynamic management of a node associated with the neural network inference engine, the node including a database shard of a vector database.

Abstract: This disclosure describes systems, methods, and devices related to high throughput (HT) control information. A device may determine a frame comprising HT control information. The device may determine to extend a size of the HT control information. The device may cause to generate a management or data frame for sending to a first station device of one or more station devices, the management or data frame comprising extended high throughput (HT) control information, define a new control identification (ID) associated with the extended HT control information, and cause to send the management or data frame to the first station device.

Abstract: Generally discussed herein are systems, methods, and apparatuses that include conductive pillars that are about co-planar. According to an example, a technique can include growing conductive pillars on respective exposed landing pads of a substrate, situating molding material around and on the grown conductive pillars, removing, simultaneously, a portion of the grown conductive pillars and the molding material to make the grown conductive pillars and the molding material about planar, and electrically coupling a die to the conductive pillars.

Abstract: Technologies for trusted I/O include a computing device having a hardware cryptographic agent, a cryptographic engine, and an I/O controller. The hardware cryptographic agent intercepts a message from the I/O controller and identifies boundaries of the message. The message may include multiple DMA transactions, and the start of message is the start of the first DMA transaction. The cryptographic engine encrypts the message and stores the encrypted data in a memory buffer. The cryptographic engine may skip and not encrypt header data starting at the start of message or may read a value from the header to determine the skip length. In some embodiments, the cryptographic agent and the cryptographic engine may be an inline cryptographic engine. In some embodiments, the cryptographic agent may be a channel identifier filter, and the cryptographic engine may be processor-based. Other embodiments are described and claimed.

Abstract: Described herein are stacked photonic integrated circuit (PIC) assemblies that include multiple layers of waveguides. The waveguides are formed of substantially monocrystalline materials, which cannot be repeatedly deposited. Layers of monocrystalline material are fabricated and repeatedly transferred onto the PIC structure using a layer transfer process, which involves bonding a monocrystalline material using a non-monocrystalline bonding material. Layers of isolation materials are also deposited or layer transferred onto the PIC assembly.

Abstract: Package substrates with components included in cavities of glass cores are disclosed. An example apparatus includes: a glass core having a first opening and a second opening spaced apart from the first opening, the second opening having a greater width than the first opening. The example apparatus further includes a conductive material adjacent a first wall of the first opening; and a dielectric material adjacent a second wall of the second opening.

Abstract: Methods and apparatus relating to an instruction and/or micro-architecture support for decompression on core are described. In an embodiment, decode circuitry decodes a decompression instruction into a first micro operation and a second micro operation. The first micro operation causes one or more load operations to fetch data into one or more cachelines of a cache of a processor core. Decompression Engine (DE) circuitry decompresses the fetched data from the one or more cachelines of the cache of the processor core in response to the second micro operation. Other embodiments are also disclosed and claimed.

Abstract: Techniques for scalable virtualization of an Input/Output (I/O) device are described. An electronic device composes a virtual device comprising one or more assignable interface (AI) instances of a plurality of AI instances of a hosting function exposed by the I/O device. The electronic device emulates device resources of the I/O device via the virtual device. The electronic device intercepts a request from the guest pertaining to the virtual device, and determines whether the request from the guest is a fast-path operation to be passed directly to one of the one or more AI instances of the I/O device or a slow-path operation that is to be at least partially serviced via software executed by the electronic device. For a slow-path operation, the electronic device services the request at least partially via the software executed by the electronic device.

Abstract: Memory management for wireless networks is described. A method, includes accessing an operational parameter for a network slice of a wireless network, determining a first memory region of a plurality of memory regions in the memory pool based on the operational parameter, and encoding configuration information to allocate the first memory region to the network slice. Other embodiments are described and claimed.

Abstract: In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive an input from one or more detectors proximate a display to present an output from a graphics pipeline, determine that a user is not interacting with the display, and in response to a determination that the user is not interacting with the display, to reduce a frame rendering rate of the graphics pipeline. Other embodiments are also disclosed and claimed.

Abstract: A processing apparatus includes a processing resource including a general-purpose parallel processing engine and a matrix accelerator. The matrix accelerator includes first circuitry to receive a command to perform operations associated with an instruction, second circuitry to configure the matrix accelerator according to a physical depth of a systolic array within the matrix accelerator and a logical depth associated with the instruction, third circuitry to read operands for the instruction from a register file associated with the systolic array, fourth circuitry to perform operations for the instruction via one or more passes through one or more physical pipeline stages of the systolic array based on a configuration performed by the second circuitry, and fifth circuitry to write output of the operations to the register file associated with the systolic array.

Abstract: Techniques to improve performance of matrix multiply operations are described in which a compute kernel can specify one or more element-wise operations to perform on output of the compute kernel before the output is transferred to higher levels of a processor memory hierarchy.

Abstract: Described herein are gate-all-around (GAA) transistors with extended drains, where the drain region extends through a well region below the GAA transistor. A high voltage can be applied to the drain, and the extended drain region provides a voltage drop. The transistor length (and, specifically length of the extended drain) can be varied based on the input voltage to the device, e.g., providing a longer drain for higher input voltages. The extended drain transistors can be implemented in devices that include CFETs, either by implementing the extended drain transistor across both CFET layers, or by providing a sub-fin pedestal with the well regions in the lower layer.

Abstract: Predictive uncertainty of a generative machine learning model may be estimated. The generative machine learning model may be a large language model or large multi-modal model. A datum may be input into the generative machine learning model. The generative machine learning model may generate outputs from the datum. Latent embeddings for the outputs may be extracted from the generative machine learning model. A covariance matrix with respect to the latent embeddings may be computed. The covariance matrix may be a two-dimensional matrix, such as a square matrix. The predictive uncertainty of the generative machine learning model may be estimated using the covariance matrix. For instance, the matrix entropy of the covariance matrix may be determined. The matrix entropy may be an approximated dimension of a latent semantic manifold spanned by the outputs of the generative machine learning model and may indicate the predictive uncertainty of the generative machine learning model.

Abstract: A datacenter including a plurality of racks. The racks associated with a motorized and/or automated system to move the racks between first and second positions. In the first position, the racks are arranged in a side-by-side fashion in one or more rows. In the second position, a rack is moved so that a lateral side of the rack is accessible. In some embodiments, the racks include a motor and gear system for interacting with tracks. In some embodiments, each of the racks includes a plurality of chassis, each chassis including a plurality of input/output (I/O) connectors to receive a connector of a cable, the plurality of I/O connectors are arranged along a lateral side of the chassis so that they are accessible when the rack is in the second position. In use, the racks may be moved between the first and second positions while the chassis remain in normal operation.

Abstract: Logic may monitor quality of communication of data to a wireless receiver device based on transport characteristics at a wireless source device. Logic may evaluate the transport characteristics to identify indication(s) of a problem with the quality of the communication. Logic may identify a root cause associated with the indication(s). Logic may associate the root cause with one or more actions to mitigate the degradation of the quality. And logic may cause performance of an operation to mitigate the degradation of the quality based on the one or more actions. The logic to evaluate the transport characteristics may determine an upper limit for an achievable mean opinion score (MOS) based on the transport characteristics; and, based on the upper limit for the achievable MOS being less than a threshold MOS, may identify the indication(s) associated with the upper limit for the achievable MOS.

Abstract: An apparatus to facilitate exception handling for debugging in a graphics environment is disclosed. The apparatus includes load store pipeline hardware circuitry to: in response to a page fault exception being enabled for a memory access request received from a thread of the plurality of threads, allocate a memory dependency token correlated to a scoreboard identifier (SBID) that is included with the memory access request; send, to memory fabric of the graphics processor, the memory access request comprising the memory dependency token; receive, from the memory fabric in response to the memory access request, a memory access response comprising the memory dependency token and indicating occurrence of a page fault error condition and fault details associated with the page fault error condition; and return the SBID associated with the memory access response and fault details of the page fault error condition to a debug register of the thread.

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.

Abstract: In one embodiment, an apparatus includes: an integrity circuit to receive data and generate a protection code based at least in part on the data; a cryptographic circuit coupled to the integrity circuit to encrypt the data into encrypted data and encrypt the protection code into an encrypted protection code; a message authentication code (MAC) circuit coupled to the cryptographic circuit to compute a MAC comprising a tag using header information, the encrypted data, and the encrypted protection code; and an output circuit to send the header information, the encrypted data, and the tag to a receiver via a link. Other embodiments are described and claimed.

Abstract: Methods and apparatus to improve user experience on computing devices are disclosed. An example computing device includes a microphone to capture audio corresponding to spoken words. The example computing device further includes a speech analyzer to: detect a keyword prompt from among the spoken words, the keyword prompt to precede a query statement of a user of the computing device; and identify topics associated with a subset of the spoken words, the subset of the spoken words captured by the microphone before the keyword prompt. The example computing device also includes a communications interface to, in response to detection of the keyword prompt, transmit information indicative of the query statement and ones of the identified topics to a remote server.

Abstract: This disclosure describes systems, methods, and devices related to using encrypted 802.11 association. A device may identify a beacon received from an access point (AP), the beacon including an indication of an authentication and key manager (AKM); transmit, to the AP, an 802.11 authentication request including an indication of parameters associated with the AKM; identify an 802.11 authentication response received from the AP based on the 802.11 authentication request, the 802.11 authentication response including a message integrity check (MIC) using a key confirmation key (KCK) and an indication that the parameters have been selected by the AP; transmit, to the AP, an 802.11 association request encrypted by a security key based on an authenticator address of the AP; and identify an 802.11 association response received from the AP based on the 802.11 association request, the 802.11 association response encrypted by the security key.

Abstract: The disclosed embodiments are generally directed to inline encryption of data at line speed at a chip interposed between two memory components. The inline encryption may be implemented at a System-on-Chip (“SOC” or “SOC”). The memory components may comprise Non-Volatile Memory express (NVMe) and a dynamic random access memory (DRAM). An exemplary device includes an SOC to communicate with a Non-Volatile Memory NVMe circuitry to provide direct memory access (DMA) to an external memory component. The SOC may include: a cryptographic controller circuitry; a cryptographic memory circuitry in communication with the cryptographic controller, the cryptographic memory circuitry configured to store instructions to encrypt or decrypt data transmitted through the SOC; and an encryption engine in communication with the crypto controller circuitry, the encryption engine configured to encrypt or decrypt data according to instructions stored at the crypto memory circuitry. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to techniques for multi-tile memory management. In an example, a graphics processor includes an interposer, a first chiplet coupled with the interposer, the first chiplet including a graphics processing resource and an interconnect network coupled with the graphics processing resource, cache circuitry coupled with the graphics processing resource via the interconnect network, and a second chiplet coupled with the first chiplet via the interposer, the second chiplet including a memory-side cache and a memory controller coupled with the memory-side cache. The memory controller is configured to enable access to a high-bandwidth memory (HBM) device, the memory-side cache is configured to cache data associated with a memory access performed via the memory controller, and the cache circuitry is logically positioned between the graphics processing resource and a chiplet interface.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (RDL) on the first layer, wherein the RDL is electrically coupled to the second surface of the first die by solder interconnects, and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by non-solder interconnects.

Abstract: One embodiment provides an apparatus comprising a memory stack including multiple memory dies and a parallel processor including a plurality of multiprocessors. Each multiprocessor has a single instruction, multiple thread (SIMT) architecture, the parallel processor coupled to the memory stack via one or more memory interfaces. At least one multiprocessor comprises a multiply-accumulate circuit to perform multiply-accumulate operations on matrix data in a stage of a neural network implementation to produce a result matrix comprising a plurality of matrix data elements at a first precision, precision tracking logic to evaluate metrics associated with the matrix data elements and indicate if an optimization is to be performed for representing data at a second stage of the neural network implementation, and a numerical transform unit to dynamically perform a numerical transform operation on the matrix data elements based on the indication to produce transformed matrix data elements at a second precision.

Abstract: In one embodiment, a selective transfer process includes forming a layer of integrated circuit (IC) components on a first substrate. The method also includes dispensing liquid droplets into a subset of a plurality of areas of a second substrate, where the areas of the second substrate are defined by hydrophobic lines patterned to match a layout of the IC components on the first substrate. The method further includes partially bonding the first substrate to the second substrate, where a subset of the IC components on the first substrate are bonded to the liquid droplets on the second substrate (e.g., via capillary forces), and separating the first substrate from the second substrate. When the first substrate is separated from the second substrate, the subset of IC components is separated from the first substrate and remain on the second substrate.

Abstract: Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. One or both of an integrated circuit (IC) die hybrid bonding region and a base substrate hybrid bonding region surrounded by hydrophobic structures that include a cross-linked material. The hybrid bonding regions are brought together with a liquid droplet therebetween, and capillary forces cause the IC die to self-align. A hybrid bond is formed by evaporating the droplet and a subsequent anneal. The cross-linked material hydrophobic structures contain the liquid droplet for alignment and are resistant to plasma treatment prior to bonding.

Abstract: Techniques for a coaxial inductor in a glass core are disclosed. In an illustrative embodiment, an inductor is positioned in a cavity of a glass core. The inductor includes a conductive via extending through the glass core surrounded by a magnetic material. A buffer layer is positioned between the edges of the cavity of the glass core and the inductor. The buffer can prevent or mitigate any stress caused by changes in temperature and different coefficients of thermal expansion of the glass core and the inductor. The inductor may form part of a fully integrated voltage regulator (FIVR), which provides a stable voltage source to a semiconductor die such as a processor.

Abstract: Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. An integrated circuit (IC) die backside surface and a surface of a structural substrate each include bonding regions surrounded by hydrophobic structures. A liquid droplet is applied to the die or structural substrate bonding region and the die is placed on the bonding region of the structural substrate. Capillary forces cause the die to self-align to the bonding region, and a bond is formed by evaporating the liquid and subsequent anneal. A hybrid bond is then formed between the opposing active surface of the die and a base substrate using wafer-to-wafer bonding. IC structures including the IC die and portions of the structural substrate and base substrate are segmented from the bonded wafers and assembled.

Abstract: Integrated circuit (IC) devices and systems with virtual ground nets, and methods of forming the same, are disclosed herein. In one embodiment, an integrated circuit die includes a device layer with transistors, a first interconnect over the device layer, and a second interconnect under the device layer. Moreover, the first interconnect includes ground traces, which are electrically coupled to each other in the first interconnect or the second interconnect.

Abstract: Methods of selectively transferring integrated circuit (IC) components between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a first substrate with a release layer and a layer of IC components over the release layer is received, and a second substrate with one or more adhesive areas is received. The layer of IC components may include one or more antennas, interconnects, inductors, capacitors, or transformers. The first substrate is partially bonded to the second substrate, such that a subset of IC components on the first substrate are bonded to the adhesive areas on the second substrate. The first substrate is then separated from the second substrate, and the subset of IC components bonded to the second substrate are separated from the first substrate and remain on the second substrate.

Abstract: In one embodiment, an integrated circuit device includes a substrate and a component coupled to the substrate. The substrate includes first reservoirs comprising Gallium-based liquid metal (LM), second reservoirs, first channels between the first reservoirs, and second channels between the second reservoirs and respective first reservoirs. The component includes circuitry and conductive contacts connected to the circuitry. Each contact defines a cavity and a portion of each conductive contact is within a respective first reservoir of the substrate such that it is in contact with the LM in the first reservoir. The component further includes dielectric lines between the conductive contacts, and each dielectric line is at least partially within a respective first channel of the substrate.

Abstract: An apparatus to facilitate conversion operations and special value use cases supporting 8-bit floating point format in a graphics architecture is disclosed. The apparatus includes a processor comprising a decoder to decode an instruction fetched for execution into a decoded instruction, wherein the decoded instruction to cause the processor to perform conversion operation corresponding to an 8-bit floating point format operand; a scheduler to schedule the decoded instruction and provide input data for an input operand of the conversion operation indicated by the decoded instruction; and conversion circuitry to execute the decoded instruction to perform the conversion operation to convert the input operand to an output operand in accordance with the 8-bit floating point format operand, the conversion circuitry comprising hardware circuitry to rescale, normalize, and convert the input operand to the output operand.

Abstract: Devices, transistor structures, systems, and techniques are described herein related to contacting source and drain transistor structures from the device backside at small dimensions and cell sizes. A first subset of dummy contact structures are removed and backfilled with contact metal and a first etch stop material. A second subset of dummy contact structures are removed and backfilled with contact metal and a second etch stop material. Subsequent metallization contacts to the first and second contacts are made using two masking/selective etch processes such that any misalignment to the other contact type does not allow contact due to the pertinent etch stop material.

Abstract: Described herein is a technique to approximate photorealistic indirect illumination shown in path traced images for dynamic lighting environments using a neural network. Given a lightly ray traced image, intermediate buffers from rendering pipeline, and light and camera information, the photorealism of rendered images can be enhanced via the neural network to approximate path traced indirect illumination.

Abstract: The substrate of an integrated circuit component comprises a multi-layer die structure conductively coupled to the substrate. The multi-die layered structure includes a first primary integrated circuit die attached to the substrate and communicatively coupled to a first photonic integrated circuit (PIC) die, and a second primary integrated circuit die vertically spaced from the first primary integrated circuit die and communicatively coupled to a second PIC die. The integrated circuit component further includes a first intermediate waveguide optically coupling a first PIC waveguide of the first PIC die to a first substrate waveguide in the substrate, and a second intermediate waveguide optically coupling a second PIC waveguide of the second PIC die to a second substrate waveguide in the substrate. The integrated circuit component may further include a third intermediate waveguide optically coupling the first PIC die to the second PIC die.

Abstract: Disclosed examples generate an original equipment manufacturer (OEM) private key and an OEM public key; generate an OEM certificate based on the OEM public key; cause sending of the OEM certificate from an OEM product to a silicon provider, the silicon provider to sign the OEM certificate based on a silicon provider private key; and cause storage of the signed OEM certificate in the OEM product.

Abstract: Hybrid bonded multi-level die stacks, related apparatuses, systems, and methods of fabrication are disclosed. First-level integrated circuit (IC) dies and a base substrate each include hybrid bonding regions surrounded by hydrophobic structures. The hybrid bonding regions are brought together with a liquid droplet therebetween, and capillary forces cause the IC die to self-align. A hybrid bond is formed by evaporating the droplet followed by anneal. Hybrid bonding regions of second-level IC dies are similarly bonded to hybrid bonding regions on backsides of the first-level IC dies. This is repeated for any number of subsequent levels of IC dies. IC structures including the bonded IC dies and portions of the base substrate are segmented and assembled.

Abstract: An integrated circuit (IC) device includes a device substrate with front- and backside IC dies and an integrated heat spreader over the backside die. The heat spreader and the backside die may be coupled to the backside of the device substrate within an array of contacts. The backside heat spreader may include a mask layer over a thermally conductive layer. The IC device may include or be coupled to second substrate (such as a motherboard). The backside heat spreader may be thermally coupled to a heat spreader or heat sink by vias through the second substrate. The backside heat spreader may enclose the backside IC die in an electrically conductive cage.

Abstract: A shared memory controller receives, from a computing node, a request associated with a memory transaction involving a particular line in a memory pool. The request includes a node address according to an address map of the computing node. An address translation structure is used to translate the first address into a corresponding second address according to a global address map for the memory pool, and the shared memory controller determines that a particular one of a plurality of shared memory controllers is associated with the second address in the global address map and causes the particular shared memory controller to handle the request.

Abstract: For example, a radar Radio Head (RH) may be configured to determine Range-Doppler (RD) information corresponding to a plurality of RD bins based on digital radar Receive (Rx) signals representing radar Radio Frequency (RF) Rx signals received by one or more Rx antennas; to detect one or more detected RD bins based on the RD information; to provide filtered RD information including RD information corresponding to the one or more detected RD bins and excluding RD information of one or more excluded RD bins, which are not included in the one or more detected RD bins; and to send the filtered RD information to another processor via a communication interconnect.

Abstract: Methods for doping 2D transistor devices and resulting architectures. The use and placement of oxide dopants, such as, but not limited to, GeOx, enable control over threshold voltage performance and contact resistance of 2D transistor devices. Architectures include distinct stoichiometry compositions.

Abstract: Methods of selectively transferring integrated circuit (IC) components between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a first substrate with a release layer and a layer of IC components over the release layer is received, and a second substrate with one or more adhesive areas is received. The layer of IC components may include one or more transistors that contain one or more group III-V materials. The first substrate is partially bonded to the second substrate, such that a subset of IC components on the first substrate are bonded to the adhesive areas on the second substrate. The first substrate is then separated from the second substrate, and the subset of IC components bonded to the second substrate are separated from the first substrate and remain on the second substrate.

Abstract: A surface of an integrated circuit (IC) die structure and a substrate to which the IC die structure is to be bonded include biphilic regions suitable for liquid droplet formation and droplet-based fine alignment of the IC die structure to the substrate. To ensure warpage of the IC die structure does not interfere with droplet-based fine alignment process, an IC die structure of greater thickness is aligned to the substrate and thickness of the IC die structure subsequently reduced. In some embodiments, a back side of the IC die structure is polished back post attachment. In some alternative embodiments, the IC die structure includes sacrificial die-level carrier is removed after fine alignment and/or bonding.

Abstract: Techniques for dynamic cache fill prioritization are described. In an embodiment, an apparatus includes a cache at a mid-level of a cache hierarchy; and a mid-level cache (MLC) unit including the cache, a local queue to store MLC lookup requests, an external queue to store MLC fill requests, and an MLC access control hardware. The MLC access control hardware is to dynamically switch prioritization of servicing the MLC lookup requests versus servicing the MLC fill requests.

Abstract: A surface of an integrated circuit (IC) die structure and a substrate to which the IC die structure is to be bonded include biphilic regions suitable for liquid droplet formation and droplet-based fine alignment of the IC die structure to the substrate. To ensure warpage of the IC die structure does not interfere with droplet-based fine alignment process, an IC die structure of greater thickness is aligned to the substrate and thickness of the IC die structure subsequently reduced. In some embodiments, a back side of the IC die structure is polished back post attachment. In some alternative embodiments, the IC die structure includes sacrificial die-level carrier is removed after fine alignment and/or bonding.

Abstract: Input/output (I/O) routing from one integrated circuit die to other integrated circuit dies in an integrated circuit component comprising heterogeneous and vertically stacked die is made from the top and bottom surfaces of the integrated circuit die to the other dies. Die-to-die I/O routing from the die to laterally adjacent die is made from the top surface of the die via one or more redistribution layers. Die-to-die routing from the die to vertically adjacent die is made via hybrid bonding on the bottom surface of the die. Embedded bridges or chiplets or not used for die-to-die I/O routing, which can free up space for more through-dielectric vias to provide power and ground connections to the die, which can provide for improved power delivery.

Abstract: A surface of an integrated circuit (IC) die structure or a host structure to which the IC die structure is to be bonded includes a biphilic surface for liquid droplet formation and droplet-based fine alignment of the IC die structure to the substrate. Hydrophobic regions can be self-aligned to hydrophilic regions of the biphilic surface by forming precursor metallization features within the hydrophobic regions concurrently with the formation of metallization features within the hydrophilic regions. Metallization features within the hydrophobic regions may then be at least partially removed as sacrificial to facilitate the formation of a hydrophobic surface. Metallization features within the hydrophilic regions may be retained and ultimately bonded to complementary features of another IC die structure or substrate structure.