Intel Patent Applications
Intel patent applications that are pending before the United States Patent and Trademark Office (USPTO).
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Publication number: 20240130068Abstract: Technologies for a flexible three-dimensional power plane in a chassis are disclosed. In one embodiment, a flexible ribbon cable is laid along a circuit board tray. The flexible ribbon cable is secured to the tray using power bosses. The power bosses connect to one or more conductors on the ribbon cable. When the circuit board is mounted on the circuit board tray, the power bosses extend through holes in the circuit board and mate with power clips on the surface of the circuit board tray. The ribbon cable, power bosses, and power clips can distribute power to various locations on the circuit board, without requiring large traces that take up space on the circuit board.Type: ApplicationFiled: December 28, 2023Publication date: April 18, 2024Applicant: Intel CorporationInventors: Nan Wang, Zhichao Z. Zhang, Lihui Wu, Jialiang Xu, Xiaoguo Liang, Bo Chen, Haifeng Gong
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Publication number: 20240129944Abstract: For example, a wireless communication device may be configured to determine an expected interference-based value corresponding to an Uplink (UL) transmission from a wireless communication station (STA) in a Trigger-Based (TB) Multi-User (MU) UL transmission to be communicated from a plurality of STAs to the wireless communication device; to determine one or more transmit (Tx) configuration parameters for the STA based on the expected interference-based value corresponding to the UL transmission from the STA; and to transmit a trigger frame to trigger the TB MU UL transmission, the trigger frame including the one or more Tx configuration parameters to configure the UL transmission from the STA.Type: ApplicationFiled: December 28, 2023Publication date: April 18, 2024Applicant: INTEL CORPORATIONInventors: Alexander W. Min, Arik Klein, Rath Vannithamby, Ziv Avital
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Publication number: 20240128181Abstract: Embodiments of a microelectronic assembly that includes: a package substrate comprising a plurality of layers of organic dielectric material and conductive traces alternating with conductive vias in alternate layers of the organic dielectric material; and a plurality of integrated circuit dies coupled to a first side of the package substrate by interconnects, in which: the plurality of layers of the organic dielectric material comprises at least a first layer having a conductive via and a second layer having a conductive trace in contact with the conductive via, the second layer is not coplanar with the first layer, sidewalls of the conductive via are orthogonal to the conductive trace, and two opposing sidewalls of the conductive via separated by a width of the conductive via protrude from respectively proximate edges of the conductive trace by a protrusion that is at least ten times less than the width of the conductive via.Type: ApplicationFiled: October 17, 2022Publication date: April 18, 2024Applicant: Intel CorporationInventors: Jeremy Ecton, Brandon C. Marin, Srinivas V. Pietambaram, Hiroki Tanaka, Haobo Chen
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Publication number: 20240129804Abstract: For example, an Access Point (AP) may be configured to process network slicing information including slice identification information and Service Level Agreement (SLA) information, wherein the slice identification information is to identify one or more Quality of Service (QoS) network slices. For example, the AP may be configured to determine a configuration of one or more radio resource allocations to be assigned to the one or more QoS network slices, and to transmit a network slicing advertisement including network slicing assignment information to indicate an assignment of the one or more radio resource allocations to the one or more QoS network slices.Type: ApplicationFiled: December 28, 2023Publication date: April 18, 2024Applicant: Intel CorporationInventors: Roya Doostnejad, Ehud Reshef, Laurent Cariou
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Publication number: 20240130002Abstract: Various technologies relating to wireless sensor networks (WSNs) are disclosed, including, but not limited to, device onboarding and authentication, network association and synchronization, data logging and reporting, asset tracking, and automated flight state detection.Type: ApplicationFiled: March 3, 2022Publication date: April 18, 2024Applicant: Intel CorporationInventors: Rahul Khanna, Yi Qian, Greeshma Pisharody, Raju Arvind, Jiejie Wang, Laura M. Rumbel, Christopher R. Carlson, Jennifer M. Williams, Prince Adu Agyeman
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Publication number: 20240129496Abstract: Methods, systems, and articles are described herein related to video coding. The method comprises receiving compressed image data of video frames including a block of image data of at least one of the frames. The method also comprises receiving first partition data to be used to decode the compressed image data and indicating a partition in the block. This method comprises detecting whether or not the block has an illegal block partition. Also, the method comprises generating second partition data to indicate the illegal block partition of the block is to be ignored. Further, the method includes decoding the block at least according to the second partition data.Type: ApplicationFiled: December 28, 2023Publication date: April 18, 2024Applicant: Intel CorporationInventor: Tsung-Han Yang
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Publication number: 20240126357Abstract: Embodiments provided a blend circuit configured to perform a power optimized blend using blend circuitry configured such that the dynamic power consumed during the blending of two input color values is reduced when the input colors are close in value. When blending two identical input color values, a portion of the blend circuit can be bypassed and clock and/or data gated.Type: ApplicationFiled: December 20, 2023Publication date: April 18, 2024Applicant: Intel CorporationInventor: Theo Drane
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Publication number: 20240129058Abstract: For example, an apparatus may include a segment parser to parse scrambled data bits of a PPDU into a first plurality of data bits and a second plurality of data bits, the PPDU to be transmitted in an OFDM transmission over an aggregated bandwidth comprising a first channel in a first frequency band and a second channel in a second frequency band; a first baseband processing block to encode and modulate the first plurality of data bits according to a first OFDM MCS for transmission over the first channel in the first frequency band; and a second baseband block to encode and modulate the second plurality of data bits according to a second OFDM MCS for transmission over the second channel in the second frequency band.Type: ApplicationFiled: October 17, 2023Publication date: April 18, 2024Applicant: INTEL CORPORATIONInventors: Alexander W. Min, Thomas J. Kenney, Laurent Cariou, Shahrnaz Azizi, Xiaogang Chen, Robert J. Stacey, Qinghua Li
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Publication number: 20240126615Abstract: Embodiments for orchestrating execution of workloads on a distributed computing infrastructure are disclosed herein. In one example, environment data is received for compute devices in a distributed computing infrastructure. The environment data is indicative of an operating environment of the respective compute devices and a physical environment of the respective locations of the compute devices. Future operating conditions of the compute devices are predicted based on the environment data, and workloads are orchestrated for execution on the distributed computing infrastructure based on the predicted future operating conditions.Type: ApplicationFiled: December 13, 2023Publication date: April 18, 2024Applicant: Intel CorporationInventors: Sundar Nadathur, Akhilesh Thyagaturu, Jonathan L. Kyle, Scott M. Baker, Woojoong Kim
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Publication number: 20240129503Abstract: Described herein is a data processing system having a multisample antialiasing compressor coupled to a texture unit and shader execution array. In one embodiment, the data processing system includes a memory device to store a multisample render target, the multisample render target to store color data for a set of sample locations of each pixel in a set of pixels; and general-purpose graphics processor comprising a multisample antialiasing compressor to apply multisample antialiasing compression to color data generated for the set of sample locations of a first pixel in the set of pixels and a multisample render cache to store color data generated for the set of sample locations of the first pixel in the set of pixels, wherein color data evicted from the multisample render cache is to be stored to the multisample render target.Type: ApplicationFiled: October 23, 2023Publication date: April 18, 2024Applicant: Intel CorporationInventors: Prasoonkumar Surti, Abhishek R. Appu, Michael J. Norris, Eric G. Liskay
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Publication number: 20240126691Abstract: Technologies for cryptographic separation of MMIO operations with an accelerator device include a computing device having a processor and an accelerator. The processor establishes a trusted execution environment. The accelerator determines, based on a target memory address, a first memory address range associated with the memory-mapped I/O transaction, generates a second authentication tag using a first cryptographic key from a set of cryptographic keys, wherein the first key is uniquely associated with the first memory address range. An accelerator validator determines whether the first authentication tag matches the second authentication tag, and a memory mapper commits the memory-mapped I/O transaction in response to a determination that the first authentication tag matches the second authentication tag. Other embodiments are described and claimed.Type: ApplicationFiled: September 7, 2023Publication date: April 18, 2024Applicant: Intel CorporationInventors: Luis S. Kida, Reshma Lal, Soham Jayesh Desai
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Publication number: 20240127031Abstract: A graph neural network (GNN) model is used in a scheduling process for compiling a deep neural network (DNN). The DNN, and parameter options for scheduling the DNN, are represented as a graph, and the GNN predicts a set of parameters that is expected to have a low cost. Using the GNN-based model, a compiler can produce a schedule for compiling the DNN in a relatively short and predictable amount of time, even for DNNs with many layers and/or many parameter options. For example, the GNN-based model reduces the overhead of exploring every parameter combination and does not exclude combinations from consideration like prior heuristic-based approaches.Type: ApplicationFiled: December 22, 2023Publication date: April 18, 2024Applicant: Intel CorporationInventors: Hamza Yous, Ian Hunter, Alessandro Palla
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Publication number: 20240126967Abstract: Described herein are techniques to automatically create a software model which covers the core functionality of a semiconductor design to be formally verified and can be easily consumed by a formal verification tool for software or semiconductor designs. These techniques enable verification engineers to expand the scope of formal verification to fix both software and RTL bugs, saving significant design time and reducing the time to market of for new products.Type: ApplicationFiled: December 22, 2023Publication date: April 18, 2024Applicant: Intel CorporationInventors: Disha Puri, Sparsa Roychowdhury, Geethabai Biradar, Theo Drane, Achutha Kiran Kumar M V
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Publication number: 20240126519Abstract: Described herein is a technique and associated tool for automatic program code optimization for high-level synthesis. The tool can efficiently explore multiple representations of an input program using e-graph rewriting and determine an HLS-efficient representation of program code for input into high-level synthesis tools.Type: ApplicationFiled: December 26, 2023Publication date: April 18, 2024Applicant: Intel CorporationInventors: Jianyi Cheng, Samuel Coward, Lorenzo Chelini, Rafael Barbalho, Theo Drane
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Publication number: 20240126695Abstract: Various embodiments are generally directed to virtualized systems. A first guest memory page may be identified based at least in part on a number of accesses to a page table entry for the first guest memory page in a page table by an application executing in a virtual machine (VM) on the processor, the first guest memory page corresponding to a first byte-addressable memory. The execution of the VM and the application on the processor may be paused. The first guest memory page may be migrated to a target memory page in a second byte-addressable memory, the target memory page comprising one of a target host memory page and a target guest memory page, the second byte-addressable memory having an access speed faster than an access speed of the first byte-addressable memory.Type: ApplicationFiled: December 21, 2023Publication date: April 18, 2024Applicant: Intel CorporationInventors: Yao Zu DONG, Kun TIAN, Fengguang WU, Jingqi LIU
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Publication number: 20240127408Abstract: Embodiments are generally directed to an adaptive deformable kernel prediction network for image de-noising. An embodiment of a method for de-noising an image by a convolutional neural network implemented on a compute engine, the image including a plurality of pixels, the method comprising: for each of the plurality of pixels of the image, generating a convolutional kernel having a plurality of kernel values for the pixel; generating a plurality of offsets for the pixel respectively corresponding to the plurality of kernel values, each of the plurality of offsets to indicate a deviation from a pixel position of the pixel; determining a plurality of deviated pixel positions based on the pixel position of the pixel and the plurality of offsets; and filtering the pixel with the convolutional kernel and pixel values of the plurality of deviated pixel positions to obtain a de-noised pixel.Type: ApplicationFiled: November 20, 2023Publication date: April 18, 2024Applicant: Intel CorporationInventors: Anbang Yao, Ming Lu, Yikai Wang, Xiaoming Chen, Junjie Huang, Tao Lv, Yuanke Luo, Yi Yang, Feng Chen, Zhiming Wang, Zhiqiao Zheng, Shandong Wang
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Publication number: 20240126964Abstract: Described herein is a technique for automated detection of case-splitting opportunities in RTL. The techniques described herein facilitate the integration of case-splitting into a hardware design tool flow, allowing the generation of hardware designs that do not suffer from timing violations. One embodiment provides a method comprising analyzing a first hardware description in a hardware description language to identify a critical path in a circuit represented by the hardware description, automatically detecting a case-splitting opportunity within the critical path, generating hardware description language for a case split having determined operator domain restrictions, and outputting a second hardware description including the hardware description language for the case split, wherein the second hardware description has a reduced operator hardware cost for the critical path relative to the first hardware description.Type: ApplicationFiled: December 22, 2023Publication date: April 18, 2024Applicant: Intel CorporationInventors: Samuel Coward, Theo Drane, George A. Constantinides
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Publication number: 20240128247Abstract: Embodiments described herein enable a microelectronic assembly that includes: a first substrate comprising glass and at least one inductor, the first substrate having a first side and an opposing second side; a second substrate coupled to the first side of the first substrate; and a plurality of integrated circuit (IC) dies. A first subset of the plurality of IC dies is directly coupled to the second side of the first substrate, a second subset of the plurality of IC dies is directly coupled to the second substrate adjacent to the first substrate, and a third subset of the plurality of IC dies is embedded in the second substrate between the first substrate and the second subset of the plurality of IC dies.Type: ApplicationFiled: October 14, 2022Publication date: April 18, 2024Applicant: Intel CorporationInventors: Brandon C. Marin, Kristof Kuwawi Darmawikarta, Srinivas V. Pietambaram, Gang Duan, Jeremy Ecton, Suddhasattwa Nad, Hiroki Tanaka
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Publication number: 20240128023Abstract: Disclosed herein are IC structures with one or more decoupling capacitors based on dummy TSVs provided in a support structure. An example decoupling capacitor includes first and second capacitor electrodes and a capacitor insulator between them. The first capacitor electrode is a liner of a first electrically conductive material on sidewalls and a bottom of an opening in the support structure, the opening in the support structure extending from the first side towards, but not reaching, the second side. The capacitor insulator is a liner of a dielectric material on sidewalls and a bottom of the opening in the support structure lined with the first electrically conductive material. The second capacitor electrode is a second electrically conductive material filling at least a portion of the opening in the support structure lined with the first electrically conductive material and with the dielectric material.Type: ApplicationFiled: December 27, 2023Publication date: April 18, 2024Applicant: Intel CorporationInventor: Changyok Park
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Publication number: 20240128255Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.Type: ApplicationFiled: December 27, 2023Publication date: April 18, 2024Applicant: Intel CorporationInventors: Adel A. Elsherbini, Shawna M. Liff, Johanna M. Swan, Arun Chandrasekhar
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Publication number: 20240127478Abstract: Technologies for performing sensor fusion include a compute device. The compute device includes circuitry configured to obtain detection data indicative of objects detected by each of multiple sensors of a host system. The detection data includes camera detection data indicative of a two or three dimensional image of detected objects and lidar detection data indicative of depths of detected objects. The circuitry is also configured to merge the detection data from the multiple sensors to define final bounding shapes for the objects.Type: ApplicationFiled: December 4, 2023Publication date: April 18, 2024Applicant: Intel CorporationInventors: Soila Kavulya, Rita Chattopadhyay, Monica Lucia Martinez-Canales
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Publication number: 20240128340Abstract: Disclosed herein are integrated circuit (IC) contact structures, and related devices and methods. For example, in some embodiments, an IC contact structure may include an electrical element, a metal on the electrical element, and a semiconductor material on the metal. The metal may conductively couple the semiconductor material and the electrical element.Type: ApplicationFiled: December 26, 2023Publication date: April 18, 2024Applicant: Intel CorporationInventors: Patrick Morrow, Glenn A. Glass, Anand S. Murthy, Rishabh Mehandru
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Publication number: 20240127414Abstract: Systems and methods for tone mapping of high dynamic range (HDR) images for high-quality deep learning based processing are disclosed. In one embodiment, a graphics processor includes a media pipeline to generate media requests for processing images and an execution unit to receive media requests from the media pipeline. The execution unit is configured to compute an auto-exposure scale for an image to effectively tone map the image, to scale the image with the computed auto-exposure scale, and to apply a tone mapping operator including a log function to the image and scaling the log function to generate a tone mapped image.Type: ApplicationFiled: October 20, 2023Publication date: April 18, 2024Applicant: Intel CorporationInventor: Attila Tamas Afra
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Publication number: 20240128982Abstract: A hardware accelerator device is provided with circuitry to perform one or more reversible data transforms on data based on a request and compress the transformed data to generate compressed transformed data. The hardware accelerator device generates an output including the compressed transformed data and transform metadata indicating the set of reversible data transforms applied to the compressed transformed data.Type: ApplicationFiled: December 27, 2023Publication date: April 18, 2024Applicant: Intel CorporationInventors: Smita Kumar, Patrick Fleming
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Publication number: 20240128138Abstract: Semiconductor packages and methods for forming semiconductor packages are disclosed. An example semiconductor package includes a substrate and a core. An insulator material is present over the core, and along a direction perpendicular to a first surface of the core, a portion of the insulator material is between the core and a first surface of the substrate. A via extends between the first surface of the core and a second surface of the core in the direction perpendicular to the first surface of the core. A bridge die is in a recess in the substrate. The bridge die is coupled with the via. An electronic component is coupled to an end of the via at a second surface of the substrate.Type: ApplicationFiled: December 21, 2023Publication date: April 18, 2024Applicant: Intel CorporationInventors: Robert L. Sankman, Rahul N. Manepalli, Robert Alan May, Srinivas Venkata Ramanuja Pietambaram, Bharat P. Penmecha
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Publication number: 20240118898Abstract: Embodiments of apparatuses, methods, and systems for selective use of branch prediction hints are described. In an embodiment, an apparatus includes an instruction decoder and a branch predictor. The instruction decoder is to decode a branch instruction having a hint. The branch predictor is to provide a prediction and a hint-override indicator. The hint-override indicator is to indicate whether the prediction is based on stored information about the branch instruction. The prediction is to override the hint if the hint-override indicator indicates that the prediction is based on stored information about the branch instruction.Type: ApplicationFiled: October 3, 2023Publication date: April 11, 2024Applicant: Intel CorporationInventors: Jared W. Stark, Ahmad Yasin, Ajay Amarsingh Singh
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Publication number: 20240120305Abstract: Embodiments of a microelectronic assembly includes: a package substrate and an integrated circuit (IC) die coupled to a surface of the package substrate by first interconnects and second interconnects, the first interconnects and the second interconnects comprising solder. The first interconnects are larger than the second interconnects, the first interconnects and the second interconnects further comprise bumps on the IC die and bond-pads on the surface of the package substrate, with the solder coupled to the bumps and the bond-pads, lateral sides of the bumps have a coating of a material that prevents solder wicking, and the surface of the package substrate includes insulative baffles between the bond-pads.Type: ApplicationFiled: October 7, 2022Publication date: April 11, 2024Applicant: Intel CorporationInventors: Jeremy Ecton, Brandon C. Marin, Suddhasattwa Nad, Srinivas V. Pietambaram, Mohammad Mamunur Rahman
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Publication number: 20240120302Abstract: An electronic device includes first and second external conductive pads coupled to route a first signal and third and fourth external conductive pads. The third and the fourth external conductive pads are between the first and the second external conductive pads on a surface of the electronic device.Type: ApplicationFiled: December 18, 2023Publication date: April 11, 2024Applicant: Intel CorporationInventors: Krishna Bharath Kolluru, Atul Maheshwari, Mahesh Kumashikar, Md Altaf Hossain, Ankireddy Nalamalpu, Omkar Karhade
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Publication number: 20240121097Abstract: Embodiments are directed to providing integrity-protected command buffer execution. An embodiment of an apparatus includes a computer-readable memory comprising one or more command buffers and a processing device communicatively coupled to the computer-readable memory to read, from a command buffer of the computer-readable memory, a first command received from a host device, the first command executable by one or more processing elements on the processing device, the first command comprising an instruction and associated parameter data, compute a first authentication tag using a cryptographic key associated with the host device, the instruction and at least a portion of the parameter data, and authenticate the first command by comparing the first authentication tag with a second authentication tag computed by the host device and associated with the command.Type: ApplicationFiled: December 20, 2023Publication date: April 11, 2024Applicant: Intel CorporationInventors: Pradeep M. Pappachan, Reshma Lal
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Publication number: 20240119625Abstract: A method and system of automatically estimating a ball carrier in team sports.Type: ApplicationFiled: June 16, 2021Publication date: April 11, 2024Applicant: Intel CorporationInventors: Ming Lu, Liwei Liao, Haihua Lin, Xiaofeng Tong, Wenlong Li, Jiansheng Chen, Yiwei He
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Publication number: 20240118992Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to debug a hardware accelerator such as a neural network accelerator for executing Artificial Intelligence computational workloads. An example apparatus includes a core with a core input and a core output to execute executable code based on a machine-learning model to generate a data output based on a data input, and debug circuitry coupled to the core. The debug circuitry is configured to detect a breakpoint associated with the machine-learning model, compile executable code based on at least one of the machine-learning model or the breakpoint. In response to the triggering of the breakpoint, the debug circuitry is to stop the execution of the executable code and output data such as the data input, data output and the breakpoint for debugging the hardware accelerator.Type: ApplicationFiled: October 16, 2023Publication date: April 11, 2024Applicant: Intel CorporationInventors: Martin-Thomas Grymel, David Bernard, Martin Power, Niall Hanrahan, Kevin Brady
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Publication number: 20240121656Abstract: For example, a wireless communication device may be configured to determine a Concurrent Multiple Band (CMB) routing scheme based on Quality of Service (QoS) requirement information and network condition information, the CMB routing scheme to route a plurality of application streams to a plurality of radios of the wireless communication device for wireless communication over a plurality of wireless communication bands, the plurality of application streams corresponding to one or more applications to be executed by the wireless communication device; and to route the plurality of application streams to the plurality of radios by determining, based on the CMB routing scheme, to which radio of the plurality of radios to route the application stream of the plurality of application streams.Type: ApplicationFiled: June 29, 2023Publication date: April 11, 2024Applicant: INTEL CORPORATIONInventors: Daniel Cohn, David Birnbaum, Ehud Reshef, Ofer Hareuveni, Dor Chay
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Publication number: 20240119558Abstract: One embodiment provides a graphics processor comprising a set of processing resources configured to perform a supersampling anti-aliasing operation via a mixed precision convolutional neural network. The set of processing resources include circuitry configured to receive, at an input block of a neural network model, a set of data including previous frame data, current frame data, jitter offset data, and velocity data, pre-process the set of data to generate pre-processed data, provide pre-processed data to a feature extraction network of the neural network model and an output block of the neural network model, process the first pre-processed data at the feature extraction network via one or more encoder stages and one or more decoder stages, output tensor data from the feature extraction network to the output block, and generate an anti-aliased output frame via the output block based on the current frame data and the tensor data output from the feature extraction network.Type: ApplicationFiled: December 4, 2023Publication date: April 11, 2024Applicant: Intel CorporationInventors: Dmitry Kozlov, Aleksei Chernigin, Dmitry Tarakanov
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Publication number: 20240121079Abstract: One or more non-transitory computer-readable media with instructions stored thereon, wherein the instructions are executable to cause one or more processor units to responsive to a data clear command issued by a tenant of a cloud service provider, issue a plurality of write commands to storage locations utilized by the tenant, the write commands to write a value based on an input provided by the tenant to the storage locations; and provide data read from at least a subset of the storage locations for attestation by the tenant of performance of the data clear command.Type: ApplicationFiled: December 20, 2023Publication date: April 11, 2024Applicant: Intel CorporationInventors: Tat Kin Tan, Chew Yee Kee, Boon Khai Ng
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Publication number: 20240120415Abstract: Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. The perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers. Growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. The lattice-matched layers can be etched away, leaving the doped semiconductor layers as fins for a ribbon FET. A ferroelectric layer can be conformally grown on the fins, creating a high-quality ferroelectric layer above and below the fins. A gate can then be grown on the ferroelectric layer.Type: ApplicationFiled: October 1, 2022Publication date: April 11, 2024Applicant: Intel CorporationInventors: Scott B. Clendenning, Sudarat Lee, Kevin P. O'Brien, Rachel A. Steinhardt, John J. Plombon, Arnab Sen Gupta, Charles C. Mokhtarzadeh, Gauri Auluck, Tristan A. Tronic, Brandon Holybee, Matthew V. Metz, Dmitri Evgenievich Nikonov, Ian Alexander Young
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Publication number: 20240119255Abstract: An example apparatus to perform a convolution on an input tensor includes a parameters generator to: generate a horizontal hardware execution parameter for a horizontal dimension of the input tensor based on a kernel parameter and a layer parameter; and generate a vertical hardware execution parameter for a vertical dimension of the input tensor based on the kernel parameter and the layer parameter; an accelerator interface to configure a hardware accelerator circuitry based on the horizontal and vertical hardware execution parameters; a horizontal Iterator controller to determine when the hardware accelerator circuitry completes the first horizontal iteration of the convolution; and a vertical Iterator controller to determine when the hardware accelerator circuitry completes the first vertical iteration of the convolution.Type: ApplicationFiled: December 21, 2023Publication date: April 11, 2024Applicant: Intel CorporationInventors: Yaniv Fais, Moshe Maor
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Publication number: 20240111830Abstract: A non-linear activation function in a neural network may be approximated by one or more linear functions. The input range may be divided into input segments, each of which corresponds to a different exponent in the input range of the activation function and includes input data elements having the exponent. Target accuracies may be assigned to the identified exponents based on a statistics analysis of the input data elements. The target accuracy of an input segment will be used to determine one or more linear functions that approximate the activation function for the input segment. An error of an approximation of the activation function by a linear function for the input segment may be within the target accuracy. The parameters of the linear functions may be stored in a look-up table (LUT). During the execution of the DNN, the LUT may be used to execute the activation function.Type: ApplicationFiled: December 8, 2023Publication date: April 4, 2024Applicant: Intel CorporationInventors: Umer Iftikhar Cheema, Robert Simofi, Deepak Abraham Mathaikutty, Arnab Raha, Dinakar Kondru
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Publication number: 20240111459Abstract: An apparatus comprising first circuitry to determine a time parameter associated with a storage operation; and second circuitry to generate a storage command, the storage command including the time parameter, a location for the storage operation, and an opcode specifying the storage operation.Type: ApplicationFiled: December 7, 2023Publication date: April 4, 2024Applicant: Intel CorporationInventors: Daniel Christian Biederman, Jackson L. Ellis
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Publication number: 20240111609Abstract: Low-latency synchronization utilizing local team barriers for thread team processing is described. An example of an apparatus includes one or more processors including a graphics processor, the graphics processor including a plurality of processing resources; and memory for storage of data including data for graphics processing, wherein the graphics processor is to receive a request for establishment of a local team barrier for a thread team, the thread team being allocated to a first processing resource, the thread team including multiple threads; determine requirements and designated threads for the local team barrier; and establish the local team barrier in a local register of the first processing resource based at least in part on the requirements and designated threads for the local barrier.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Biju George, Supratim Pal, James Valerio, Vasanth Ranganathan, Fangwen Fu, Chunhui Mei
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Publication number: 20240111534Abstract: Embodiments described herein provide a technique enable a broadcast load from an L1 cache or shared local memory to register files associated with hardware threads of a graphics core. One embodiment provides a graphics processor comprising a cache memory and a graphics core coupled with the cache memory. The graphics core includes a plurality of hardware threads and memory access circuitry to facilitate access to memory by the plurality of hardware threads. The graphics core is configurable to process a plurality of load request from the plurality of hardware threads, detect duplicate load requests within the plurality of load requests, perform a single read from the cache memory in response to the duplicate load requests, and transmit data associated with the duplicate load requests to requesting hardware threads.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Fangwen Fu, Chunhui Mei, Maxim Kazakov, Biju George, Jorge Parra, Supratim Pal
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Publication number: 20240111826Abstract: An apparatus to facilitate hardware enhancements for double precision systolic support is disclosed. The apparatus includes matrix acceleration hardware having double-precision (DP) matrix multiplication circuitry including a multiplier circuits to multiply pairs of input source operands in a DP floating-point format; adders to receive multiplier outputs from the multiplier circuits and accumulate the multiplier outputs in a high precision intermediate format; an accumulator circuit to accumulate adder outputs from the adders with at least one of a third global source operand on a first pass of the DP matrix multiplication circuitry or an intermediate result from the first pass on a second pass of the DP matrix multiplication circuitry, wherein the accumulator circuit to generate an accumulator output in the high precision intermediate format; and a down conversion and rounding circuit to down convert and round an output of the second pass as final result in the DP floating-point format.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Jiasheng Chen, Kevin Hurd, Changwon Rhee, Jorge Parra, Fangwen Fu, Theo Drane, William Zorn, Peter Caday, Gregory Henry, Guei-Yuan Lueh, Farzad Chehrazi, Amit Karande, Turbo Majumder, Xinmin Tian, Milind Girkar, Hong Jiang
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Publication number: 20240111539Abstract: Techniques and mechanisms for a processor to determine an operational mode based on metadata for a page table. In an embodiment, an instruction fetch unit of the processor detects a pointer to a next instruction, in a sequence of instructions, which is to be prepared for execution with a core of the processor. Based on the pointer, a page table is identified as including an entry which indicates a location of the instruction. The page table includes, or otherwise corresponds to, metadata which comprises an identifier of an operational mode of the processor. Based on the metadata, the processor is transitioned to the operational mode in preparation for an execution of the instruction. In another embodiment, the operational mode is one of multiple operational modes which each correspond to a different instruction set architecture.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Jason Agron, Andreas Kleen, Rangeen Basu Roy Chowdhury
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Publication number: 20240111590Abstract: An apparatus to facilitate ordered thread dispatch for thread teams is disclosed. The apparatus includes one or more processors including a graphic processor, the graphics processor including a plurality of processing resources, and wherein the graphics processor is to: allocate a thread team local identifier (ID) for respective threads of a thread team comprising a plurality of hardware threads that are to be executed solely by a processing resource of the plurality of processing resources; and dispatch the respective threads together into the processing resource, the respective threads having the thread team local ID allocated.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Biju George, Vasanth Ranganathan, Fangwen Fu, Ben Ashbaugh, Roland Schulz
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Publication number: 20240111925Abstract: Described herein are techniques for automated hardware power optimization via e-graph based automatic RTL exploration. These techniques provide a tool that automatically performs RTL optimization and generates power optimized RTL without requiring design engineers to perform labor and knowledge intensive manual optimizations.Type: ApplicationFiled: December 13, 2023Publication date: April 4, 2024Applicant: Intel CorporationInventors: Samuel Coward, Theo Drane, George A. Constantinides
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Publication number: 20240112973Abstract: Through-glass vias (TGVs) are formed without the use of a planarization step to planarize the TGV fill material after filling holes that extend through a glass layer with the fill material. After the holes are filled with the fill material, the fill material is etched and the glass layer is etched. After etching of the glass is performed, the top and bottom surfaces of the glass layer are recessed relative to the top and bottom surfaces of the fill material in the holes, resulting in formation of fill material stubs. TGV pads are then formed on the fill material stubs. The resulting pads can have protrusions that extend away from a surface of the glass layer. If the TGVs are plated through-holes, a portion of the metal lining the inner wall of a TGV hole can extend past a surface of the glass layer and into a TGV pad.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Jeremy D. Ecton, Gang Duan, Brandon Christian Marin, Suddhasattwa Nad, Srinivas V. Pietambaram
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Publication number: 20240110975Abstract: Methods and apparatus relating to techniques to provide secure remote debugging are described. In an embodiment, a debugging entity generates and transmits a host token to a device via an interface. The interface provides encrypted communication between the debugging entity and the device. The debugging entity generates a session key based at least in part on the host token and a device token. The debugging entity transmits an acknowledgement signal to the device after generation of the session key to initiate a debug session. The debugging entity transmits a debug unlock key to the device to cause the device to be unlocked for the debug session. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Tsvika Kurts, Vladislav Mladentsev, Elias Khoury, Rakesh Kandula, Reuven Elbaum, Boris Dolgunov
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Publication number: 20240111615Abstract: Embodiments described herein are generally directed to the use of sidecars to perform dynamic API contract generation and conversion. In an example, a first sidecar of a source microservice intercepts a first call to a first API exposed by a destination microservice. The first call makes use of a first API technology specified by a first contract and is originated by the source microservice. An API technology is selected from multiple API technologies. The selected API technology is determined to be different than the first API technology. Based on the first contract, a second contract is dynamically generated that specifies an intermediate API that makes use of the selected API technology. A second sidecar of the destination microservice is caused to generate the intermediate API and connect the intermediate API to the first API.Type: ApplicationFiled: December 15, 2023Publication date: April 4, 2024Applicant: Intel CorporationInventors: Marcos Carranza, Cesar Martinez-Spessot, Mateo Guzman, Francesc Guim Bernat, Karthik Kumar, Rajesh Poornachandran, Kshitij Arun Doshi
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Publication number: 20240111090Abstract: A device comprises a substrate and an IC die, which may be a photonic IC. The substrate comprises a first surface, a second surface opposite the first surface, an optical waveguide integral with the substrate, and a hole extending from the first surface to the second surface. The hole comprises a first sidewall. The optical waveguide is between the first surface and the second surface, parallel to the first surface, and comprises a first end which extends to the first sidewall. The IC die is within the hole and comprises a second sidewall and an optical port at the second sidewall. The second sidewall is proximate to the first sidewall and the first end of the optical waveguide is proximate to and aligned with the optical port. The substrate may include a recess to receive another device comprising a socket.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Robert A. May, Tarek Ibrahim, Shriya Seshadri, Kristof Darmawikarta, Hiroki Tanaka, Changhua Liu, Bai Nie, Lilia May, Srinivas Pietambaram, Zhichao Zhang, Duye Ye, Yosuke Kanaoka, Robin McRee
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Publication number: 20240112295Abstract: Shared local registers for thread team processing is described. An example of an apparatus includes one or more processors including a graphic processor having multiple processing resources; and memory for storage of data, the graphics processor to allocate a first thread team to a first processing resource, the first thread team including hardware threads to be executed solely by the first processing resource; allocate a shared local register (SLR) space that may be directly reference in the ISA instructions to the first processing resource, the SLR space being accessible to the threads of the thread team and being inaccessible to threads outside of the thread team; and allocate individual register spaces to the thread team, each of the individual register spaces being accessible to a respective thread of the thread team.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Biju George, Fangwen Fu, Supratim Pal, Jorge Parra, Chunhui Mei, Maxim Kazakov, Joydeep Ray
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Publication number: 20240111691Abstract: Techniques for time-aware remote data transfers. A time may be associated with a remote direct memory access (RDMA) operation in a translation protection table (TPT). The RDMA operation may be permitted or restricted based on the time in the TPT.Type: ApplicationFiled: December 7, 2023Publication date: April 4, 2024Applicant: Intel CorporationInventors: Daniel Christian Biederman, Kenneth Keels, Renuka Vijay Sapkal, Tony Hurson