Abstract: A memory device includes CRC (cyclic redundance check) circuitry to detect CRC errors in write transactions. The CRC circuitry computes CRC for a data block to compare with CRC bits that were computed and sent by the memory controller. The memory device records the pass/fail status of write transactions in an error status register readable by the memory controller. The memory device can trigger the ALERT_n signal in response to an error.

Abstract: This disclosure describes systems, methods, and devices related to decoding low-complexity enhancement video coding (LCEVC) video data. A device may receive a bitstream including a first layer and enhancement layers; decode a video frame of the first layer of the bitstream using a base decoder; up-sample the decoded video frame; decode the video frame of a first enhancement layer using tile-level quantization parameters; generate a first combined intermediate video frame using the up-sampled video frame and the decoded video data of the first enhancement layer; up-sample the first combined intermediate video frame; decode encoded video data of a second enhancement layer; generate a second combined intermediate video frame using the decoded video data of the second enhancement layer and a selected reference frame; and generate a combined output video frame using the first combined intermediate video frame and the second combined intermediate video frame.

Abstract: Memory modules and sockets are disclosed. An example memory module comprises a circuit board, a first row of connection pins disposed along an edge of the circuit board, and a second row of pins disposed adjacent to the first row of pins and further from the edge than the first row of pins.

Abstract: Via structures for hybrid bonding architectures, and methods for making same. The structures include a die with a plurality of conductive contacts arranged at a pitch of less than about 4 microns in a hybrid bonding interface. The first layer of metal is below the plurality of conductive contacts, and a second layer of metal is below the first layer of metal and separated therefrom by an insulating layer. A via structure in the die comprises copper or tungsten and is electrically coupled at a first end to a first conductive contact of the plurality of conductive contacts and electrically coupled at a second end to the second layer of metal. A second conductive contact located sequentially next to the first conductive contact is electrically coupled to the first layer of metal.

Abstract: Disclosed is a technical solution to generate hardware-aware machine learning (ML) model architectures for multiple domains without training. An example apparatus includes at least one memory, machine readable instructions, and processor circuitry to at least one of instantiate or execute the machine readable instructions. The example processor circuitry is to generate multiple candidate architectures for a ML model based on target hardware with which the ML model is to be executed and a search space corresponding to the multiple domains. Additionally, the example processor circuitry is to compute respective composite scores for the multiple candidate architectures, the respective composite scores based on respective latency scores for the multiple candidate architectures.

Abstract: Hardware accelerator designs for neural networks are improved with various approaches to reduce circuit area, improve power consumption, and reduce starvation. Convolutional layers of a neural network may multiply a set of weights with a set of inputs. One example defers two’s complement arithmetic from the parallelized multiplication circuits and completes the two’s complement arithmetic when the results are accumulated. In another example, a multiplication circuit initially multiplies an input by an initial value of the maximum (or minimum) multiplication range before applying the magnitude of a multiplication encoded relative to the multiplication range. In another example, after dimensional reduction earlier in the network hardware, circuitry for a convolutional layer uses a reduced number of convolutional block circuits that are reused across a plurality of clock cycles to apply different subsets of weight channels.

Abstract: Devices and systems with stacked memory, and methods of forming the same, are disclosed herein. In one example, a microelectronic assembly includes a logic die, a stack of memory dies above the logic die, and a passthrough die between the logic die and the stack of memory dies, where the logic die is conductively coupled to the stack of memory dies through the passthrough die.

Abstract: An adapter is provided that includes a first interface to couple to a particular device, where link layer data is to be communicated over the first interface, and a second interface to couple to a physical layer (PHY) device. The PHY device includes wires to implement a physical layer of a link, and the link couples the adapter to another adapter via the PHY device. The second interface includes a data channel to communicate the link layer data over the physical layer, and a sideband channel to communicate sideband messages between the adapter and the other adapter over the physical layer. The adapter is to implement a logical PHY for the link.

Abstract: Embodiments are generally directed to dynamically dividing activations and kernels for improving memory efficiency. An embodiment of a method in a compute engine performing machine learning comprises: receiving, by a convolutional layer of a convolutional neural network (CNN) implemented on the compute engine, a plurality of activation groups contained in an input data, wherein the convolutional layer includes one or more kernel groups and the one or more kernel groups each include a plurality of kernels; determining a plurality of memory efficiency metrics based on the number of activation groups of the plurality of activation groups and the number of kernels of the plurality of kernels; selecting a first optimal number of activation groups and a second optimal number of kernels that are associated with an optimal memory efficiency metric in the plurality of memory efficiency metrics; and performing a convolutional operation on the input data based on the first optimal number and the second optimal number.

Abstract: A system is provided that includes a set of graph processing cores and a set of dense compute cores, where the set of graph processing cores and the set of dense cores are interconnected in a network. The dense compute cores include offload queue circuitry to receive an offload request from the set of graph processing cores to handle dense compute workloads. Memory controllers are also provided in the system for use by the graph processing cores in reading and writing to memory in association with sparse graph applications, the memory controllers enhanced to efficiently handle memory transactions in sparse graph applications.

Abstract: Integrated circuit structures having uniform grid metal gate and trench contact cut, and methods of fabricating integrated circuit structures having uniform grid metal gate and trench contact cut, are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires. A gate electrode is over the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A first dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. A second dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure laterally spaced apart from and parallel with the first dielectric cut plug structure.

Abstract: An apparatus and system of paging using paging early indication (PEI) and subgrouping are described. A fifth generation nodeB (gNB) checks paging information of a UE from a limited paging container of the UE provided from the core network to determine whether PEI/subgrouping information is present. The limited paging container contains paging information of the UE that is provided in the UE capability and is used by a previous gNB. If the paging information of the UE does not indicate the ability of the UE to use PEI and/or subgrouping, the gNB checks the information in the UE capability; if the paging information and the UE capability conflict, the gNB signals the UE to monitor for PEI/Subgrouping. The gNB updates the paging capability with PEI and/or subgrouping support before the UE enters idle mode or inactive state and sends the update to the core network.

Abstract: Methods and apparatus for two-layer Alpha-based buffer management with dynamic RED. A two-layer hierarchical sharing scheme using alpha parameters is provided. A buffer is dynamically shared across upper-level entities, such as hosts, using one set of alpha parameters, then a dynamically-adjusted buffer portion allocated for an upper level entity is shared among its lower level entities (e.g., sub queues) using a separate set of low-level alpha parameters. The memory spaces for the upper- and lower-level entities may be dynamically redistributed. Determinations to drop and/or mark and ECN field of received packets are performed using Dynamic RED, which employs dynamic thresholds and associated dynamic probabilities.

Abstract: Embodiments disclosed herein include electronic packages and methods of assembling such electronic packages. In an embodiment, an electronic package comprises a first layer comprising glass. In an embodiment, conductive pillars are formed through the first layer, and a buildup layer stack is on the first layer. In an embodiment, conductive routing is provided through the buildup layer stack. In an embodiment, a second layer is over a surface of the buildup layer stack opposite from the glass layer.

Abstract: A constant voltage may be used during battery charging to reduce or avoid the formation of a dendrite, such as a stepped constant voltage. For each charging period, each level of the stepped constant voltage may be calculated to ensure a corresponding current level within each period remains below a safe current limit. A voltage transition between any two periods may occur in response to expiration of a predetermined time, or in response to a determination that the current level has fallen below a lower current limit. A current level during each period may be maintained such that the battery heat is maintained below a reference heat level, which may increase battery cycle life (e.g., battery capacity or maximum recharging cycles). The battery heat may be measured directly or indirectly, or may be estimated based on other measured or controlled values.

Abstract: Integrated circuit structures having recessed trench contacts and deep boundary vias are described. For example, an integrated circuit structure includes a plurality of gate lines extending over a plurality of semiconductor nanowire stack channel structures. A plurality of trench contacts extends over a plurality of source or drain structures, where a first one of the plurality of trench contacts has a recess therein. A backside metal routing layer is extending beneath the plurality of gate lines and beneath the plurality of trench contacts. A conductive structure couples the backside metal routing layer to a second one of the one or more of the plurality of trench contacts. The conductive structure includes a pillar portion in contact with the second one of the plurality of trench contacts, the pillar portion on a line portion, the line portion in contact with and extending along the backside metal routing layer.

Abstract: Predictive Failure Analysis (PFA) techniques that are thermal aware can enable the prevention of uncorrectable errors without premature replacement of memory resources with redundant memory resources. In one example, a management controller (such as Baseboard Management Controller (BMC)) can monitor the rate of corrected errors. When the BMC detects that there are too many corrected errors occurring within certain time duration, the BMC can check the temperature and airflow rate of memory modules. Based on temperature data, the BMC can boost the fans and verify the reduction in memory corrected errors. If after multiple retries the rate of corrected error remains same, the BMC can enable memory resource replacement techniques such as SDDC or ADDDC or sparing on the failing memory module.

Abstract: An integrated circuit structure includes a first device, and a second device laterally adjacent to the first device. The first device includes (i) a first source region, and a first source contact including a first conductive material, (ii) a first drain region, and a first drain contact including the first conductive material, and (iii) a first body laterally between the first source region and the first drain region. The second device includes (i) a second source region, and a second source contact including a second conductive material, (ii) a second drain region, and a second drain contact including the second conductive material, and (iii) a second body laterally between the second source region and the second drain region. The first and second conductive materials are compositionally different. The first conductive material induces compressive strain on the first body, and the second conductive material induces tensile strain on the second body.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first substrate; a second substrate; and an array of interconnects electrically coupling the first substrate to the second substrate. In an embodiment, the array of interconnects comprises first interconnects, wherein the first interconnects have a first volume and a first material composition, and second interconnects, wherein the second interconnects have a second volume and a second material composition, and wherein the first volume is different than the second volume and/or the first material composition is different than the second material composition.

Abstract: Systems, apparatuses and methods may provide for technology that determines a selected priority corresponding to a selected region in a microprocessor, determines an adjacent priority corresponding to an adjacent region in the microprocessor, wherein the adjacent region is adjacent to the selected region, and places the adjacent region in a first reduced power state if the selected priority is greater than the adjacent priority and temperature of the selected region is less than a selected temperature threshold associated with the selected region.

Abstract: Systems, methods, and apparatuses for implementing capability-directed array prefetching are described. In certain examples, a hardware processor comprises an execution circuit to execute an instruction that generates a memory access request for an element in memory; a capability management circuit to check a capability for the memory access request, the capability comprising an address field of the element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of an object to which the capability authorizes access; a cache; and a prefetch circuit to prefetch an additional element of the object from the memory to the cache based on the capability checked by the capability management circuit.

Abstract: Examples relate to a concept for providing access to remote memory. A network interface controller apparatus comprises circuitry configured to obtain a memory transaction request with respect to memory of a first host hosting the network interface controller apparatus from a second host. The circuitry is configured to translate the memory transaction request to a cache transaction request. The circuitry is configured to provide the cache transaction request to the first host. The circuitry is configured to obtain a response to the cache transaction request from the first host. The circuitry is configured to provide information on the response to the cache transaction request to the second host.

Abstract: A multi-link device (MLD) apparatus, including at least two transmission queues and first medium access control (MAC) circuitry and second MAC circuitry. The first MAC circuitry and the second MAC circuitry can transmit data of the at least two transmission queues over respective links responsive to receiving a trigger indicating that a transmission opportunity (TXOP) is available on the link corresponding to the respective first MAC circuitry and second MAC circuitry.

Abstract: For example, an apparatus may include a scheduler configured to determine scheduling information to schedule radar transmissions of a radar device during a sequence of radar frames. For example, the scheduler may be configured to determine a burst-based frame setting to schedule a sequence of radar burst transmissions during a radar frame of the sequence of radar frames. In one example, the burst-based frame setting may include a setting of a burst gap duration. In one example, the burst gap duration may include a duration of a burst gap between first and second consecutive radar burst transmissions of the sequence of radar burst transmissions.

Abstract: Technologies for beam expansion for vertically-emitting photonic integrated circuits are disclosed. In the illustrative embodiment, waveguides in a photonic integrated circuit (PIC) die guide light to vertical couplers, which direct the light from the waveguides out of the top surface of the PIC die. A glass microoptic substrate is mounted on the top surface of the PIC die, positioned over the vertical couplers. A mirror in the glass microoptic substrate reflects the light from the vertical couplers to propagate in a direction parallel to the top surface of the PIC die. Another set of mirrors in the glass microoptic substrate focus the light from each waveguide into a collimated beam directed out of the top surface of the glass microoptic substrate.

Abstract: This disclosure describes an apparatus comprising a memory to store downlink (DL) transmission configuration indicator (TCI) state chain information, and a processing circuitry, coupled with the memory, to retrieve the DL TCI state chain information from the memory, wherein the DL TCI state information includes an indication of a source reference signal (RS) for a synchronization signal block (SSB) associated with a physical cell identifier that is different from an identifier of a serving cell, and monitor an SSB based on the DL TCI state chain information.

Abstract: A computing platform comprising a plurality of disaggregated data center resources and an infrastructure processing unit (IPU), communicatively coupled to the plurality of resources, to compose a platform of the plurality of disaggregated data center resources for allocation of microservices cluster.

Abstract: Techniques for tag checking for dynamically repeating memory accesses are described. In an embodiment, an apparatus includes instruction decoder circuitry to decode a single instruction, the single instruction having a format including an opcode field, the single instruction having a first opcode value in the opcode field; and execution circuitry coupled to the instruction decoder circuitry, the execution circuitry to perform operations in response to decoding of the single instruction, the operations including performing repeating memory tag checking operations in connection with repeating memory access operations.

Abstract: An example processor includes vector registers to store sub-matrices of two source matrices and execution circuitry to perform a cross-product matrix multiplication. A decoder interprets an instruction specifying the source matrices and the operation. The execution circuitry multiplies each combination of sub-matrices from the two source matrices-first with first, first with second, second with first, and second with second—to generate four corresponding sub-matrices of a result matrix, which are stored in a third vector register. This architecture enables efficient parallel matrix computations for high-performance processing tasks.

Abstract: Methods and apparatus implementing half width modes in DRAM and doubling of bank resources. DRAM devices, such as LPDDR6 SDRAM dies include multiple memory banks configured in memory groups and include I/O interface circuitry for first and second memory channels. A DRAM device may be selectively operated in a first half-width mode under which DQ lines for a partial memory channel operate as a first half-width DQ data bus. When operated in the first half-width mode, the partial memory channel is enabled to access all the memory banks on the DRAM. The DRAM device may also be selectively operated in a second half-width mode under which DQ lines for first and second partial memory channels operate as independent half-width DQ data buses. In this mode, each partial memory channel enables access to a respective portion of the memory banks.

Abstract: For example, a wireless communication device may be configured to transmit a frame from a sub 10 Gigahertz (GHz) (sub-10 GHz) wireless communication station (STA) of the wireless communication device over a sub-10 GHz wireless communication channel, the frame including beamforming (BF) assistance information corresponding to a millimeterWave (mmWave) STA of the wireless communication device, the BF assistance information including orientation-based information corresponding to the mmWave STA, wherein the orientation-based information corresponding to the mmWave STA is based on an orientation of the mmWave STA; and to communicate by the mmWave STA one or more BF training frames over a mmWave wireless communication channel.

Abstract: Apparatus and method for reducing frame rate lag. For example, a graphics processing apparatus comprises: a plurality of graphics cores to execute shaders to process objects of a graphics scene; a render engine to rasterize the objects and render image frames of the graphics scene in a framebuffer; an artificial intelligence (AI)-based frame generator to detect potential stutter conditions associated with the rendering of one or more of the image frames and to responsively trigger AI-interpolated frame generation to generate one or more AI-interpolated frames between a previously rendered frame and a current frame being rendered, the AI-based frame generator to determine an expected number of AI-interpolated frames to be generated and to configure interpolated distance values for each AI-interpolated frame based on an amount of time to render the previously rendered frame and/or an amount of time to render one or more blocks of the current frame being rendered.

Abstract: A memory module management controller in a memory module includes a reset controller that monitors a reset signal received from a host memory controller in the host system that is communicatively coupled to the memory module. The memory module management controller includes sideband bus control circuitry. The memory module also includes memory integrated circuits (for example, Dynamic Random Access Memory (DRAM)) and a Registering Clock Driver (RCD). The reset signal from the host memory controller can be time multiplexed, a short duration pulse to indicate reset of the sideband bus control circuitry and a long duration pulse to indicate reset of other components in the memory module, for example, memory integrated circuits and/or Registering Clock Driver (RCD).

Abstract: An apparatus and method including: graphics processing cores to execute a mesh shader to process a triangle list associated with a mesh and generate a corresponding tristrip; clipper circuitry to clip the tristrip to a view volume, the clipper circuitry to: read corresponding header data including render target array index (RTAI) and view port index (VPI) values corresponding to a current vertex of the tristrip; perform a vertex cache lookup to determine corresponding RTAI and VPI values associated with a previously processed vertex, if any; read vertex data corresponding to the current vertex from memory and processing with new VPI and RTAI values when the RTAI and VPI values of the current vertex do not match those of a previously processed vertex; and perform clip operations based on previously processed vertex data when the RTAI and VPI values of the current vertex match those of the previously processed vertex.

Abstract: This disclosure describes systems, methods, and devices related to decoding JPEG XS video data. A device may identify a bitstream received from a device, the bitstream encoded using JPEG XS; determine that a first slice of a video frame of the bitstream is located within a region of interest of the video frame; determine that a second slice of the video frame is not located within a region of interest of the video frame; discard the second slice based on the determination that the second slice is not located within a region of interest of the video frame; apply an inverse wavelet transformation to the first slice based on the determination that the first slice is located within a region of interest of the video frame; and generate a reconstructed video frame including the first slice and excluding the second slice.

Abstract: This disclosure describes systems, methods, and devices facilitating Wi-Fi peer-to-peer (P2P) communications in a scheduled basic service set. A device may identify a service period for station devices in a basic service set; transmit a traffic indication map (TIM) to the station devices; transmit a null data packet (NDP) feedback report (NFRP) trigger frame associated with requesting the station devices to request uplink transmissions based on the TIM; identify NDP responses received from the station devices based on the NFRP trigger frame, the NDP responses indicative of requested transmissions; transmit an opportunistic power save (OPS) frame to the station devices; and transmit an indication associated with at least one of the station devices applying multi-user (MU) enhanced distributed channel access (EDCA) following a trigger-based channel access opportunity during the service period or with using a TXOP of the TXOPs for Wi-Fi P2P communications.

Abstract: Examples include techniques for a memory module per row activate counter. The techniques include detecting a row hammer or row disturb condition for a row address at a volatile memory device if an activate count to the row address matches a threshold count. The activate count is maintained by a controller for the memory module. Detection of the row hammer or row disturb condition can cause refresh management actions to mitigate the row hammer or row disturb condition.

Abstract: An example processor executes an instruction having an operand field to indicate a multi-register cross-product matrix multiplication to be performed with the first plurality of sub-matrices and the second plurality of sub-matrices to generate the third plurality of sub-matrices. Execution circuitry execute the instruction, the execution circuitry to generate each sub-matrix of the third plurality of sub-matrices in a corresponding vector register of the third plurality of vector registers by multiplying a sub-matrix in a corresponding vector register of the first plurality of vector registers and a sub-matrix in a corresponding vector register of the second plurality of vector registers.

Abstract: An apparatus and method for progress tracking strided vector loads and stores. For example, an example method comprises: decoding a progress tracking strided load instruction including fields to indicate a destination vector register in which to load source data elements, memory locations of the source data elements, and a register to store a progress indication; initiating execution of the progress tracking strided load instruction; loading one or more of the source data elements to corresponding locations in the destination vector register; updating the progress indication in accordance with the one or more source data elements loaded or a next source data element to be loaded; and in response to an interruption of the execution of the progress tracking strided load instruction, re-starting the execution of the instruction from an execution point based on the progress indication.

Abstract: Methods and apparatus to manufacture a coupled inductor are disclosed. An example coupled inductor includes a base of a magnetic core including a first channel and a second channel extending between first and second sides of the base, the first channel spaced apart from the second channel, a third channel of the base extending transverse to the first and second channels, a first conductive wire positioned in the base, a first portion of the first conductive wire positioned in the first channel, a second portion of the first conductive wire positioned in the second channel, a third portion of the first conductive wire positioned in the third channel, and a first portion of a second conductive wire positioned in the first channel, a second portion of the conductive wire positioned in the second channel, a third portion of the second conductive wire positioned in the third channel.

Abstract: Systems, apparatuses, methods, and computer-readable media are provided to address SRS configuration and transmission in the scenario of multi-DCI multi-TRP operation. Other embodiments may be described and/or claimed.

Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a substrate having a surface; a die having a first surface and an opposing second surface, wherein the first surface of the die is coupled to the surface of the substrate by interconnects, and wherein the second surface of the die has a roughness between 100 nanometers and 500 nanometers; a cooling apparatus thermally coupled to the second surface of the die; and a material between the second surface of the die and the cooling apparatus. In some embodiments, the material includes a thermal interface material. In some embodiments, the material includes a solder-based thermal interface material in direct contact with the second surface of the die and with the cooling apparatus.

Abstract: Embodiments described herein are generally directed to selective multithreaded execution of memory training by CPU sockets. In an example, a memory configuration and a current phase of execution of memory training for each of multiple CPU sockets of a computer system is received. Based on the memory configuration and the current phase of execution of each of the CPU sockets an estimated power usage across all CPU sockets may be determined. Based on the estimated power usage and a power consumption threshold (e.g., PTAM or PA), performance of the current phase of execution of one or more CPU sockets may be selectively released for one or more channels of the one or more CPU sockets.

Abstract: Thermally compensated waveguides are disclosed herein. According to one aspect, the present disclosure proposes new ways to combine negative TOC (NTOC) material layers within the waveguides. NTOC materials can be implemented in one or more of a cladding layer, a core rib/channel waveguide, a horizontally segmented waveguide, a vertically segmented waveguide, a sub-wavelength grating structure, and/or in various other waveguide structure implementations including arbitrary core or cladding shapes. The integration of NTOC materials improves the temperature dependence of the waveguide spectrum. The need for fast and efficient optical-based technologies is increasing as Internet data traffic growth rate is overtaking voice traffic, pushing the need for optical communications.

Abstract: Optical connectors with alignment features, and methods of forming the same, are disclosed herein. In one example, an optical ferrule includes holes to couple a fiber array to the optical ferrule, a mating protrusion to mate with an optical receptacle, and alignment features to align the fiber array with optical waveguides in the optical receptacle. The optical receptacle includes the optical waveguides, a mating cavity to mate with the mating protrusion on the optical ferrule, and alignment features to mate with the alignment features on the optical ferrule.

Abstract: An apparatus and system of establishing a Transmission Configuration Indication (TCI) state switch delay are described. The TCI state switch delay for a reference signal (RS) on a component carrier (CC) in intra-band carrier aggregation (CA) is dependent on whether a TCI state indicated in the DCI is known based on a type of Quasi Co-Location (QCL) and whether a common TCI state ID is known on the CC. The delay is known for a delay of QCL-typeD RS on the CC or any other QCL-typeD RS in the CC set that contains the CC. The delay may be based on that of a single CC delay, with the slot where the new TCI state applies determined based on a carrier with a smallest subcarrier spacing (SCS) in the CC or the CC set.

Abstract: Example methods and systems for multi-skeleton tracking in reconstructions of a volumetric scene are disclosed. Measured skeletons are derived from multiple video streams and compared with predicted skeletons generated by a Kalman filter that incorporates historical pose data. A temporal object key point loss metric quantifies the difference between measured and predicted skeletons over time. Loss values form a cost matrix processed by a Hungarian assignment algorithm to match measured skeletons with predicted identities, providing stable player IDs, jersey numbers and team information. The matched skeletons are updated and predicted for subsequent frames, enabling real time virtual viewpoints, point of view views, and other immersive visualizations.

Abstract: This disclosure describes systems, methods, and devices related to good cell criteria. A device may establish a relaxation criteria for radio link monitoring (RLM) and beam failure detection (BFD). The device may utilize the relaxation criteria to assist a user equipment (UE) to enter or exit a relaxed condition. The device may apply a relaxation threshold to both RLM and BFD, wherein the relaxation threshold is based on a signal to noise ratio (SNR) of at least one reference signal (RS).

Abstract: A system can be designed with memory to operate in a low temperature environment. The low temperature memory can be customized for low temperature operation, having a gate stack to adjust a work function of the memory cell transistors to reduce the threshold voltage (Vth) relative to a standard memory device. The reduced temperature can improve the conductivity of other components within the memory, enabling increased memory array sizes, fewer vertical ground channels for stacked devices, and reduced operating power.

Abstract: Various aspects of an object weight estimation system are described, to enable weight estimation of an object to be transferred from an object source (e.g., a human or an ambulatory robot) that holds the object using one or more arms. One technique includes: tracking an object to be transferred from the object source to a robot; identifying, from at least one image captured by the robot, a posture of the object source; identifying respective segments of the object source from the posture of the object source; determining an estimated weight of the object based on a center of gravity of the object source, as the center of gravity of the object source is calculated in real-time from a balance of the respective segments; and causing a responsive action with the robot, based on the estimated weight of the object.