Intel Patents

Intel Corporation designs and manufactures microprocessors and chipsets for computing and communications equipment manufacturers. Its products may be found in desktops, servers, tablets, smartphones and other devices.

Intel Patents by Type

  • Intel Patents Granted: Intel patents that have been granted by the United States Patent and Trademark Office (USPTO).
  • Intel Patent Applications: Intel patent applications that are pending before the United States Patent and Trademark Office (USPTO).
  • Publication number: 20190089939
    Abstract: Described are mechanisms for depth sensor optimization based on detected distances. The mechanisms may comprise a distance measurement module, which may be operable to measure a physical distance between a 3D camera sensor and a person or object in view of the 3D camera. The mechanisms may also comprise a sensor mode selector module, which may be operable to select a best camera sensor configuration based on a measured distance from a distance-measurement module.
    Type: Application
    Filed: September 18, 2017
    Publication date: March 21, 2019
    Applicant: Intel Corporation
    Inventor: Yen Hsiang Chew
  • Publication number: 20190089940
    Abstract: An example system for generating stereoscopic light field panoramas includes a receiver to receive a plurality of synchronized images. The system also includes a calibrator and projector to calibrate the synchronized images, undistort the synchronized images, and project the undistorted images to a sphere to generate undistorted rectilinear images. The system further includes a disparity estimator to estimate a disparity between neighboring views of the undistorted rectilinear images to determine an optical flow between the undistorted rectilinear images. The system includes a view interpolator to perform in-between view interpolation on the undistorted rectilinear images based on the optical flow. The system also further includes a light field panorama generator to generate a stereoscopic light field panorama for a plurality of perspectives using concentric viewing circles.
    Type: Application
    Filed: September 15, 2017
    Publication date: March 21, 2019
    Applicant: INTEL CORPORATION
    Inventors: Fan Zhang, Oscar Nestares
  • Publication number: 20190086994
    Abstract: An first apparatus is provided which comprises: a first port coupled to a second port of a second apparatus; first one or more circuitries to monitor current of a power bus that is to supply power from the first port to the second port; and second one or more circuitries to: while the first port is to operate in a high-current mode of operation, determine that the current of the power bus is less than a threshold current; and cause the first port to enter a suspend mode of operation from the high-current mode of operation, in response to the current of the power bus being less than the threshold current.
    Type: Application
    Filed: September 19, 2017
    Publication date: March 21, 2019
    Applicant: Intel Corporation
    Inventors: Rajaram Regupathy, Abdul R. Ismail
  • Publication number: 20190086727
    Abstract: In some examples, display backlight strings are grouped into at least two groups based on characteristics of the display backlight strings. A first of the at least two groups of display backlight strings is operated at a first operating voltage. A second of the at least two groups of display backlight strings is operated at a second operating voltage.
    Type: Application
    Filed: September 21, 2017
    Publication date: March 21, 2019
    Applicant: INTEL CORPORATION
    Inventors: Vijayakumar A. Dibbad, Mallari C. Hanchate
  • Publication number: 20190089582
    Abstract: An apparatus is provided which comprises: a plurality of data routers to route data packets, wherein the plurality of data routers comprises: a first data router comprising a trace port, and a second data router coupled to a component; and one or more trace routers to route trace information of the apparatus, wherein a first trace router of the one or more trace routers is coupled to the trace port, and wherein the first trace router is to route configuration information from the component to the trace port, the configuration information to configure the trace port.
    Type: Application
    Filed: September 19, 2017
    Publication date: March 21, 2019
    Applicant: Intel Corporation
    Inventors: Simona Bernardi, Helmut Reinig, Todor M. Mladenov
  • Publication number: 20190087690
    Abstract: Techniques related to implementing an always on face detection architecture at ultra low power are discussed. Such techniques include updating a face detection model at a host processor using positive and/or negative validation of face detection results from an always on microcontroller operating at ultra low power.
    Type: Application
    Filed: November 21, 2018
    Publication date: March 21, 2019
    Applicant: Intel Corporation
    Inventor: Charu Srivastava
  • Publication number: 20190089966
    Abstract: A method for efficient frame loss recovery and reconstruction (EFLRR) in a dyadic hierarchy is described herein. The method includes obtaining a current frame of a group of pictures. The method also includes calculating a Dyadic Hierarchy Picture Index difference based on a layer information in response to a prior frame missing in the group of pictures. Finally, the method includes decoding the current frame in response to a determined frame continuity based on the Dyadic Hierarchy Picture Index difference.
    Type: Application
    Filed: September 21, 2017
    Publication date: March 21, 2019
    Applicant: INTEL CORPORATION
    Inventors: Prasanna Kumar Mandapadi Ramasubramanian, Rajesh Poornachandran, Sri Ranjan Srikantam
  • Publication number: 20190086679
    Abstract: An example apparatus for displaying stereo elemental images includes two coupled eyepieces. Each of the two eyepieces also includes a curved screen to display a number of elemental images. Each of the two eyepieces also includes a curved lens array concentrically displaced in front of the curved screen to magnify the elemental images. Each of the number of elemental images is magnified by a different lens in the curved lens array.
    Type: Application
    Filed: September 19, 2017
    Publication date: March 21, 2019
    Applicant: INTEL CORPORATION
    Inventors: Joshua J. Ratcliff, Alexey M. Supikov, Santiago E. Alfaro, Basel Salahieh
  • Publication number: 20190087729
    Abstract: Systems and methods are provided that tune a convolutional neural network (CNN) to increase both its accuracy and computational efficiency. In some examples, a computing device storing the CNN includes a CNN tuner that is a hardware and/or software component that is configured to execute a tuning process on the CNN. When executing according to this configuration, the CNN tuner iteratively processes the CNN layer by layer to compress and prune selected layers. In so doing, the CNN tuner identifies and removes links and neurons that are superfluous or detrimental to the accuracy of the CNN.
    Type: Application
    Filed: September 18, 2017
    Publication date: March 21, 2019
    Applicant: Intel Corporation
    Inventors: Seok-Yong Byun, Byungseok Roh, Minje Park, Byoungwon Choe
  • Publication number: 20190087341
    Abstract: In one embodiment, a processor comprises a first prefetcher to generate prefetch requests to prefetch data into a mid-level cache; a second prefetcher to generate prefetch requests to prefetch data into the mid-level cache; and a prefetcher selector to select a prefetcher configuration for the first prefetcher and the second prefetcher based on at least one memory access metric, wherein the prefetcher configuration is to specify whether the first prefetcher is to be enabled to issue, to the mid-level cache, prefetch requests for data of a particular page and whether the second prefetcher is to be enabled to issue, to the mid-level cache, prefetch requests for data of the particular page.
    Type: Application
    Filed: September 19, 2017
    Publication date: March 21, 2019
    Applicant: INTEL CORPORATION
    Inventors: Seth H. Pugsley, Manjunath Shevgoor, Christopher B. Wilkerson
  • Publication number: 20190087925
    Abstract: Systems, apparatuses and methods of monitoring the utilization of protective equipment by individuals requesting access to a restricted area that requires the use of specific protective equipment, are provided. A protective equipment checker, which includes a proximity sensor, a three-dimensional (3D) camera, and a radio-frequency identification (RFID) reader, performs a full body scan on the individual to determine if the location-specific protective equipment is being worn, or is in the possession of the individual. If a determination is made that the proper protective equipment is being worn, the individual is granted access to the location. If, one the other hand, the required protective equipment is not being worn, entry to the location is denied.
    Type: Application
    Filed: March 25, 2016
    Publication date: March 21, 2019
    Applicant: Intel Corporation
    Inventors: Elizabeth Stortstrom, Andrew Larson, Mark E. Sprenger, Ralph V. Miele
  • Publication number: 20190087374
    Abstract: An embodiment of an extensible memory hub may include one or more upstream interface ports to couple the extensible memory hub to the controller, one or more downstream interface ports to couple the extensible memory hub to one or more of the nonvolatile memory and another extensible memory hub, and a clock circuit to provide a first clock signal at a first frequency to the one or more upstream interface ports and a second clock signal at a second frequency to the one or more downstream interface ports, where the first frequency may be different from the second frequency. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: November 15, 2018
    Publication date: March 21, 2019
    Applicant: Intel Corporation
    Inventors: Jawad Khan, Knut Grimsrud
  • Publication number: 20190087008
    Abstract: A mechanism to provide visual feedback regarding computing system command gestures. An embodiment of an apparatus includes a sensing element to sense a presence or movement of a user of the apparatus, a processor, wherein operation of the processor includes interpretation of command gestures of a user to provide input to the apparatus; and a display screen, the apparatus to display one or more icons on the display screen, the one or more icons being related to the operation of the apparatus. The apparatus is to display visual feedback for a user of the apparatus, visual feedback including a representation of one or both hands of the user while the one or both hands are within a sensing area for the sensing element.
    Type: Application
    Filed: November 30, 2015
    Publication date: March 21, 2019
    Applicant: INTEL CORPORATION
    Inventors: RAJIV MONGIA, ACHINTYA K. BHOWMIK, MARK H. YAHIRO, DANA KRIEGER, ED MAGNUM, DIANA POVIENG
  • Publication number: 20190089957
    Abstract: Techniques related to coding video using adaptive quantization rounding offsets for use in transform coefficient quantization are discussed. Such techniques may include determining the value of a quantization rounding offset for a picture of a video sequence based on evaluating a maximum coding bit limit of the picture, a quantization parameter of the picture, and parameters corresponding to the video.
    Type: Application
    Filed: November 19, 2018
    Publication date: March 21, 2019
    Applicant: Intel Corporation
    Inventors: Ximin Zhang, Sang-hee Lee, Keith W. Rowe
  • Publication number: 20190088773
    Abstract: There is disclosed in an example, a gallium nitride (GaN) field effect transistor (FET) having a gate, a drain, and a source, having: a doped GaN buffer layer; a first epitaxy layer above the buffer layer, the first epitaxy layer having a first doping profile (for example, doped, or p-type doping); and a second epitaxy layer above the first epitaxy layer, the second epitaxy layer having a second doping profile (for example, undoped, or n-type doping).
    Type: Application
    Filed: March 22, 2016
    Publication date: March 21, 2019
    Applicant: Intel Corporation
    Inventors: Mark Armstrong, Han Wui Then
  • Publication number: 20190087999
    Abstract: An apparatus to facilitate pixel compression is disclosed. The apparatus includes a rasterizer module to convert an image to a plurality of pixels, an interface coupled to the rasterizer module, a depth check module coupled to the interface and compression logic to perform a compression encoding on the plurality of pixels, including dividing the plurality of pixels into a mega pixel block having a plurality of pixel blocks, determining coverage information for pixels in each of the plurality of pixel blocks, encoding each of the plurality of pixel blocks based on the coverage information to generate a mega encoded block.
    Type: Application
    Filed: September 20, 2017
    Publication date: March 21, 2019
    Applicant: Intel Corporation
    Inventors: Subramaniam Maiyuran, Jorge Garcia Pabon, Vasanth Ranganathan, Saikat Mandal, Karol Szerszen, Luis Cruz Camacho, Abhishek R. Appu, Joydeep Ray
  • Publication number: 20190089446
    Abstract: Technologies described herein provide mechanisms and formats to accomplish the beam switching. In one implementation, least one frame structure for both uplink (UL) and downlink (DL) beam switching is provided. The UL beam switching and refinement may rely on 5G Physical Random Access Channel (xPRACH) or 5G Sounding Reference Signal (xSRS). The DL beam switching and refinement may be done based on a beam refinement reference signal (BRRS). In some embodiments, to accomplish the both UL and DL beam switching and refinement in one subframe, the BRRS and xPRACH or xSRS may be located in one subframe.
    Type: Application
    Filed: July 1, 2016
    Publication date: March 21, 2019
    Applicant: INTEL IP CORPORATION
    Inventors: Yushu ZHANG, Wenting CHANG, Yuan ZHU, Gang XIONG, Bishwarup MONDAL
  • Publication number: 20190089409
    Abstract: Embodiments may relate to a transceiver chip. The transceiver chip may include a substrate that has a first transceiver component and a second transceiver component positioned therein. The transceiver chip may further include a well material that is positioned between the first transceiver component and the second transceiver component. The well material may mitigate cross-talk between the first transceiver component and the second transceiver component. Other embodiments may be described or claimed.
    Type: Application
    Filed: November 20, 2018
    Publication date: March 21, 2019
    Applicant: Intel Corporation
    Inventors: Telesphor Kamgaing, Georgios Dogiamis, Henning Braunisch, Hyung-Jin Lee, Richard Dischler
  • Publication number: 20190088538
    Abstract: In an example, there is disclosed a chemical compound, including a transition metal, a post-transition metal, a metalloid, and a nonmetal. By way of non-limiting example, the post-transition metal may be aluminum. The transition metal is selected from the group consisting of tungsten, tantalum, hafnium, molybdenum, niobium, zirconium, vanadium, and titanium. The metalloid may be boron or silicon. The nonmetal may be carbon or nitrogen. The compound may be used, for example, as a barrier material in an integrated circuit.
    Type: Application
    Filed: March 31, 2016
    Publication date: March 21, 2019
    Applicant: Intel Corporation
    Inventors: Daniel J. Zierath, Jason A. Farmer, Daniel B. Bergstrom
  • Publication number: 20190087717
    Abstract: One embodiment provides a four stable state neuron. The four stable state neuron includes a plurality of input elements and a plurality of coupling channels. Each input element is coupled to a respective coupling channel and each input element is to scale a respective two-dimensional input signal by a weight. The four stable state neuron further includes a first output element coupled to the plurality of coupling channels. The first output element is to receive the plurality of weighted two-dimensional input signals and to generate a two-dimensional output signal based, at least in part, on a threshold value.
    Type: Application
    Filed: April 1, 2016
    Publication date: March 21, 2019
    Applicant: Intel Corporation
    Inventors: Sasikanth Manipatruni, Ian A. Young, Dmitri E. Nikonov
  • Publication number: 20190088759
    Abstract: Techniques are disclosed for transistor gate trench engineering to decrease capacitance and resistance. Sidewall spacers, sometimes referred to as gate spacers, or more generally, spacers, may be formed on either side of a transistor gate to help lower the gate-source/drain capacitance. Such spacers can define a gate trench after dummy gate materials are removed from between the spacers to form the gate trench region during a replacement gate process, for example. In some cases, to reduce resistance inside the gate trench region, techniques can be performed to form a multilayer gate or gate electrode, where the multilayer gate includes a first metal and a second metal above the first metal, where the second metal includes lower electrical resistivity properties than the first metal. In some cases, to reduce capacitance inside a transistor gate trench, techniques can be performed to form low-k dielectric material on the gate trench sidewalls.
    Type: Application
    Filed: April 1, 2016
    Publication date: March 21, 2019
    Applicant: INTEL CORPORATION
    Inventors: SEUNG HOON SUNG, WILLY RACHMADY, JACK T. KAVALIEROS, HAN WUI THEN, MARKO RADOSAVLJEVIC
  • Publication number: 20190089036
    Abstract: Embodiments may relate to a dielectric waveguide that includes a substrate and a waveguide material disposed within the substrate. The dielectric waveguide may further include a waveguide launcher electromagnetically and physically coupled with the waveguide material, wherein the waveguide launcher is exposed at a side of the dielectric substrate. Other embodiments may be described or claimed.
    Type: Application
    Filed: November 15, 2018
    Publication date: March 21, 2019
    Applicant: Intel Corporation
    Inventors: Telesphor Kamgaing, Georgios Dogiamis, Aleksandar Aleksov, Gilbert W. Dewey, Hyung-Jin Lee
  • Publication number: 20190088004
    Abstract: A system, article, and method of 3D reconstruction with volume-based filtering for image processing.
    Type: Application
    Filed: November 19, 2018
    Publication date: March 21, 2019
    Applicant: Intel Corporation
    Inventors: Blake Lucas, Rita Brugarolas Brufau
  • Publication number: 20190088005
    Abstract: An example system for lightweight view dependent rendering is described herein. The system includes a processor configured to determine a moving region of each camera view, wherein the moving region is defined by a bounding box and track each moving region to obtain a plurality of cropped videos for each camera view. The system may also be configured to generate a billboard for each camera view and render each billboard.
    Type: Application
    Filed: November 15, 2018
    Publication date: March 21, 2019
    Applicant: INTEL CORPORATION
    Inventor: Blake Lucas
  • Publication number: 20190088269
    Abstract: A system, article, and method of acoustic dereverberation factoring the actual non-ideal acoustic environment.
    Type: Application
    Filed: November 20, 2018
    Publication date: March 21, 2019
    Applicant: Intel IP Corporation
    Inventors: Shmuel Markovich Golan, Alejandro Cohen
  • Patent number: 10234920
    Abstract: In one embodiment, a processor includes: at least one core to execute instructions; a power controller to control power consumption of the processor; and a storage to store a plurality of entries to associate a dynamic capacitance with a time duration for which a current spike is to be exposed to a power delivery component. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Avinash N. Ananthakrishnan, Jorge P. Rodriguez
  • Patent number: 10234956
    Abstract: Processing techniques and device configurations for performing and controlling output effects at a plurality of wearable devices are generally described herein. In an example, a processing technique may include receiving, at a computing device, an indication of a triggering gesture that occurs at a first wearable device, determining an output effect corresponding to the indication of the triggering gesture, and in response to determining the output effect, transmitting commands to computing devices that are respectively associated with a plurality of wearable devices, the commands causing the plurality of wearable devices to generate the output effect at the plurality of wearable devices. In further examples, output effects such as haptic feedback, light output, or sound output, may be performed by the plurality of wearable devices, associated computing devices, or other controllable equipment.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Saurin Shah, Narayan Sundararajan, Manan Goel, Brian K. Vogel, Jason Blanchard, Jason Wright, Lakshman Krishnamurthy, Swarnendu Kar
  • Patent number: 10235128
    Abstract: An embodiments of a contextual sound apparatus may include a sound identifier to identify a sound, a context identifier to identify a context, and an action identifier communicatively coupled to the sound identifier and the context identifier to identify an action based on the identified sound and the identified context. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Robert L. Vaughn, James B. Eynard
  • Patent number: 10236233
    Abstract: Embodiments of heat spreaders with integrated preforms, and related devices and methods, are disclosed herein. In some embodiments, a heat spreader may include: a frame formed of a metal material, wherein the metal material is a zinc alloy or an aluminum alloy; a preform secured in the frame, wherein the preform has a thermal conductivity higher than a thermal conductivity of the metal material; and a recess having at least one sidewall formed by the frame. The metal material may have an equiaxed grain structure. In some embodiments, the equiaxed grain structure may be formed by squeeze-casting or rheocasting the metal material.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Aravindha R. Antoniswamy, Thomas J. Fitzgerald
  • Patent number: 10234833
    Abstract: Technologies for predicting the power usage of a data center are disclosed. A data center manager gathers sensor data from the compute devices of the data center. The sensor data indicates factors such as power used by the compute device and the intake air inlet temperature. The data center manager trains a machine-learning-based algorithm based on training sensor data, and then applies the machine-learning-based algorithm to sensor data as it is being gathered. The machine-learning-based algorithm can predict a change in future power usage of the data center, and control a cooling unit to compensate before the power usage even begins to change.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Nishi Ahuja, Rahul Khanna, Abishai Daniel, Zhijie Sheng
  • Patent number: 10235794
    Abstract: An embodiment of a parallel processor apparatus may include a sample pattern selector to select a sample pattern for a pixel, and a sample pattern subset selector communicatively coupled to the sample pattern selector to select a first subset of the sample pattern for the pixel corresponding to a left eye display frame and to select a second subset of the sample pattern for the pixel corresponding to a right eye display frame, wherein the second subset is different from the first subset. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Nikos Kaburlasos, Joydeep Ray, John H. Feit, Travis T. Schluessler, Jacek Kwiatkowski, Philip R. Laws
  • Patent number: 10235486
    Abstract: In one embodiment, a design tool for designing a system on chip (SoC) includes hardware logic to generate one or more configuration files for a fabric of a SoC to be designed by the design tool. This logic is configured, based at least in part on user input, to generate the one or more configuration files, according to at least one of: automatic derivation of all parameters of the fabric, according to a first user selection; manual input by a user of at least some parameters of the fabric and automatic derivation of at least other parameters of the fabric, according to a second user selection; and manual input by the user of the all parameters of the fabric, according to a third user selection. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Krishnan Srinivasan, Robert P. Adler, Robert De Gruijl, Jay Tomlinson, Eric A. Geisler
  • Patent number: 10235732
    Abstract: A method and system are described herein for an optimization technique on two aspects of thread scheduling and dispatch when the driver is allowed to pick the scheduling attributes. The present techniques rely on an enhanced GPGPU Walker hardware command and one dimensional local identification generation to maximize thread residency.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: March 19, 2019
    Assignee: INTEL CORPORATION
    Inventors: Jayanth N. Rao, Michal Mrozek
  • Patent number: 10235735
    Abstract: An embodiment of a graphics apparatus may include a tile candidate identifier to determine if a compute kernel is a tile candidate, and a compute kernel tiler communicatively coupled to the tile candidate identifier to tile the compute kernel if the compute kernel is determined to be a tile candidate. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Abhishek Venkatesh, Prasoonkumar Surti, Slawomir Grajewski, Louis Feng, Kai Xiao, Tomasz Janczak, Devan Burke, Travis T. Schluessler
  • Patent number: 10235811
    Abstract: An embodiment of a graphics processor pipeline apparatus may include a vertex fetcher to fetch vertices, a vertex shader communicatively coupled to the vertex fetcher to shade the fetched vertices, a primitive assembler communicatively coupled to the vertex shader to assemble primitives, and a primitive replicator communicatively coupled to the primitive assembler to replicate primitives for at least a first and a second viewport.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Kalyan K. Bhiravabhatla, Subramaniam Maiyuran, Robert M. Toth, Tomasz Janczak
  • Patent number: 10235175
    Abstract: A processor of an aspect includes a plurality of logical processors. A first logical processor of the plurality is to execute software that includes a memory access synchronization instruction that is to synchronize accesses to a memory. The processor also includes memory access synchronization relaxation logic that is to prevent the memory access synchronization instruction from synchronizing accesses to the memory when the processor is in a relaxed memory access synchronization mode.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Martin G. Dixon, William C. Rash, Yazmin A. Santiago
  • Patent number: 10235302
    Abstract: In an embodiment, a processor for invalidating cache entries comprises: at least one processing unit; a processor cache; and direct cache unit. The direct cache unit is to receive, from a first device, a direct read request for data in a first cache entry in the processor cache; determine whether the direct read request is an invalidating read request; in response to a determination that the direct read request is an invalidating read request: send the data in the first cache entry directly from the processor cache to the first device without accessing a main memory; and invalidate the first cache entry in the processor cache. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Samantha J. Edirisooriya, Geetani R. Edirisooriya
  • Patent number: 10235171
    Abstract: An apparatus includes a first circuit to determine a real program order (RPO) of an eldest undispatched instruction from among a plurality of strands, a second circuit to determine an RPO limit based on a delta value and the RPO of the eldest undispatched instruction, an ordering buffer to store entries for instructions that are waiting to be retired, and a third circuit to execute an orderable instruction from a strand from the plurality of strands to cause an entry for the orderable instruction to be inserted into the ordering buffer in response to a determination that an RPO of the orderable instruction is less than or equal to the RPO limit.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: March 19, 2019
    Assignee: INTEL CORPORATION
    Inventors: Alexander Y. Ostanevich, Jayesh Iyer, Sergey P. Scherbinin, Dmitry M. Maslennikov, Denis G. Motin, Alexander V. Ermolovich, Andrey Chudnovets, Sergey A. Rozhkov, Boris A. Babayan
  • Patent number: 10235180
    Abstract: A scheduler implementing a dependency matrix having restricted entries is disclosed. A processing device of the disclosure includes a decode unit to decode an instruction and a scheduler communicably coupled to the decode unit. In one embodiment, the scheduler is configured to receive the decoded instruction, determine that the decoded instruction qualifies for allocation as a restricted reservation station (RS) entry type in a dependency matrix maintained by the scheduler, identify RS entries in the dependency matrix that are free for allocation, allocate one of the identified free RS entries with information of the decoded instruction in the dependency matrix, and update a row of the dependency matrix corresponding to the claimed RS entry with source dependency information of the decoded instruction.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Srikanth T. Srinivasan, Matthew C. Merten, Bambang Sutanto, Rahul R. Kulkarni, Justin M. Deinlein, James D. Hadley
  • Patent number: 10235177
    Abstract: In an example, an apparatus includes a binary translator (BT) including circuitry to: analyze a code block; determine that an architectural register mapped to a physical register in the physical register file is available for early reclamation; and insert a reclamation hint into the code block. In another example, a processor reclaims the physical register based at least in part on the reclamation hint.
    Type: Grant
    Filed: July 2, 2016
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Vineeth Mekkat, Janghaeng Lee, Youfeng Wu
  • Patent number: 10236001
    Abstract: Techniques for passive enrollment of a user in a speaker identification (ID) device are provided. One technique includes: parsing, by a processor of the speaker ID device, a speech sample, spoken by the user, into a keyword phrase sample and a command phrase sample; identifying, by a text-dependent speaker ID circuit of the speaker ID device, the user as the speaker of the keyword phrase sample; associating the command phrase sample with the identified user; determining if the command phrase sample in conjunction with one or more earlier command phrase samples associated with the user is sufficient command phrase sampling to enroll the user in a text-independent speaker ID circuit of the speaker ID device; and enrolling the user in the text-independent speaker ID circuit using the command phrase samples associated with the user after determining there is sufficient command phrase sampling to enroll the user.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: March 19, 2019
    Assignee: INTEL CORPORATION
    Inventor: David Pearce
  • Patent number: 10235301
    Abstract: Generally, this disclosure provides systems, methods and computer readable media for a page table edit controller configured to control access to guest page tables by virtual machine (VM) guest software through the manipulation of extended page tables. The system may include a translation look-aside buffer (TLB) to maintain a policy to lock one or more guest linear addresses (GLAs) to one or more allowable guest physical addresses (GPAs); a page walk processor to update the TLB based on the guest page tables; and a page table edit control (PTEC) module to: identify entries of the guest page tables that map GLAs associated with the policy to a first GPA; verify that the mapping conforms to the policy; and place the guest page table into one of a plurality of restricted accessibility states based on the verification, the restricted accessibility applied to the VM guests and to the page walk processor.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: March 19, 2019
    Assignee: INTEL CORPORATION
    Inventors: Michael Lemay, David M. Durham, Andrew V. Anderson, Gilbert Neiger, Ravi L. Sahita
  • Patent number: 10234930
    Abstract: In an embodiment, a processor includes: a plurality of first cores to independently execute instructions, each of the plurality of first cores including a plurality of counters to store performance information; at least one second core to perform memory operations; and a power controller to receive performance information from at least some of the plurality of counters, determine a workload type executed on the processor based at least in part on the performance information, and based on the workload type dynamically migrate one or more threads from one or more of the plurality of first cores to the at least one second core for execution during a next operation interval. Other embodiments are described and claimed.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Victor W. Lee, Edward T. Grochowski, Daehyun Kim, Yuxin Bai, Sheng Li, Naveen K. Mellempudi, Dhiraj D. Kalamkar
  • Patent number: 10235304
    Abstract: Embodiments of apparatus, method, and storage medium associated with MCCG memory integrity for securing/protecting memory content/data of VM or enclave are described herein. In some embodiments, an apparatus may include one or more encryption engines to encrypt a unit of data to be stored in a memory in response to a write operation from a VM or an enclave of an application, prior to storing the unit of data into the memory in an encrypted form; wherein to encrypt the unit of data, the one or more encryption engines are to encrypt the unit of data using at least a key domain selector associated with the VM or enclave, and a tweak based on a color within a color group associated with the VM or enclave. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: October 1, 2016
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: David M. Durham, Siddhartha Chhabra, Serge J. Deutsch, Michael E. Kounavis, Alpa T. Narendra Trivedi
  • Patent number: 10235327
    Abstract: A system and method is described for simplifying implementation of repeater (e.g., re-driver/re-timer) module implementation in high-data-rate interconnects that carry a relatively low-data-rate clock signal as well as the data stream (e.g., PCIe). At the endpoint, any information critical to the function of the repeater (e.g., the most recent data rate negotiated by a pair of endpoints communicating through the repeater) is embedded in the clock signal by pulse-width modulation as ordered sets. The repeater only needs to read the clock-embedded information rather than decoding the data stream. Thus repeaters for such applications reconstruct the high-rate data-stream while actually decoding only the low-rate clock signal. Because the clock-signal protocol is independent of the data-stream protocol, the repeater's operation is protocol-agnostic with respect to the data-stream.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: March 19, 2019
    Assignee: INTEL CORPORATION
    Inventors: Huimin Chen, Duane G. Quiet
  • Patent number: 10236076
    Abstract: Methods and apparatus for predictable protocol aware testing on a memory interface are are shown. An apparatus to support a protocol aware testing on a memory interface may include a digital controller to receive a plurality of read request commands from a unit under test. The digital controller further to hold the plurality of read request commands while a hold signal has a first value, and to sequentially release individual read request commands of the plurality of read request commands while to the hold signal has a second value. The digital controller further to provide input/output (I/O) commands to an output based on a particular released read request command of the plurality of read request commands. Timing of provision of the I/O commands is deterministic based on a transition of the hold signal from the first value to the second value.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Wei Ming Lim, Madhu Rao, Alvin Shing Chye Goh, Kim Leong Lee, Terrence Huat Hin Tan, Vui Yong Liew, Yah Chen Chew
  • Patent number: 10235526
    Abstract: Various embodiments are directed to a system for accessing a self-encrypting drive (SED) upon resuming from a sleep power mode (SPM) state. An SED may be authenticated within a system, for example, upon resuming from a sleep state, based on unwrapping the SED passphrase with a SPM resume passphrase stored in a standby power register to receive power during the SPM state.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: March 19, 2019
    Assignee: INTEL CORPORATION
    Inventors: Asher Altman, Mark Schmisseur
  • Patent number: 10236111
    Abstract: Techniques and mechanisms for delivering power with a transformer. In an embodiment, the transformer comprises a dielectric slab structure, a first conductor, a layer of ferromagnetic material disposed around first windings of the first conductor, and a second conductor which forms second windings around the layer of ferromagnetic material. For one of the first windings or one of the second windings, a cross-section of the winding conforms to a rectangle, wherein a width of the cross-section which is more than a height of the cross-section. A ferromagnetic material of the ferrite layer extends between successive ones of the first windings. In another embodiment, a volume fraction of the ferromagnetic material in the ferrite layer is equal to or less than ninety seven percent (97%).
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventor: Arvind Sundaram
  • Patent number: 10231632
    Abstract: Described is an apparatus which comprises: a current source to generate a current having AC and DC components; a current-to-voltage converter to convert the current or a copy of the current to a voltage proportional to a resistance, the voltage having AC and DC components that correspond to the AC and DC components of the current; a first sample-and-hold circuit to sample and filter the AC component from the voltage and to provide an output voltage with the DC component; a second sample-and-hold circuit to sample the output voltage; a voltage-to-current converter to convert the sampled output voltage to a corresponding current; and an amplifier to receive the output voltage.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventor: Craig P. Finlinson
  • Patent number: D843367
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Aleksander Magi, Randall W. Martin