Intel Patents

Intel Corporation designs and manufactures microprocessors and chipsets for computing and communications equipment manufacturers. Its products may be found in desktops, servers, tablets, smartphones and other devices.

Intel Patents by Type

  • Intel Patents Granted: Intel patents that have been granted by the United States Patent and Trademark Office (USPTO).
  • Intel Patent Applications: Intel patent applications that are pending before the United States Patent and Trademark Office (USPTO).
  • Publication number: 20170302356
    Abstract: Signaling techniques to support DL MU-MIMO in 60 GHz wireless networks are described. According to various such techniques, a transmitting 60 GHz-capable device may be configured to include DL MU-MIMO control information in a PHY header of a PPDU that comprises respective data for multiple receiving devices. In some embodiments, the DL MU-MIMO control information may include information identifying each such receiving device. In various embodiments, the DL MU-MIMO control information may include information specifying—for each such receiving device—one or more respective spatial streams that are assigned to that receiving device. Other embodiments are described and claimed.
    Type: Application
    Filed: June 29, 2017
    Publication date: October 19, 2017
    Applicant: INTEL IP CORPORATION
    Inventors: Chittabrata Ghosh, Carlos Cordeiro
  • Publication number: 20170302402
    Abstract: Some demonstrative embodiments include apparatuses, devices, systems and methods of multi-user (MU) wireless communication. For example, a wireless station may generate a MU Physical Layer Convergence Protocol (PLCP) Protocol Data Unit (PPDU) including a header field and a plurality of Spatial Streams (SSs) of Media Access Control (MAC) Protocol Data Units (MPDUs) to a plurality of users, the header field including an indication of a plurality of modulation schemes corresponding to respective ones of the plurality of users; and process transmission of the MU PPDU to the plurality of users over a wireless communication band.
    Type: Application
    Filed: May 2, 2017
    Publication date: October 19, 2017
    Applicant: Intel IP Corporation
    Inventors: Carlos Cordeiro, Assaf Kasher, Chittabrata Chitto Ghosh
  • Publication number: 20170303328
    Abstract: Wireless communication networks may use various techniques, including those that use multiple-access techniques such as multi-user multiple-input multiple-output (MU-MIMO) techniques. In some embodiments, the use of a MU-MIMO setup frame may give a destination STA a chance to select a best antenna weight vector (AWV) based on previous antenna training. In particular, the use of an AWVgroupID may be used to identify a group of one or more STAs that can be the destination STAs of the MU-MIMO setup frame.
    Type: Application
    Filed: December 28, 2016
    Publication date: October 19, 2017
    Applicant: Intel IP Corporation
    Inventors: Laurent Cariou, Carlos Cordeiro, Assaf Kasher
  • Publication number: 20170301371
    Abstract: An audio stream of a video is selected for enhancement using image of the video. In one example, audio streams in the video are identified and segregated. Points of interest and their locations are identified in the image of the video. The position of each audio stream is plotted to a location of a point of interest. A selection of a point of interest from the sequence of images is received. A plotted audio stream is selected based on the corresponding point of interest and the selected audio stream is enhanced.
    Type: Application
    Filed: April 15, 2016
    Publication date: October 19, 2017
    Applicant: Intel Corporation
    Inventors: Jerome L. Anand, Kumaran Sethuraman
  • Publication number: 20170300361
    Abstract: Methods and apparatus relating to employing out-of-order queues for improved GPU (Graphics Processing Unit) utilization are described. In an embodiment, logic is used to employ out-of-order queues for improved GPU (Graphics Processing Unit) utilization. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: July 3, 2016
    Publication date: October 19, 2017
    Applicant: INTEL CORPORATION
    Inventors: Pavan K. Lanka, Krzysztof Laskowski, Michal Mrozek
  • Publication number: 20170299690
    Abstract: Described herein are technologies related to estimating location of a mobile device especially while the device is traveling a known and mapped route. That is, the described technologies estimate a user's location when they are traversing a commonly traveled route. More particularly, the described technologies are especially suited to estimating geo-location of a user. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Application
    Filed: March 5, 2017
    Publication date: October 19, 2017
    Applicant: Intel Corporation
    Inventors: Anthony G. Lamarca, Jaroslaw J. Sydir
  • Publication number: 20170300434
    Abstract: Methods and apparatus relating to techniques for Electromagnetic Interference (EMI) mitigation on high-speed lanes using false stall are described. In one embodiment, protocol logic determines whether to perform a false stall operation on a lane in response to a determination that no data is to be sent over the lane and that data is being transmitted over the lane. The false stall operation includes sending one or more training symbols (e.g., immediately) after an End Of Burst (EOB) signal over the lane, instead of allowing the lane to stall. Other embodiments are also disclosed.
    Type: Application
    Filed: March 13, 2017
    Publication date: October 19, 2017
    Applicant: Intel Corporation
    Inventor: Gregory L. Ebert
  • Publication number: 20170300347
    Abstract: Examples may include a determining a checkpointing/delivery policy for primary and secondary virtual machines based on output-packet-similarities. The output-packet-similarities may be based on a comparison of time intervals via which content matched for packets outputted from the primary and secondary virtual machines. A checkpointing/delivery mode may then be selected based, at least in part, on the determined checkpointing/delivery policy.
    Type: Application
    Filed: October 8, 2014
    Publication date: October 19, 2017
    Applicant: INTEL CORPORATION
    Inventors: KUN TIAN, YAO ZU DONG
  • Publication number: 20170300342
    Abstract: Various embodiments are generally directed to an apparatus, method and other techniques for receiving information to invoke a transition from a first operating system to a second operating system, copying a system context for the second operating system from a location of a non-volatile memory to a volatile memory, the location associated with the second operating system and transitioning from the first operating system to the second operating system using the system context for the second operating system.
    Type: Application
    Filed: June 30, 2017
    Publication date: October 19, 2017
    Applicant: INTEL CORPORATION
    Inventors: FARAZ A. SIDDIQI, BARNES COOPER
  • Publication number: 20170299510
    Abstract: Techniques are disclosed for particulate matter (PM) measurement in a medium (such as air) using flat-top intensity laser sheet beam generation. The techniques for generating the laser sheet beam may include nonspecialized optical elements (e.g., aspherical, spherical, biconvex, and/or cylindrical lenses) that are cost-effective, reduce the overall footprint of the system, and also provide for relatively increased power efficiencies compared to conventional techniques. The PM measurement system may use the laser sheet beam generated in combination with a medium flow channel to pass the medium through the laser sheet beam, thereby causing particulates within the medium to scatter light, which can be detected using a light sensor (e.g., a photodetector). The scattered light signals can then be analyzed to match them with corresponding particulate sizes and the amount of signals per particulate size can also be determined to measure the size and count of particulates within the medium.
    Type: Application
    Filed: April 19, 2016
    Publication date: October 19, 2017
    Applicant: INTEL CORPORATION
    Inventors: TOLGA ACIKALIN, SHENGBO XU, MELISSA A. COWAN
  • Publication number: 20170299342
    Abstract: Described herein are technologies related to passive or active cloaking devices. More particularly, the passive or active cloaking devices utilize input/output grating couplers and waveguides to create an impression of invisibility on an object that is covered by the passive or active cloaking devices.
    Type: Application
    Filed: April 11, 2016
    Publication date: October 19, 2017
    Applicant: Intel Corporation
    Inventors: Ian A. Young, Johanna M. Swan, Robert L. Sankman, Marko Radosavljevic
  • Patent number: 9791282
    Abstract: Technologies for sharing route navigation data in a community cloud include a mobile navigation device of a vehicle and a remote mobile navigation device of a remote vehicle. The mobile navigation device generates sensor data associated with a current route of the vehicle and determines whether a reference traffic event occurs within a segment of the current route of the vehicle. In response to a determination that a reference traffic event occurs, the mobile navigation devices transmits route update data to the remote mobile navigation device. Based on the route update data, the remote mobile navigation device updates a current route of the remote vehicle to avoid the reference traffic event within a corresponding segment of the current route of the remote vehicle. The mobile navigation device may also transmit the sensor data to a community compute device, which may transmit route update data to the remote mobile navigation device.
    Type: Grant
    Filed: September 27, 2014
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Elmoustapha Ould-Ahmed-Vall, Sunil K. Cheruvu
  • Patent number: 9791501
    Abstract: Examples of thermal contact devices and methods are shown. Compliant thermal contact devices are shown that include interleaved conducting structures to provide a high thermal conduction contact area. Selected examples include a thermal interface material located at the interleaved interface between the conducting structures. Selected examples also include designs for alternate chip orientations.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Paul Diglio, David W. Song
  • Patent number: 9791470
    Abstract: Magnet placement is described for integrated circuit packages. In one example, a terminal is applied to a magnet. The magnet is then placed on a top layer of a substrate with solder between the terminal and the top layer, and the solder is reflowed to attach the magnet to the substrate.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Feras Eid, Sasha N. Oster, Kyu Oh Lee, Sarah Haney
  • Patent number: 9791538
    Abstract: The disclosure generally relates to a method, apparatus and system to deploy aquatic sensors to obtain oceanographic data. In an exemplary embodiment, a free-floating or untethered sensor receives signals from different transmitters. The signals may be configured to travel through air and/or water. The sensor records each signals' time of arrival and determines its location in relationship to known transmitters based on the signal travel time. The position of each sensor may be determined by triangulation to several devices whose positions are known. The distances from the sensor in question to each device is measured by means of time-of-flight measurements for a wireless signal from the sensor to each known-position device. Other methods such as trilateration or dead-reckoning may also be used. The sensor may additionally collect and record oceanographic or other environmental data.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Barry A. O'Mahony, Marc A. Alexander
  • Patent number: 9788581
    Abstract: Some forms relate to an electronic system that includes a textile. The electronic system includes a stretchable body that includes an integrated circuit that is configured to compute and communicate with an external device, wherein the stretchable body further includes at least one of (i) a power source that provides power to at least one of the electronic components; (ii) at least one sensor; (iii) a sensing node that receives signals from each sensor and sends signals to the integrated circuit; and (iv) an antenna that is configured to send and receive signals to and from the integrated circuit and the external device; and a textile attached to the stretchable body.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Adel Elsherbini, Sasha Oster, Braxton Lathrop, Nadine L. Dabby, Feras Eid
  • Patent number: 9792212
    Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for providing a virtual shared cache mechanism. A processing device includes a plurality of clusters allocated into a virtual private shared cache. Each of the clusters includes a plurality of cores and a plurality of cache slices co-located within the plurality of cores. The processing device also includes a virtual shared cache including the plurality of clusters such that the cache data in the plurality of cache slices is shared among the plurality of clusters.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Yen-Cheng Liu, Aamer Jaleel, Bongjin Jung, Zeshan A. Chishti, Adrian C. Moga, Eric Delano, Ren Wang
  • Patent number: 9792224
    Abstract: A processor or system may include a memory controller to store, in a pre-allocated portion of bit-addressable, random access persistent memory (PM), a relationship between a group of addresses being stored in the PM according to a set of instructions when executed. The memory controller is further to retrieve the relationship when accessing an address from the groups of addresses.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Karthik Kumar, Martin P. Dimitrov, Thomas Willhalm
  • Patent number: 9792151
    Abstract: A graphics processing unit's workload duration is monitored across a number of frames. A threshold “k” may be used to determine if the workload is Burst or Sustained for a number of frames and another time constant “t” may be used to monitor the burst behavior. If the device continues to be in burst mode over time “t” and the performance state is not an energy efficient state, then the system may lower the performance state to “Pe” and monitor if the same workload remains as Burst. If not, the performance state may be raised to the next higher performance state.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventor: Murali Ramadoss
  • Patent number: 9792190
    Abstract: Embodiments are generally directed to high capacity energy backed memory with off device storage. A memory device includes a circuit board; multiple memory chips that are installed on the circuit board; a controller to provide for backing up contents of the memory chips when a power loss condition is detected; a connection to a backup energy source; and a connection to a backup data storage that is separate from the memory device.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Mohan J. Kumar, Murugasamy K. Nachimuthu, George Vergis
  • Patent number: 9791834
    Abstract: A system includes a digital-to-time converter (DTC) to generate output signals with phase offsets set by a plurality of DTC input values and a time-to-digital converter (TDC) operatively coupled to the DTC, wherein the TDC has a lower resolution than the DTC. The system also includes a processing component operatively coupled to the DTC and the TDC. The processing device, for each of a plurality of TDC thresholds, determines a DTC input value corresponding to a respective TDC threshold. The processing device may then generate a calibration function based on the determined DTC input values and corresponding TDC thresholds.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Elias Nassar, Samer Nassar, Eyal Fayneh, Rotem Banin, Ofir Degani, Inbar Falkov
  • Patent number: 9792222
    Abstract: Systems and methods for validating virtual address translation. An example processing system comprises: a processing core to execute a first application associated with a first privilege level and a second application associated with a second privilege level, wherein a first set of privileges associated with the first privilege level includes a second set of privileges associated with the second privilege level; and an address validation component to validate, in view of an address translation data structure maintained by the first application, a mapping of a first address defined in a first address space of the second application to a second address defined in a second address space of the second application.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Ravi L. Sahita, Gilbert Neiger, David M. Durham, Vedvyas Shanbhogue, Michael Lemay, Ido Ouziel, Stanislav Shwartsman, Barry Huntley, Andrew V. Anderson
  • Patent number: 9791899
    Abstract: An apparatus and method to permit reconfiguration of a memory topology. A printed circuit board (PCB) has a central processing unit (CPU) connector coupled a pair of dual inline memory module (DIMM) connectors coupled thereto. The PCB defines an electrical access channel coupling the pair of DIMM connectors into a T topology having a first branch and a second branch. The second branch of the T topology is electrically discontinuous with the rest of the T topology proximate to a T junction. A bridge may be provided to span the discontinuity.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: October 17, 2017
    Assignee: INTEL CORPORATION
    Inventors: Gong Ouyang, Kai Xiao, Lu-Vong Phan
  • Patent number: 9792229
    Abstract: In an embodiment, a processor includes: at least one core to execute instructions; and a memory protection logic to encrypt data to be stored to a memory coupled to the processor, generate a message authentication code (MAC) based on the encrypted data, the MAC to have a first value according to a first key, obtain the encrypted data from the memory and validate the encrypted data using the MAC, where the MAC is to be re-keyed to have a second value according to a second key and without the encrypted data. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Eugene M. Kishinevsky, Siddhartha Chhabra, Men Long, Jungju Oh, David M. Durham
  • Patent number: 9792234
    Abstract: Examples are disclosed for establishing a secure destination address range responsive to initiation of a direct memory access (DMA) operation. The examples also include allowing decrypted content obtained as encrypted content from a source memory to be placed at a destination memory based on whether destination memory addresses for the destination memory fall within the secure destination address range.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: October 17, 2017
    Assignee: INTEL CORPORATION
    Inventors: Jayant Mangalampalli, Venkat R. Gokulrangan
  • Patent number: 9792235
    Abstract: Method and apparatus for implementing an optimized credit return mechanism for packet sends. A Programmed Input/Output (PIO) send memory is partitioned into a plurality of send contexts, each comprising a memory buffer including a plurality of send blocks configured to store packet data. A storage scheme using FIFO semantics is implemented with each send block associated with a respective FIFO slot. In response to receiving packet data written to the send blocks and detecting the data in those send blocks has egressed from a send context, corresponding freed FIFO slots are detected, and a lowest slot for which credit return indicia has not be returned is determined. The highest slot in a sequence of freed slots from the lowest slot is then determined, and corresponding credit return indicia is returned.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Mark Debbage, Yatin M. Mutha
  • Patent number: 9792243
    Abstract: Apparatus, systems, and/or methods may include a peripheral component interconnect express (PCIe) link to directly couple a slot with a network fabric. The slot may be defined by a surface and/or may accommodate a hardware module. A rack unit implementation may be utilized, such as a one rack unit (1 U) implementation, a four rack unit (4 U) implementation, and so on. The network fabric may be utilized when hardware modules communicate across the PCIe link, may be bypassed when hardware modules communicate across an additional PCIe link, and so on. The PCIe link may include a direct connect point-to-point PCIe link, a dual star PCIe link, and so on. In addition, the PCIe link may be utilized in a rack-scale architecture.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Dirk F. Blevins, John M. Morgan, Marc A. Goldschmidt, Edward J. Pullin
  • Patent number: 9792246
    Abstract: An I/O interface supports scrambling, where the scrambling can include nonlinear scrambling of the scrambling code, or dynamic bus inversion of the scrambling code, or selective switching of selected bits of the scrambling code, or a combination of these. The transmitting device includes a scrambler and the receiving device includes a descrambler. Both the scrambler and the descrambler generate a linear feedback scrambling code modified by applying one or more of the techniques mentioned above. The modified scrambling code may cause fewer than half of the scrambled output bits to be toggled with respect to a previous scrambled output. The scrambler applies the modified scrambling code to a signal to transmit. The descrambler applies the modified scrambling code to a received signal.
    Type: Grant
    Filed: December 27, 2014
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Ee Loon Teoh, Eng Hun Ooi, Christopher P Mozak, Brian R McFarlane
  • Patent number: 9791975
    Abstract: Embodiments of an apparatus and system are described for a hybrid computing device. Some embodiments may comprise a computing device having an enclosure arranged to support a display on a front of the enclosure, a projector adjustment ring integrated into a portion of the perimeter of the enclosure, and a projector module adjustably coupled to the projector adjustment ring. In various embodiments, the projector module may be arranged for dual-axis rotation within the projector adjustment ring. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 31, 2012
    Date of Patent: October 17, 2017
    Assignee: INTEL CORPORATION
    Inventors: Sameer Sharma, Kun Hung Liang, Cheng Tsung Lin
  • Patent number: 9791904
    Abstract: In an embodiment, a processor includes a plurality of cores and a plurality of temperature sensors, where each core is proximate to at least one temperature sensor. The processor also includes a power control unit (PCU) including temperature logic to receive temperature data that includes a corresponding temperature value from each of the temperature sensors. Responsive to an indication that a highest temperature value of the temperature data exceeds a threshold, the temperature logic is to adjust a plurality of domain frequencies according to a determined policy that is based on instruction execution characteristics of at least two of the plurality of cores. Each domain frequency is associated with a corresponding domain that includes at least one of the plurality of cores and each domain frequency is independently adjustable. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Nir Rosenzweig, Doron Rajwan, Dorit Shapira, Nadav Shulman, Tomer Ziv
  • Patent number: 9791905
    Abstract: Systems and methods of interconnecting devices may include an input/output (IO) interface having one or more clock circuits, a power supply coupled to the one or more clock circuits, and logic to receive a rate adjustment command at the IO interface. The logic may also be configured to adjust a data rate of the IO interface in response to the rate adjustment command, and to adjust an output voltage of the power supply in response to the rate adjustment command.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Stephen R. Mooney, Howard L. Heck, James E. Jaussi, Bryan K. Casper
  • Patent number: 9791917
    Abstract: Apparatuses, methods, and storage media for modifying augmented reality in response to user interaction are described. In one instance, the apparatus for modifying augmented reality may include a processor, a scene capture camera coupled with the processor to capture a physical scene, and an augmentation management module to be operated by the processor. The augmentation management module may obtain and analyze the physical scene, generate one or more virtual articles to augment a rendering of the physical scene based on a result of the analysis, track user interaction with the rendered augmented scene, and modify or complement the virtual articles in response to the tracked user interaction. Other embodiments may be described and claimed.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Gila Kamhi, Amit Moran
  • Patent number: 9791943
    Abstract: An apparatus may include a first panel having a first user interface that includes a keyboard. The apparatus may also include a second panel coupled via a hinge to the first panel in a clamshell structure. The second panel may include a first display side to present information in a first display mode when the apparatus is arranged in an open position, and a second display side to present information in a second display mode when the apparatus is arranged in a closed position. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: October 17, 2017
    Assignee: INTEL CORPORATION
    Inventor: Tim Hulford
  • Patent number: 9792438
    Abstract: In an embodiment, a system includes a processor having at least one core and a security engine, the security engine having a focus change logic to inform a trusted application to be executed in a trusted execution environment of a request for a focus change during execution of the trusted application, enable the focus change to occur during execution of the trusted application when allowed by the trusted application, and otherwise to prevent the focus change. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Nathan Heldt-Sheller, Ned M. Smith
  • Patent number: 9792817
    Abstract: Apparatus, systems, and/or methods may involve reporting a road hazard. Road hazard data may be collected for an object on a road, which may include automatically generated data from a device associated with the object causing a hazard. The road hazard data may be provided to a service, an application, a device, a client, and so on. For example, the road hazard data may be merged with a map and provided to a map services client, a navigation client, and so on. An alert may be generated based on the road hazard data to warn of the hazard caused by the object. The alert may include a visual and/or audio representation of the hazard data. The alert may be used to automatically and/or manually avoid the hazard.
    Type: Grant
    Filed: December 24, 2013
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Tomer Rider, Aviv Ron, Yair Giwnewer
  • Patent number: 9792671
    Abstract: A mechanism is described for facilitating code filters for coded light depth acquisition in depth images at computing devices according to one embodiment. A method of embodiments, as described herein, includes detecting a code image of an object comprising pixels of code values and pixels of metadata values including confidence and code transition locations, and computing a vertical filter to be applied to the code image to smooth out the code transitions along vertical directions. The method further include computing a horizontal filter to be applied to the code image to smooth out the code transitions along horizontal directions, and computing a consistency filter to be applied to the code image to increase an accuracy of the code values and mark inconsistent pixels as invalid.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Vitaly Surazhsky, Michael Bronstein, Alex Bronstein, Ron Kimmel, Erez Sperling, Aviad Zabatani, Ohad Menashe, David H. Silver
  • Patent number: 9792673
    Abstract: A mechanism is described for facilitating management of image noise in digital images using a smart noise management filter according to one embodiment. A method of embodiments, as described herein, includes detecting a digital image of an object, where detecting further includes detecting a pattern signal associated with the digital image. The method may further include measuring a spread function relating to at least one of the digital image and an imaging system of a computing device, where measuring further includes determining deconvolution of the spread function, and where measuring further includes computing a pre-shaping filter based on the deconvolution of the spread function. The method may further include executing the pre-shaping filter to apply the pattern signal to the deconvolution of the spread function to obtain a pre-shaped projection pattern of the digital image.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Vitaly Surazhsky, Ron Kimmel, Alex Bronstein, Michael Bronstein, Erez Sperling, Aviad Zabatani
  • Patent number: 9791641
    Abstract: Inverted 45° semiconductor mirrors as vertical optical couplers for PIC chips, particularly optical receivers and transmitters. An inverted 45° semiconductor mirror functions to couple light between a plane in the PIC chip defined by thin film layers and a direction normal to a top surface of the PIC chip where it may be generated or collected by an off-chip component, such as a wire terminal. In an exemplary embodiment, a (110) plane of a cubic crystalline semiconductor may provide a 45° facet inverted relative to a (100) surface of the semiconductor from which light is to be emitted. In further embodiments, a (110) plane may be exposed by undercutting a device layer of a semiconductor on insulator (SOI) substrate. Alternatively, a pre-etched substrate surface may be bonded to a handling wafer, thinned, and then utilized for PIC waveguide formation.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: John Heck, Haisheng Rong
  • Patent number: 9792064
    Abstract: Embodiments of systems, apparatuses, and methods for energy efficiency and energy conservation including enabling autonomous hardware-based deep power down of devices are described. In one embodiment, a system includes a device, a static memory, and a power control unit coupled with the device and the static memory. The system further includes a deep power down logic of the power control unit to monitor a status of the device, and to transfer the device to a deep power down state when the device is idle. In the system, the device consumes less power when in the deep power down state than in the idle state.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Inder M. Sodhi, Alon Naveh, Doron Rajwan, Ryan D. Wells, Eric C. Samson
  • Patent number: 9792115
    Abstract: A processing core is described having execution unit logic circuitry having a first register to store a first vector input operand, a second register to a store a second vector input operand and a third register to store a packed data structure containing scalar input operands a, b, c. The execution unit logic circuitry further include a multiplier to perform the operation (a*(first vector input operand))+(b*(second vector operand))+c.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Jesus Corbal, Andrew T. Forsyth, Thomas D. Fletcher, Lisa K. Wu, Eric Sprangle
  • Patent number: 9792119
    Abstract: Instructions and logic provide vector horizontal majority voting functionality. Some embodiments, responsive to an instruction specifying: a destination operand, a size of the vector elements, a source operand, and a mask corresponding to a portion of the vector element data fields in the source operand; read a number of values from data fields of the specified size in the source operand, corresponding to the mask specified by the instruction and store a result value to that number of corresponding data fields in the destination operand, the result value computed from the majority of values read from the number of data fields of the source operand.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Elmoustapha Ould-Ahmed-Vall, Kshitij A. Doshi, Suleyman Sair, Charles R. Yount
  • Patent number: 9792063
    Abstract: Providing data security includes: in response to a request to write data content to a storage, generating encrypted data content based on the data content; attempting to obtain a reference to the encrypted data content in the storage; in the event that the reference to the encrypted data content is obtained, modifying a translation line to refer to the reference to the encrypted data content in the storage; and in the event that the reference to the encrypted data content is not obtained: storing the encrypted data content at a new location; obtaining a reference to the encrypted data content stored at the new location; and modifying the translation line to refer to the reference to the encrypted data content stored at the new location.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventor: David R. Cheriton
  • Patent number: 9793163
    Abstract: Subtractive self-aligned via and plug patterning for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate. The first layer includes a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. The interconnect structure further includes a second layer of the interconnect structure disposed above the first layer of the interconnect structure. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Robert L. Bristol, Florian Gstrein, Richard E. Schenker, Paul A. Nyhus, Charles H. Wallace, Hui Jae Yoo
  • Patent number: 9792687
    Abstract: Systems and methods for determining point-to-point distances from 3D image data. In some embodiments, two measure points, for example specified by a user, represent endpoints on an object of interest within an image frame. Assuming all points lying between these endpoints also belong to the object of interest, additional 3D data associated with points that lie along a measurement line defined by the measure points may be leveraged to provide a robust distance measurement. In some embodiments, total least squares fitting is performed, for example through Robust Principal Component Analysis (RPCA) to identify linear structures within the set of the 3D coordinates on the measurement line. In some exemplary embodiments, the minimum covariance determinant (MCD) estimator of the covariance matrix of the data is computed for a highly robust estimate of multivariate location and multivariate scatter.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Kalpana Seshadrinathan, Oscar Nestares, Ali Mehdizadeh, Max T. Stein, Yi Wu, James Granger
  • Patent number: 9792714
    Abstract: Systems and methods may provide for identifying one or more facial expressions of a subject in a video signal and generating avatar animation data based on the one or more facial expressions. Additionally, the avatar animation data may be incorporated into an audio file associated with the video signal. In one example, the audio file is sent to a remote client device via a messaging application. Systems and methods may also facilitate the generation of avatar icons and doll animations that mimic the actual facial features and/or expressions of specific individuals.
    Type: Grant
    Filed: March 20, 2013
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Wenlong Li, Xiaofeng Tong, Yangzhou Du, Thomas Sachson, Yunzhen Wang
  • Patent number: 9793159
    Abstract: Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects are described. In an example, an interconnect structure for an integrated circuit includes a first layer disposed above a substrate. The first layer of the interconnect structure includes a grating of alternating metal lines and dielectric lines in a first direction. A second layer of the interconnect structure is disposed above the first layer. The second layer includes a grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. Each metal line of the grating of the second layer is disposed on a recessed dielectric line composed of alternating distinct regions of a first dielectric material and a second dielectric material corresponding to the alternating metal lines and dielectric lines of the first layer of the interconnect structure.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Charles H. Wallace, Paul A. Nyhus, Elliot N. Tan, Swaminathan Sivakumar
  • Patent number: 9793233
    Abstract: Methods of forming a microelectronic packaging structure are described. Those methods may include forming a solder paste comprising a sacrificial polymer on a substrate, curing the solder paste below a reflow temperature of the solder to form a solid composite hybrid bump on the conductive pads, forming a molding compound around the solid composite hybrid bump, and reflowing the hybrid bump, wherein the sacrificial polymer is substantially decomposed.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: October 17, 2017
    Assignee: INTEL CORPORATION
    Inventors: Rajasekaran Swaminathan, Leonel R. Arana, Yoshihiro Tomita, Yosuke Kanaoka
  • Patent number: 9793201
    Abstract: Embodiments of the present description relate to the field of fabricating microelectronic substrates. The microelectronic substrate may include a trace routing structure disposed between opposing glass layers. The trace routing structure may comprise one or more dielectric layers having conductive traces formed thereon and therethrough. Also disclosed are embodiments of a microelectronic package including a microelectronic device disposed proximate one glass layer of the microelectronic substrate and coupled with the microelectronic substrate by a plurality of interconnects.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Qing Ma, Johanna M. Swan
  • Patent number: 9793220
    Abstract: A capacitive sensor and measurement circuitry is described that may be able to reproducibly measure miniscule capacitances and variations thereof. The capacitance may vary depending upon local environmental conditions such as mechanical stress (e.g., warpage or shear stress), mechanical pressure, temperature, and/or humidity. It may be desirable to provide a capacitor integrated into a semiconductor chip that is sufficiently small and sensitive to accurately measure conditions expected to be experienced by a semiconductor chip.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: October 17, 2017
    Assignee: INTEL DEUTSCHLAND GMBH
    Inventors: Hans-Joachim Barth, Horst Baumeister, Peter Baumgartner, Philipp Riess, Jesenka Veledar Krueger
  • Patent number: 9793225
    Abstract: The present description relates to the field of fabricating microelectronic packages, wherein a microelectronic device may be attached to a microelectronic substrate with a compensator to control package warpage. The warpage compensator may be a low coefficient of thermal expansion material, including but not limited to silicon or a ceramic material, which is positioned on a land-side of the microelectronic device to counteract the thermal expansion effects of the microelectronic device.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Pramod Malatkar, Richard J. Harries