Intel Patents

Intel Corporation designs and manufactures microprocessors and chipsets for computing and communications equipment manufacturers. Its products may be found in desktops, servers, tablets, smartphones and other devices.

Intel Patents by Type
  • Intel Patents Granted: Intel patents that have been granted by the United States Patent and Trademark Office (USPTO).
  • Intel Patent Applications: Intel patent applications that are pending before the United States Patent and Trademark Office (USPTO).
  • Publication number: 20200169723
    Abstract: Systems, apparatuses and methods may provide for technology that includes a substrate, and a display pipeline coupled to the substrate. The display pipeline may to barrel an initial image to form a barreled image.
    Type: Application
    Filed: November 26, 2019
    Publication date: May 28, 2020
    Applicant: Intel Corporation
    Inventors: Ravindra A. Babu, Sagar C. Pawar, Satyanantha R. Musunuri, Sashank Ms, Kalyan K. Kaipa
  • Publication number: 20200168384
    Abstract: Described herein are magnetic core inductors (MCI) and methods for manufacturing magnetic core inductors. A first embodiment of the MCI can be a snake-configuration MCI. The snake-configuration MCI can be formed by creating an opening in a base material, such as copper, and providing a nonconductive magnetic material in the opening. The inductor can be further formed by forming plated through holes into the core material. The conductive elements for the inductor can be formed in the plated through holes. The nonconductive magnetic material surrounds each conductive element and plated through hole. In embodiments, a layered coil inductor can be formed by drilling a laminate to form a cavity through the laminate within the metal rings of the layered coil inductor. The nonconductive magnetic material can be provided in the cavity.
    Type: Application
    Filed: September 28, 2017
    Publication date: May 28, 2020
    Applicant: Intel Corporation
    Inventors: Junnan Zhao, Ying Wang, Cheng Xu, Kyu Oh Lee, Sheng Li, Yikang Deng
  • Publication number: 20200169363
    Abstract: Embodiments of efeMTC synchronization signals for enhanced cell search and enhanced system information acquisition are described. In some embodiments, an apparatus of a base station (BS) is configured to generate a length-x sequence for an efeMTC synchronization signal, the length-x sequence configured for repetition in frequency domain within 6 physical resource blocks (PRB). In some embodiments, to generate the length-x sequence, the BS may be configured to select any one index of the set of root indices {1, 2, . . . , 63}, excluding the root indices 25, 29 and 34, to correspond to a different physical-layer cell identity (PCID). In some embodiments, the BS may be configured to encode RRC signaling to include a System Information Block (SIB) comprising configuration information for transmission of the efeMTC synchronization signal, and transmit the length-x sequence as the efeMTC synchronization signal in frequency resources according to the SIB.
    Type: Application
    Filed: March 20, 2018
    Publication date: May 28, 2020
    Applicant: Intel IP Corporation
    Inventors: Salvatore TALARICO, Qiaoyang YE, Debdeep CHATTERJEE, Seunghee HAN, Dae Won LEE
  • Publication number: 20200169720
    Abstract: An activity recording system is provided. The activity recording system includes a three-dimensional camera, a sensor arrangement that is fitted to a subject being recorded, and an activity recording device. The activity recording device receives image information from the three-dimensional camera and sensor arrangement information from the sensor arrangement. Both the image information and the sensor arrangement information include location measurements. The sensor arrangement information is generated by location sensors that are positioned at target features of the subject to be tracked. The sensor arrangement information is a key to the image information that specifies where, in any given image, the target features of the subject lie. Activity data having these characteristics may be applied to solve a variety of system development problems. Such activity data can be used to training machine learning components or test computer vision components for a fraction of the cost of using conventional techniques.
    Type: Application
    Filed: January 30, 2020
    Publication date: May 28, 2020
    Applicant: INTEL CORPORATION
    Inventor: Amit Bleiweiss
  • Publication number: 20200169383
    Abstract: A processor comprises a first register to store an encoded pointer to a memory location. First context information is stored in first bits of the encoded pointer and a slice of a linear address of the memory location is stored in second bits of the encoded pointer. The processor also includes circuitry to execute a memory access instruction to obtain a physical address of the memory location, access encrypted data at the memory location, derive a first tweak based at least in part on the encoded pointer, and generate a keystream based on the first tweak and a key. The circuitry is to further execute the memory access instruction to store state information associated with memory access instruction in a first buffer, and to decrypt the encrypted data based on the keystream. The keystream is to be generated at least partly in parallel with accessing the encrypted data.
    Type: Application
    Filed: January 29, 2020
    Publication date: May 28, 2020
    Applicant: Intel Corporation
    Inventors: David M. Durham, Michael LeMay, Michael E. Kounavis, Santosh Ghosh, Sergej Deutsch, Anant Vithal Nori, Jayesh Gaur, Sreenivas Subramoney, Karanvir S. Grewal
  • Publication number: 20200167274
    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to two or more persistent storage devices, wherein at least one of the two or more persistent storage devices is to be logically organized with a namespace divided into two or more zones, determine two or more different zone size dependent parameters associated with the two or more persistent storage devices, determine a smallest aligned boundary based on each of the two or more different zone size dependent parameters, and set a zone group size for access to the two or more persistent storage devices based on the determined smallest aligned boundary. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: December 20, 2019
    Publication date: May 28, 2020
    Applicant: Intel Corporation
    Inventors: Shirish Bahirat, Michael Scott Allison, Mary Allison Goodman
  • Publication number: 20200168536
    Abstract: Disclosed herein are asymmetric cored integrated circuit (IC) package supports, and related devices and methods. For example, in some embodiments, an IC package support may include a core region having a first face and an opposing second face, a first buildup region at the first face of the core region, and a second buildup region at the second face of the core region. A thickness of the first buildup region may be different than a thickness of the second buildup region. In some embodiments, an inductor may be included in the core region.
    Type: Application
    Filed: November 28, 2018
    Publication date: May 28, 2020
    Applicant: Intel Corporation
    Inventors: Lauren Ashley Link, Andrew James Brown, Prithwish Chatterjee, Sai Vadlamani, Ying Wang, Chong Zhang
  • Publication number: 20200167949
    Abstract: The systems and methods disclosed herein provide determination of an orientation of a feature towards a reference target. As a non-limiting example, a system consistent with the present disclosure may include a processor, a memory, and a single camera affixed to the ceiling of a room occupied by a person. The system may analyze images from the camera to identify any objects in the room and their locations. Once the system has identified an object and its location, the system may prompt the person to look directly at the object. The camera may then record an image of the user looking at the object. The processor may analyze the image to determine the location of the user's head and, combined with the known location of the object and the known location of the camera, determine the direction that the user is facing. This direction may be treated as a reference value, or “ground truth.” The captured image may be associated with the direction, and the combination may be used as training input into an application.
    Type: Application
    Filed: January 20, 2020
    Publication date: May 28, 2020
    Applicant: INTEL CORPORATION
    Inventors: GLEN J. ANDERSON, GIUSEPPE RAFFA, CARL S. MARSHALL, MENG SHI
  • Publication number: 20200167506
    Abstract: A PCIe card includes an FPGA and a memory that is discrete from the FPGA. The memory is accessible by the FPGA and not other devices on the card. The FPGA's core fabric is configured with a security processor that verifies a bitstream loaded through the FGPA into the memory as authentic or not authentic to limit unauthorized access to data from a user circuit that is associated with a not authentic bitstream. The security processor is loaded into the FPGA when a request is made for bitstream verification and is allowed to be overwritten after the security processor processes the bitstream to determine if the bitstream is authentication or not authentic. Allowing the security processor to be overwritten allows for high percentage usage of the core fabric for user circuits and limits the inclusion of a static circuit in the core fabric that is infrequently used.
    Type: Application
    Filed: September 27, 2019
    Publication date: May 28, 2020
    Applicant: Intel Corporation
    Inventors: Prakash Iyer, Eric Innis, Evan Custodio, Ting Lu
  • Publication number: 20200168724
    Abstract: Disclosed herein are tunneling field effect transistors (TFETs), and related methods and computing devices. In some embodiments, a TFET may include: a first source/drain material having a p-type conductivity; a second source/drain material having an n-type conductivity; a channel material at least partially between the first source/drain material and the second source/drain material, wherein the channel material has a first side face and a second side face opposite the first side face; and a gate above the channel material, on the first side face, and on the second side face.
    Type: Application
    Filed: August 18, 2017
    Publication date: May 28, 2020
    Applicant: Intel Corporation
    Inventors: Cheng-Ying Huang, Willy Rachmady, Matthew V. Metz, Ashish Agrawal, Benjamin Chu-Kung, Uygar E. Avci, Jack T. Kavalieros, Ian A. Young
  • Publication number: 20200163562
    Abstract: An apparatus is provided for monitoring heart rate. The apparatus comprises various components to effectively reduce photodiode capacitance. The apparatus includes: an amplifier; a first current source; a first pair of resistors coupled to the first current source and the amplifier; a pair of devices coupled to the first pair of resistors; a photo-diode coupled to the pair of devices; a second pair of resistors coupled to the pair of devices and the photo-diode; and a second current source coupled to the second pair of resistors.
    Type: Application
    Filed: August 13, 2018
    Publication date: May 28, 2020
    Applicant: Intel Corporation
    Inventor: Philip Neaves
  • Publication number: 20200168794
    Abstract: Phase change memory cells, structures, and devices having a phase change material and an electrode forming an ohmic contact therewith are disclosed and described. Such electrodes can have a resistivity of from 10 to 100 mOhm·cm.
    Type: Application
    Filed: December 3, 2019
    Publication date: May 28, 2020
    Applicant: Intel Corporation
    Inventors: Valter Soncini, Davide Erbetta
  • Publication number: 20200168708
    Abstract: A method for forming III-N structures of desired nanoscale dimensions is disclosed. The method is based on, first, providing a material to serve as a shell inside which a cavity can he formed, followed by using epitaxial growth to fill the cavity with III-N semiconductor(s). Filling a cavity of specified shape and dimensions with a III-N semiconductor results in formation of a III-N structure which has shape and dimensions defined by those of the cavity in the shell, advantageously enabling formation of III-N structures on a nanometer scale without having to rely on etching of III-N materials. Ensuring that at least a part of the III-N material in the cavity is formed by lateral epitaxial overgrowth allows obtaining high quality III-N semiconductor in that part without having to grow a thick layer. Disclosed III-N nanostructures can serve as foundation for fabricating III-N device components, e.g. transistors, having non-planar architecture.
    Type: Application
    Filed: September 26, 2017
    Publication date: May 28, 2020
    Applicant: Intel Corporation
    Inventors: Marko Radosavljevic, Sansaptak Dasgupta, Han Wui Then
  • Publication number: 20200166569
    Abstract: Embodiments may relate an x-ray filter. The x-ray filter may be configured to be positioned between an x-ray source output and a device under test (DUT) that is to be x-rayed. The x-ray filter may include at least 80% titanium (Ti) by weight. Other embodiments may be described or claimed.
    Type: Application
    Filed: November 23, 2018
    Publication date: May 28, 2020
    Applicant: Intel Corporation
    Inventors: Mario Pacheco, Deepak Goyal
  • Publication number: 20200163619
    Abstract: A wearable device measures heart rate recovery of a user in a non-clinical setting. The wearable device comprises a heart rate detector configured to detect heart rate data of the user, an activity sensor configured to detect motion of the user, and a processor. The processor is configured to identify a start of an activity by the user using the motion detected by the activity sensor. Responsive to detecting the start of the activity, the processor monitors the motion detected by the activity sensor to identify an end of the activity. A regression analysis is performed on heart rate data detected by the heart rate detector during a period of time after the end of the activity, and the heart rate recovery of the user is determined using the regression analysis.
    Type: Application
    Filed: August 2, 2019
    Publication date: May 28, 2020
    Applicant: Intel Corporation
    Inventors: Jonathan K. Lee, Marco Della Torre
  • Publication number: 20200167089
    Abstract: An embodiment of a memory controller device includes technology to control access to a memory array which includes a single-level cell region and a multi-level cell region, determine an amount of valid data in a dynamic portion of the single-level cell region at runtime, and adjust a size of the dynamic portion of the single-level cell region at runtime based on the determined amount of valid data in the dynamic portion of the single-level cell region. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: August 6, 2019
    Publication date: May 28, 2020
    Applicant: Intel Corporation
    Inventors: Shankar Natarajan, Suresh Nagarajan, Shivashekar Muralishankar, Sriram Natarajan, Yihua Zhang
  • Publication number: 20200167190
    Abstract: An apparatus comprising an interface to receive an identification of a function to be executed; and a scheduling engine comprising circuitry, the scheduling engine to select a candidate compute element from a plurality of candidate compute elements based on a combined burden, the combined burden based on an estimated burden to execute the function by the candidate compute element and an estimated burden of data movement over at least one interconnect identified for the candidate compute element.
    Type: Application
    Filed: January 29, 2020
    Publication date: May 28, 2020
    Applicant: Intel Corporation
    Inventor: Francesc Guim Bernat
  • Publication number: 20200167487
    Abstract: A method comprises initializing, by an accelerator device of the computing device, an authentication tag in response to an initialization command from a trusted execution environment of the computing device, initiating a transfer, by the accelerator device, of data between a host memory and an accelerator device memory in response to a descriptor from the trusted execution environment, wherein the descriptor comprises a target memory address and is indicative of a transfer direction, comparing, in a memory range selection engine comprising at least one comparator to compare the target memory address with a plurality of address ranges and select a cryptographic key from the plurality of plurality of address range registers based on the target memory address, performing, by the accelerator device, a cryptographic operation with the data in response to transferring the data, updating, by the accelerator device, the authentication tag in response to transferring the data, and finalizing, by the accelerator device
    Type: Application
    Filed: January 28, 2020
    Publication date: May 28, 2020
    Applicant: Intel Corporation
    Inventors: Luis S. Kida, Reshma Lal
  • Publication number: 20200167488
    Abstract: Embodiments are directed to protection of communications between a trusted execution environment and a hardware accelerator utilizing enhanced end-to-end encryption and inter-context security. An embodiment of an apparatus includes one or more processors having one or more trusted execution environments (TEEs) including a first TEE to include a first trusted application; an interface with a hardware accelerator, the hardware accelerator including trusted embedded software or firmware; and a computer memory to store an untrusted kernel mode driver for the hardware accelerator, the one or more processors to establish an encrypted tunnel between the first trusted application in the first TEE and the trusted software or firmware, generate a call for a first command from the first trusted application, generate an integrity tag for the first command, and transfer command parameters for the first command and the integrity tag to the kernel mode driver to generate the first command.
    Type: Application
    Filed: January 28, 2020
    Publication date: May 28, 2020
    Applicant: Intel Corporation
    Inventors: Salessawi Ferede Yitbarek, Lawrence A. Booth Jr., Brent Thomas, Reshma Lal, Pradeep M. Pappachan, Akshay Kadam
  • Patent number: 10664573
    Abstract: Apparatuses, methods and storage media associated with managing a computing platform in view of an expiration date are described herein. In embodiments, an apparatus may include a computing platform that includes one or more processors to execute applications; and a trusted execution environment that includes a tamper-proof storage to store an expiration date of the computing platform, and a firmware module to be operated in a secure system management mode to regulate operation of the computing platform in view of at least whether a current date is earlier than the expiration date. Other embodiments may be described or claimed.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Jiewen Yao, Vincent J. Zimmer, Rajesh Poornachandran
  • Patent number: 10666946
    Abstract: Techniques described herein are related to video coding using display modification input.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Sean J. Lawrence, Frederic J. Noraz, Jill M. Boyce, Sumit Mohan
  • Patent number: 10664039
    Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Andrew J. Herdrich, Rameshkumar G. Illikkal, Ravishankar Iyer, Sadagopan Srinivasan, Jaideep Moses, Srihari Makineni
  • Patent number: 10666999
    Abstract: Example methods and apparatus for adaptive video transmission based on channel capacity are disclosed. A first wireless display source device for adaptive video transmission based on channel capacity includes a video bit rate determiner, a comparer and a video bit rate setter. The video bit rate determiner is to determine a collective video bit rate based on a current number of wireless display connections in a peer-to-peer (P2P) group multiplied by a current video bit rate of the first wireless display source device. The P2P group includes a second wireless display source device in proximity to the first wireless display source device. The comparer is to compare the collective video bit rate to a wireless display capacity in proximity to the first wireless display source device.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Abhijeet Kolekar, Inching Chen, Karthik Veeramani
  • Patent number: 10664179
    Abstract: An integrated circuit includes protected container access control logic to perform a set of access control checks and to determine whether to allow a device protected container module (DPCM) and an input and/or output (I/O) device to communicate securely through one of direct memory access (DMA) and memory-mapped input/output (MMIO). The DPCM and the I/O device are allowed to communicate securely if it is determined that at least the DPCM and the I/O device are mapped to one another, an access address associated with the communication resolves into a protected container memory, and a page of the protected container memory into which the access address resolves allows for the aforementioned one of DMA and MMIO. In some cases, a Security Attributes of Initiator (SAI) or security identifier may be used to obtain a DPCM identifier or attest that access is from a DPCM mapped to the I/O device.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Ilya Alexandrovich, Vladimir Beker, Gideon Gerzon, Vincent R. Scarlata
  • Patent number: 10664237
    Abstract: An apparatus and method for performing a reciprocal square root. For example one embodiment of a processor comprises: a decoder to decode a reciprocal square root instruction to generate a decoded reciprocal square root instruction; a source register to store at least one packed input data element; a destination register to store a result data element; and reciprocal square root execution circuitry to execute the decoded reciprocal square root instruction, the reciprocal square root execution circuitry to use a first portion of the packed input data element as an index to a data structure containing a plurality of sets of coefficients to identify a first set of coefficients from the plurality of sets, the reciprocal square root execution circuitry to generate a reciprocal square root of the packed input data element using a combination of the coefficients and a second portion of the packed input data element.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Cristina Anderson, Elmoustapha Ould-Ahmed-Vall, Marius Cornea-Hasegan, Robert Valentine, Mark Charney, Jesus Corbal, Venkateswara Madduri
  • Patent number: 10664416
    Abstract: Technologies for secure I/O with an external peripheral device link controller include a computing device coupled to an external dock device by an external peripheral link, such as a Thunderbolt link. The external dock device includes an I/O controller that receives device data from an I/O device, generates a channel identifier associated with the I/O device, and transmits I/O data that includes the channel identifier to a dock controller. The dock controller encapsulates the I/O data to generate peripheral link protocol data and transmits the peripheral link protocol data to a host controller of the computing device over the external peripheral link. The host controller de-encapsulates the peripheral link protocol data and forwards the I/O data to memory. The channel identifier may be a predetermined value associated with the I/O controller, or may include a controller identifier associated with the host controller. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Reshma Lal, Siddhartha Chhabra
  • Patent number: 10666909
    Abstract: Methods, apparatus, systems and articles of manufacture to perform remote monitoring are disclosed. Some example methods include adjusting an image capture rate at which an image sensor captures images based on a difference image containing differences between a first image of a first set of objects and a second image of a second set of objects. Example methods also include reducing a file size of the difference image using an edge detection technique and prioritizing one or more of a set of frames based on an amount of information contained in the frames. The frames are subdivisions of the image. In further example methods, the first image is taken at a first time and the second image is taken at a second, later time, and the method includes subtracting the first image from the second image to generate the difference image.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: John Brady, Keith Nolan, Wael Guibene, Michael Nolan, Mark Kelly
  • Patent number: 10664430
    Abstract: Described is a reconfigurable transmitter which includes: a first pad; a second pad; a first single-ended driver coupled to the first pad; a second single-ended driver to the second pad; a differential driver coupled to the first and second pads; and a logic unit to enable of the first and second single-ended drivers, or to enable the differential driver.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Tzu-Chien Hsueh, Ganesh Balamurugan, Bryan K. Casper
  • Patent number: 10664425
    Abstract: A processor may include a core to execute interrupt latency control unit (ILCU) software and an interrupt controller circuitry. The interrupt controller circuitry includes: a first register to store a first time value at which a first interrupt is received at the interrupt controller circuitry and a second register to store a second time value at which the first interrupt is delivered to the core. The ILCU software is to: read the first time value in the first register and the second time value in the second register; determine an amount of time the first interrupt was pending at the interrupt controller circuitry; determine interrupt configuration information that adjusts the first interrupt priority of a subsequent interrupt; and send the interrupt configuration information to the interrupt controller circuitry. The interrupt controller circuitry is to adjust the first interrupt priority of the subsequent interrupt to the second interrupt priority.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventor: SampathKumar Malalangaradhos
  • Patent number: 10665577
    Abstract: Techniques are disclosed for forming monolithic integrated circuit semiconductor structures that include a III-V portion implemented with III-N semiconductor materials, such as gallium nitride, indium nitride, aluminum nitride, and mixtures thereof. The disclosed semiconductor structures may further include a CMOS portion implemented with semiconductor materials selected from group IV of the periodic table, such as silicon, germanium, and/or silicon germanium (SiGe). The disclosed techniques can be used to form highly-efficient envelope tracking devices that include a voltage regulator and a radio frequency (RF) power amplifier that may both be located on the III-N portion of the semiconductor structure. Either of the CMOS or III-N portions can be native to the underlying substrate to some degree. The techniques can be used, for example, for system-on-chip integration of a III-N voltage regulator and RF power amplifier along with column IV CMOS devices on a single substrate.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: May 26, 2020
    Assignee: INTEL CORPORATION
    Inventors: Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic, Seung Hoon Sung, Sanaz Gardner
  • Patent number: 10663980
    Abstract: Various embodiments are generally directed to providing information capture by multiple drones, which may operate in a swarm, while maintaining rights and/or value assigned to the content authored by each drone or by subsets of drones. In general, the present disclosure provides that drones participating in content acquisition may attest to their authenticity to establish trust between drones in the swarm.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: May 26, 2020
    Assignee: INTEL CORPORATION
    Inventors: Ned M. Smith, Rajesh Poornachandran
  • Patent number: 10664433
    Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing SoC coverage through virtual devices in PCIe and DMI controllers.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Lakshminarayana Pappu, Timothy J. Callahan, Hem Doshi, Hooi Kar Loo, Suketu U. Bhatt
  • Patent number: 10664396
    Abstract: A method and apparatus for performing a data transfer, which include a selection a data transfer operation mode, based on telemetry data, from a first operation mode where a first type of data is transferred from a memory of a computing system to one or more shared storage devices, and a second operation mode where a second type of data is transferred from the memory to the one or more shared storage devices, the first type of data being associated with a first range of address space of the one or more shared storage devices, the second type of data being associated with a second range of address space of the one or more shared storage devices different from the first range of address space. Furthermore, a data transfer from the memory to the one or more shared storage devices in the selected data transfer operation mode may be included.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: May 26, 2020
    Assignee: INTEL CORPORATION
    Inventors: Francesc Guim Bernat, Kshitij Doshi, Sujoy Sen
  • Patent number: 10665222
    Abstract: A system, article, and method provide temporal-domain feature extraction for automatic speech recognition.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Suyoung Bang, Muhammad Khellah, Somnath Paul, Charles Augustine, Turbo Majumder, Wootaek Lim, Tobias Bocklet, David Pearce
  • Patent number: 10664199
    Abstract: A processor includes a processing core to generate a memory request for an application data in an application. The processor also includes a virtual page group memory management (VPGMM) unit coupled to the processing core to specify a caching priority (CP) to the application data for the application. The caching priority identifies importance of the application data in a cache.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Subramanya R. Dulloor, Rajesh M. Sankaran, David A. Koufaty, Christopher J. Hughes, Jong Soo Park, Sheng Li
  • Patent number: 10664273
    Abstract: An apparatus and method for processing efficient multicast operation.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Christopher J. Hughes, Dan Baum
  • Patent number: 10663998
    Abstract: Various embodiments provide a voltage regulator circuit with automatic phase shedding. A control circuit may control first transitions of a power state of the voltage regulator based on an average current draw of the voltage regulator. The control circuit may further control second transitions of the power state of the voltage regulator based on a voltage droop of the output voltage and/or a peak current draw of the voltage regulator. The first transitions may be performed synchronously, and the second transitions may be performed asynchronously. Other embodiments may be described and claimed.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Tamir Salus, Alexander Lyakhov, Alexander Gendler, Krishnakanth Sistla, Ankush Varma, Rachid Rayess, Nimrod Angel
  • Patent number: 10664284
    Abstract: An apparatus and method are described for executing both latency-optimized execution logic and throughput-optimized execution logic on a processing device. For example, a processor according to one embodiment comprises: latency-optimized execution logic to execute a first type of program code; throughput-optimized execution logic to execute a second type of program code, wherein the first type of program code and the second type of program code are designed for the same instruction set architecture; logic to identify the first type of program code and the second type of program code within a process and to distribute the first type of program code for execution on the latency-optimized execution logic and the second type of program code for execution on the throughput-optimized execution logic.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Oren Ben-Kiki, Yuval Yosef, Ilan Pardo, Dror Markovich
  • Patent number: 10664600
    Abstract: Apparatus, systems, or methods for a programmable circuit to facilitate a processor to boot a computing device having the processor. A programmable circuit may include non-volatile storage and firmware stored in the non-volatile storage. The firmware may configure the programmable circuit as a memory controller of a memory device coupled to the programmable circuit, to facilitate the processor to boot the computing device having the processor, the programmable circuit, and the memory device, into operation. Other embodiments may also be described and claimed.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Yah Wen Ho, Tung Lun Loo, Yan Fei Lee
  • Patent number: 10664281
    Abstract: Methods and apparatuses relating to dynamic asymmetric scaling of branch predictor tables are described. Branch predictor circuits to perform dynamic asymmetric scaling of branch predictor tables are also described.
    Type: Grant
    Filed: September 29, 2018
    Date of Patent: May 26, 2020
    Assignee: INTEL CORPORATION
    Inventors: Ragavendra Natarajan, Niranjan Soundararajan, Saurabh Gupta, Sreenivas Subramoney
  • Patent number: 10664178
    Abstract: Various embodiments are directed to providing integrity protection for a system management mode. During initialization, a hash value of a system management mode control routine may be determined. Subsequently, during operation, the hash value may be compared to a hash value of a system management mode control routine to be executed. The system management mode control routine to be executed may be determined to be authentic if the hash values are the same.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: May 26, 2020
    Assignee: INTEL CORPORATION
    Inventors: Jorge E. Gonzalez Diaz, Juan Manuel Cruz Alcaraz
  • Patent number: 10665708
    Abstract: Semiconductor devices including an elevated or raised doped crystalline structure extending from a device layer are described. In embodiments, III-N transistors include raised crystalline n+ doped source/drain structures on either side of a gate stack. In embodiments, an amorphous material is employed to limit growth of polycrystalline source/drain material, allowing a high quality source/drain doped crystal to grow from an undamaged region and laterally expand to form a low resistance interface with a two-degree electron gas (2DEG) formed within the device layer. In some embodiments, regions of damaged GaN that may spawn competitive polycrystalline overgrowths are covered with the amorphous material prior to commencing raised source/drain growth.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Marko Radosavljevic, Sansaptak Dasgupta, Sanaz K. Gardner, Seung Hoon Sung, Han Wui Then, Robert S. Chau
  • Patent number: 10664407
    Abstract: A set of data entries is transferred via a memory mapped interface from an external peripheral device to a processor device and is stored in a shared memory region. Based on a first pointer to the shared memory region, a first process executed by the processor device processes a first group of the data entries. Based on a second pointer to the shared memory region, a second process executed by the processor device processes a second group of the data entries. The second process indicates the second pointer to the first process. The first process indicates a lower one of the first pointer and the second pointer to the peripheral device.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Anant Raj Gupta, Ingo Volkening, Jun Ye Zhou
  • Patent number: 10665522
    Abstract: A semiconductor device and method is disclosed. Devices shown include a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die. Devices shown further included a molded routing layer coupled to the integrated routing layer.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: May 26, 2020
    Assignee: Intel IP Corporation
    Inventors: Lizabeth Keser, Thomas Ort, Thomas Wagner, Bernd Waidhas
  • Patent number: 10664270
    Abstract: An apparatus and method for performing signed multiplication of packed signed/unsigned doublewords and accumulation with a quadword.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Mark Charney, Jesus Corbal, Venkateswara Madduri
  • Patent number: 10666288
    Abstract: Detailed herein are embodiments of systems, methods, and apparatuses for decompression using hardware and software. In hardware, an input buffer stores incoming input records from a compressed stream. A plurality of decoders decode at least one input record from the input buffer out output an intermediate record from the decoded data and a subset of the plurality of decoders to output a stream of literals. Finally, a reformat circuit formats an intermediate record into one of two types of tokens.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, James D. Guilford, Sean M. Gulley, Kirk S. Yap
  • Patent number: 10664272
    Abstract: In embodiments, apparatuses, methods and storage media (transitory and non-transitory) are described that are associated with receiving a call from an application at a shared library, accessing a first resource based at least in part on the first call, and storing a prefetch entry in a prefetch engine based at least in part on an address of a second resource in preparation to service a second call to the shared library that requires traversal of a plurality of stages at the shared library. A prefetch request may be performed based at least in part on the second call, and the second resource may be accessed based at least in part on a result of the prefetch request. In embodiments, the shared library may be a Message Passing Interface (MPI) library. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventor: Dmitry Igorevich Durnov
  • Patent number: 10666061
    Abstract: An electronic system may include a charging device and an electronic device. The charging device may include an input port, a charge circuit, a storage, and a connector device. The charging device may receive a direct current (DC) voltage at the input port. The charge circuit may receive the DC voltage and provide a charged voltage to the storage. The electronic device may include a body, a battery, a first pad directly on the battery and a second pad directly on the battery. The battery may receive the DC charged voltage when the electronic device is coupled to the charging device.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventor: Andrew Keates
  • Patent number: 10664027
    Abstract: The disclosed embodiments relate to methods, systems and apparatus for dynamic temperature aware functional safety. The disclosed embodiments provide adaptive techniques to track extended dynamic temperature range of a System-on-Chip (SOC) and automatically tune critical IP components of the SOC so that system can operate reliably even at high temperatures. The disclosed embodiments relax the overdesign of the SOC components by reusing existing components such as a ring oscillator to determine temperature at different regions of the SOC. In one embodiment, the disclosed principles use a Calibrated Ring Oscillator (CRO) temperature sensors. The CRO-based temperature sensors provide fast temperature measurement suitable for detecting dynamic temperature ranges and temperature rate of change. The CROs are existing on the SOC and do not require addition of additional sensors.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Amit Kumar Srivastava, Rao Jagannadha Rapeta, Asad Azam
  • Patent number: 10666265
    Abstract: An integrated circuit device may include programmable logic fabric disposed on a first integrated circuit die and having configuration memory. The integrated circuit device may also include a base die that may provide memory and/or operating supporting circuitry. The first die and the second die may be coupled using a high-speed parallel interface. The interface may employ microbumps. The first die and the second die may also include controllers for the interface.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Kevin Clark, Scott J. Weber, James Ball, Simon Chong, Ravi Prakash Gutala, Aravind Raghavendra Dasu, Jun Pin Tan