Abstract: This disclosure describes systems, methods, and devices related to traffic indications for multi-link devices (MLDs). A device may generate a first traffic indication map (TIM) with a first bitmap including a first indication that traffic is to be sent by a first access point (AP) device of the MLD to a first non-AP device of a second MLD using a first communication link The device may generate a second TIM with a second bitmap including a second indication that no traffic is to be sent by a second AP device of the MLD to a second non-AP device of the second MLD using a second communication link The device may send, using the first communication link, the beacon, the beacon including the first TIM and the second TIM. The device may send, using the first communication link, a data frame to the first non-AP device of the second MLD.

Abstract: The disclosure is directed to apparatus and methods for manufacturing including a collaborative robot, a camera operatively coupled to the collaborative robot, a memory coupled to the collaborative robot, and processing circuitry coupled to the memory, the processing circuitry configured to receive image data of at least one component intended for a printed circuit board (PCB), the image data collected by the camera operatively coupled to the collaborative robot, determine, based on the image data, a coordinate location for the component, and secure the component to the PCB using an end effector of the collaborative robot based on the received image data. In one embodiment, the collaborative robot is configured to operate alongside a human, the collaborative robot in combination with the camera configured to manufacture a computer system with the PCB.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

Abstract: An initializer for circle distribution on a 2D surface using a polar coordinate system for image compression, video compression, motion detection, and posture detection. The initializer can also be used for sphere distribution in a 3D shape. The initializer uses a mixed deterministic and iterative/stochastic approach. Using the polar coordinate system for initialization enables coverage of the user space, and after parameters are initialized, the method transitions to a cartesian coordinate system. Methods for using the polar system in CPU units by applying an XNOR/AND architecture for neural network model compression are also described. The neural network includes a perceptron for supervised learning of binary classifiers. The unit responsible for multiplication in a MAC architecture can be replaced with a non-linear expressive function. Thus, a neural network having a non-linear expressive perceptron (quadtron) is described for solving circle distribution and other problems.

Abstract: This disclosure describes systems, methods, and devices related to aligned channel access. A device may perform a first backoff countdown on a first link associated with a first station device (STA) of the device, wherein the device is a multi-link device (MLD). The device may detect a second backoff countdown associated with a second STA of the MLD after the first backoff countdown reaches zero. The device may determine to hold the first backoff countdown at zero based on the value of the second backoff countdown. The device may transmit in synchronization on the first link and on the second link from the first STA and the second STA respectively based on holding the first backoff countdown at zero.

Abstract: This disclosure describes systems, methods, and devices related to adding or removing communication access points (APs) affiliated with an associated AP multi-link device (AP-MLD). A non-AP-MLD may identify a communication link between the non-AP-MLD and an AP-MLD, the communication link previously used by the non-AP-MLD; encode a request frame comprising a multi-link reconfiguration element indicative of a request to add or remove the communication link; cause the non-AP-MLD to transmit the request frame to the AP-MLD; and identify a response frame received from the AP-MLD, the response frame comprising the multi-link reconfiguration element and indicating whether the communication link was accepted or rejected to be added or removed.

Abstract: This disclosure describes systems, methods, and devices related to WLAN sensing sounding. A device may identify a sensing null data packet (NDP) request frame received from a second device, the sensing NDP request frame associated with performing a wireless local area network channel sounding procedure; identify transmit parameters included in a transmit control field of the sensing NDP request frame; generate an NDP frame using the transmit parameters; and send, in response to the sensing NDP request frame, the NDP frame to the second device.

Abstract: Described herein are integrated circuit devices that include semiconductor devices near the center of the device, rather than towards the top or bottom of the device, and integrated inductors formed over the semiconductor devices. Power delivery to the device is on the opposite side of the semiconductor devices. The integrated inductors may be used for power step-down to reduce device thickness and/or a number of power rails.

Abstract: Described herein is a generalized optimal reduction scheme for reducing an array modulo a constant. The constant modulo operation calculates a result for array of bits xi, width n modulo an odd positive integer constant d, (e.g., x[n:0] mod d). Circuitry to perform such operation can be configured to compress the array of bits xi, width n into an array of bits yi width m. The techniques described herein enable the design of optimal circuitry via iterative exploration of all potential reduction strategies that are available given the input constraints.

Abstract: A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.

Abstract: Embodiments described herein provide a technique to facilitate the synchronization of workgroups executed on multiple graphics cores of a graphics core cluster. One embodiment provides a graphics core including a cache memory and a graphics core coupled with the cache memory. The graphics core includes execution resources to execute an instruction via a plurality of hardware threads and barrier circuitry to synchronize execution of the plurality of hardware threads, wherein the barrier circuitry is configured to provide a plurality of re-usable named barriers.

Abstract: This disclosure describes systems, methods, and devices related to bond strength measurement. A device may comprise a first portion of a plate connected to a movement mechanism, a second portion of the plate comprising a sticky probe and a third portion of the plate comprising a mirror with a reflective side pointing outwards. The device may further comprise an optical fiber sensor assembly comprising an optical fiber bundle for sending light through a first optical fiber and receiving light reflected from the mirror through a second optical fiber.

Abstract: Thermal heat spreaders and/or an IC die with solderable thermal structures may be assembled together with a solder array thermal interconnects. A thermal heat spreader may include a non-metallic material and one or more metallized surfaces suitable for bonding to a solder alloy employed as thermal interface material between the heat spreader and an IC die. An IC die may include a metallized back-side surface similarly suitable for bonding to a thermal interconnect comprising a solder alloy. Metallization on the IC die and/or heat spreader may comprise a plurality of solderable structures. A multi-chip package may include multiple IC die having different die thickness that are accommodated by a z-height thickness variation in the thermal interconnects and/or the solderable structures of the IC die or heat spreader.

Abstract: The techniques described in the detailed description above enable the manufacturing of circuits with increased performance and efficiency when performing division by a constant number. One embodiment provides circuitry including an input circuit to receive an input value including a plurality of bits, a logarithmic tree coupled with the input circuit, the logarithmic tree configured to compute an array of values based on a plurality of multi-bit groups of the plurality of bits of the input value, each value in the array of values includes a modulus of a corresponding multi-bit group with respect to the constant, a binary array adder to compute a quotient of the division operation based on the array of values, the input value, and the constant, and an output circuit to output the quotient.

Abstract: Described herein is a technique for automatic program code optimization for high-level synthesis. One embodiment provides a method comprising receiving input including first program code in a high-level language; translating the first program code into an intermediate language; constructing an equality graph (e-graph) from the intermediate language; interleaving control-flow, data path, and gate-level transformations to explore equivalent hardware designs represented by the e-graph; selecting a hardware design based on a cost function; extracting a representation of a selected hardware design in the intermediate language; generating second program code in the high-level language; and performing high-level synthesis using the second program code.

Abstract: A first computing system includes a data store with a sensitive dataset. The first computing system uses a feature extraction tool to perform a statistical analysis of the dataset to generate feature description data to describe a set of features within the dataset. A second computing system is coupled to the first computing system and does not have access to the dataset. The second computing system uses a data synthesizer to receive the feature description data and generate a synthetic dataset that models the dataset and includes the set of features. The second computing system trains a machine learning model with the synthetic data set and provides the trained machine learning model to the first computing system for use with data from the data store as an input.

Abstract: An apparatus comprising translator circuitry to receive a plurality of physical addresses of memory data, determine an offset associated with each of the physical page addresses and apply a tweak seed to each offset to generate a plurality of tweaks.

Abstract: The disclosure is directed to apparatus and methods for detection of out of position (OOP) components in a carrier tape forming machine. An apparatus includes cross track sensors coupled to the bus interface circuitry, the cross track sensors configured to detect OOP components prior to overlaying the components on the carrier tape with cover tape, optical sensors to detect the OOP components on the carrier tape after overlaying with cover tape and prior to sealing and to detect reflections from OOP components seated on the carrier tape, an amplifier coupled to the optical sensors to amplify signals generated by the optical sensors and set a range for determining whether the components are OOP, and relays to receive indications of detected OOP components, and a controller coupled to the relays to stop the carrier tape forming machine as a function of signals received by the relays.

Abstract: Embodiments described herein provide a technique to facilitate the broadcast or multicast of asynchronous loads to shared local memory of a plurality of graphics cores within a graphics core cluster. One embodiment provides a graphics processor including a cache memory a graphics core cluster coupled with the cache memory. The graphics core cluster includes a plurality of graphics cores. The plurality of graphics cores includes a graphics core configured to receive a designation as a producer graphics core for a multicast load, read data from the cache memory; and transmit the data read from the cache memory to a consumer graphics core of the plurality of graphics cores.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for sparse tensor storage for neural network accelerators. An example apparatus includes sparsity map generating circuitry to generate a sparsity map corresponding to a tensor, the sparsity map to indicate whether a data point of the tensor is zero, static storage controlling circuitry to divide the tensor into one or more storage elements, and a compressor to perform a first compression of the one or more storage elements to generate one or more compressed storage elements, the first compression to remove zero points of the one or more storage elements based on the sparsity map and perform a second compression of the one or more compressed storage elements, the second compression to store the one or more compressed storage elements contiguously in memory.

Abstract: An embodiment of an integrated circuit may comprise an array of hardware counters, and circuitry communicatively coupled to the array of hardware counters, the circuitry to count accesses to one or more selected pages of a memory with the array of hardware counters. Other embodiments are disclosed and claimed.

Abstract: Embodiments described herein provide a technique to enable access to entries in a surface state or sampler state using 64-bit virtual addresses. One embodiment provides a graphics core that includes memory access circuitry configured to facilitate access to the memory by functional units of the graphics core. The memory access circuitry is configured to receive a message to access an entry in a surface state or a sampler state associated with a parallel processing operation. The message specifies a base address for a surface state entry or sampler state entry. The circuitry can add the base address and the offset to determine a 64-bit virtual address for the entry in the surface state entry or the sampler state and submit a memory access request to the memory to access the entry of the surface state or sampler state.

Abstract: Described herein are integrated circuit devices that include semiconductor devices near the center of the device, rather than towards the top or bottom of the device. In this arrangement, heat can become trapped inside the device. Metal fill, such as copper, is formed within a portion of the device, e.g., over the semiconductor devices and any front side interconnect structures, to transfer heat away from the semiconductor devices and towards a heat spreader.

Abstract: Embodiments detailed herein relate to matrix operations. In particular, support for matrix (tile) addition, subtraction, and multiplication is described. For example, circuitry to support instructions for element-by-element matrix (tile) addition, subtraction, and multiplication are detailed. In some embodiments, for matrix (tile) addition, decode circuitry is to decode an instruction having fields for an opcode, a first source matrix operand identifier, a second source matrix operand identifier, and a destination matrix operand identifier; and execution circuitry is to execute the decoded instruction to, for each data element position of the identified first source matrix operand: add a first data value at that data element position to a second data value at a corresponding data element position of the identified second source matrix operand, and store a result of the addition into a corresponding data element position of the identified destination matrix operand.

Abstract: The disclosure relates to tuning configuration parameters for graphics pipeline for better user experience. A device for graphics processing, comprising: hardware engines; a graphics pipeline at least partly implemented by the hardware engines; and a tuner, coupled to the hardware engines and the graphics pipeline, the tuner to: collect statuses of the device during runtime for a previous frame; determine configuration parameters based on the collected statuses, the configuration parameters associated with three-dimensional 3D rendering, pre-processing and video encoding of the graphics pipeline; and tune the graphics pipeline with the determined configuration parameters for processing a next frame.

Abstract: Adjusting workload execution based on workload similarity. A processor may determine a similarity of a first workload to a second workload. The processor may adjust execution of the first workload based on execution parameters of the second workload and the similarity of the first workload to the second workload.

Abstract: Described herein is a graphics processor comprising a system interconnect and a graphics processor cluster coupled with the system interconnect. The graphics processor cluster includes circuitry configurable to generate per-frame neural representations of a multi-view video via incremental training and transferal of weights.

Abstract: Systems, methods, and apparatuses relating to instructions to reset software thread runtime property histories in a hardware processor are described. In one embodiment, a hardware processor includes a hardware guide scheduler comprising a plurality of software thread runtime property histories; a decoder to decode a single instruction into a decoded single instruction, the single instruction having a field that identifies a model-specific register; and an execution circuit to execute the decoded single instruction to check that an enable bit of the model-specific register is set, and when the enable bit is set, to reset the plurality of software thread runtime property histories of the hardware guide scheduler.

Abstract: A memory device that performs internal ECC (error checking and correction) can selectively return read data with application of the internal ECC or without application of the internal ECC, in response to different read commands from the memory controller. The memory device can normally apply ECC and return corrected data in response to a normal read command. In response to a retry command, the memory device can return the read data without application of the internal ECC.

Abstract: Systems, apparatuses, and methods to mitigate effects of glitch attacks on a broadcast communication bus are provided. The voltage levels of the communication bus are repeatedly sampled to identify glitch attacks. The voltage level on the communication bus can be overdriven or overwritten to either corrupt received messages or correct received messages.

Abstract: Apparatus and methods for thermal management of electronic user devices are disclosed herein. An example apparatus includes at least one of a user presence detection analyzer to identify a presence of a user relative to an electronic device based on first sensor data generated by a first sensor or at least one of an image data analyzer or a motion data analyzer to determine a gesture of the user relative to the device based on second sensor data generated by a second sensor; a thermal constraint selector to select a thermal constraint for a temperature of an exterior surface of the electronic device based on one or more of the presence of the user or the gesture; and a power source manager to adjust a power level for a processor of the electronic device based on the thermal constraint.

Abstract: The computer executable instructions include a command that accepts multiple user input through various command options. The command encapsulates and implements multiple original software algorithms that convert trunking design intent, expressed via the command options, into trunks on multiple layers of a process technology node. Once executed, the command generates shapes of trunks of specified topology on specified layers. The command includes a set of options to generate a simple or complex trunking topology. The command accepts topology, set of zones, nets and many other options that the user provides to the command to yield trunks of a desired topology. The topology description is relative; thus, it can easily adjust as design changes. The command together with its options represents trunk creation intent.

Abstract: Methods, apparatus, systems and articles of manufacture to identify a side-channel attack are disclosed. Example instructions cause one or more processors to generate an event vector based on one or more counts corresponding to tasks performed by a central processing unit; determine distances between the event vector and weight vectors of neurons in a self-organizing map; select a neuron of the neurons that results based on a determined distance; identify neurons that neighbor the selected neuron; and update at least one of a weight vector of the selected neuron or weight vectors of the neighboring neurons based on the determined distance of the selected neuron.

Abstract: Systems, methods, and devices for isolating a misbehaving accelerator circuit, such as an accelerator function unit or an accelerated function context, are provided. An integrated circuit may include a region that includes an accelerator circuit. When the accelerator circuit issues a request, another region of the integrated circuit or a processor connected to the integrated circuit may determine whether there is a misbehavior associated with the request and, in response to determining that there is a misbehavior associated with the request, may perform a misbehavior response to mitigate a negative impact of the misbehavior of the accelerator circuit.

Abstract: Systems, methods, and apparatuses relating to linear address masking architecture are described. In one embodiment, a hardware processor includes an address generation unit to generate a linear address for a memory access request to a memory, at least one control register comprising a user mode masking bit and a supervisor mode masking bit, a register comprising a current privilege level indication, and a memory management unit to mask out a proper subset of bits inside an address space of the linear address for the memory access request based on the current privilege level indication and either of the user mode masking bit or the supervisor mode masking bit to produce a resultant linear address, and output the resultant linear address.

Abstract: Disclosed examples include after a first tuning of hyperparameters in a hyperparameter space, selecting first hyperparameter values for respective ones of the hyperparameters; generating a polygonal shaped failure region in the hyperparameter space based on the first hyperparameter values; setting the first hyperparameter values to failure before a second tuning of the hyperparameters; and selecting second hyperparameter values for the respective ones of the hyperparameters in a second tuning region after the second tuning of the hyperparameters in the second tuning region, the second tuning region separate from the polygonal shaped failure region.

Abstract: Examples described herein relate to processor circuitry to issue a cache coherence message to a central processing unit (CPU) cluster by selection of a target cluster and issuance of the request to the target cluster, wherein the target cluster comprises the cluster or the target cluster is directly connected to the cluster. In some examples, the selected target cluster is associated with a minimum number of die boundary traversals. In some examples, the processor circuitry is to read an address range for the cluster to identify the target cluster using a single range check over memory regions including local and remote clusters. In some examples, issuance of the cache coherence message to a cluster is to cause the cache coherence message to traverse one or more die interconnections to reach the target cluster.

Abstract: A method for trajectory generation based on player tracking is described herein. The method includes determining a temporal association for a first player in a captured field of view and determining a spatial association for the first player. The method also includes deriving a global player identification based on the temporal association and the spatial association and generating a trajectory based on the global player identification.

Abstract: Methods, apparatus, systems and articles of manufacture for distributed training of a neural network are disclosed. An example apparatus includes a neural network trainer to select a plurality of training data items from a training data set based on a toggle rate of each item in the training data set. A neural network parameter memory is to store neural network training parameters. A neural network processor is to generate training data results from distributed training over multiple nodes of the neural network using the selected training data items and the neural network training parameters. The neural network trainer is to synchronize the training data results and to update the neural network training parameters.

Abstract: Examples described herein relate to a graphics processing apparatus that includes a memory device and a graphics processing unit (GPU). In some examples, the GPU is configured to execute a shader program that is to identify at least two code blocks that are independent from each other and cause execution of an unexecuted independent code block with available data based on use of a scoreboard to track data availability for independent code blocks. In some examples, execution of the shader program is to cause the GPU to select a first code block identifier for tracking completion of a dependency of the first independent code block. In some examples, execution of the shader program is to cause the GPU to identify an offset to a first instruction position in a sequence of instructions of the first independent code block in an instruction queue.

Abstract: Techniques are described related to digital radio control and operation. The various techniques described herein enable high-frequency local oscillator (LO) signal generation using injection locked cock multipliers (ILCMs). The techniques also include the use of LO signals for carrier aggregation applications for phased array front ends. Furthermore, the disclosed techniques include the use of array element-level control using per-chain DC-DC converters. Still further, the disclosed techniques include the use of adaptive spatial filtering and optimal combining of analog-to-digital converters (ADCs) to maximize dynamic range in digital beamforming systems.

Abstract: Embodiments of the present invention are directed to dual threshold voltage (VT) channel devices and their methods of fabrication. In an example, a semiconductor device includes a gate stack disposed on a substrate, the substrate having a first lattice constant. A source region and a drain region are formed on opposite sides of the gate electrode. A channel region is disposed beneath the gate stack and between the source region and the drain region. The source region is disposed in a first recess having a first depth and the drain region disposed in a second recess having a second depth. The first recess is deeper than the second recess. A semiconductor material having a second lattice constant different than the first lattice constant is disposed in the first recess and the second recess.

Abstract: Apparatuses, methods and storage medium associated with multi-camera devices are disclosed herein. In embodiments, a multi-camera device may include 3 or more camera sensors disposed on a world facing side of the multi-camera device. Further, the multi-camera device may be configured to provide a soft shutter button at a location on an opposite side to the world facing side, coordinated with locations of the 3 or more camera sensors that reduces likelihood of blocking of one or more of the 3 or more camera sensors. Other embodiments may be disclosed or claimed.

Abstract: An apparatus for encoding and decoding video receives a request to decode a current video frame. The apparatus determines whether encoding is within a threshold for a previous video frame. Additionally, the apparatus waits for the encoding to start if the encoding is within the threshold. Further, the apparatus provides a signal to begin encoding the current video frame. Also, the apparatus submits a decode workload to a graphics processor unit (GPU) for the current video frame. The apparatus additionally submits, in parallel with submitting the decode workload to the GPU, an encode workload to the GPU for the previous video frame.

Abstract: Methods, systems, and storage media are described for monitoring downlink control information (DCI). In particular, some embodiments may be directed to monitoring DCI for an indication of channel occupancy time (COT) information. Other embodiments may be described and/or claimed.

Abstract: A device to host a service producer in a 5G system (or 5G system architecture), a method to be performed at the device, and a non-transitory storage device storing instructions to be executed at the device. The method includes: decoding a request from a service consumer to manage one or more 5G quality of service (QoS) indicators (5QIs), each 5QI including a 5QI value and corresponding 5QI characteristics; configuring one or more network functions (NFs) of the 5GS with the 5QIs based on the request; and encoding for transmission to the service consumer a message including a result of managing the one or more 5QIs.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.

Abstract: Embodiments provided a blend circuit configured to perform a power optimized blend using blend circuitry configured such that the dynamic power consumed during the blending of two input color values is reduced when the input colors are close in value. When blending two identical input color values, a portion of the blend circuit can be bypassed and clock and/or data gated.

Abstract: Disclosed herein are IC structures with one or more decoupling capacitors based on dummy TSVs provided in a support structure. An example decoupling capacitor includes first and second capacitor electrodes and a capacitor insulator between them. The first capacitor electrode is a liner of a first electrically conductive material on sidewalls and a bottom of an opening in the support structure, the opening in the support structure extending from the first side towards, but not reaching, the second side. The capacitor insulator is a liner of a dielectric material on sidewalls and a bottom of the opening in the support structure lined with the first electrically conductive material. The second capacitor electrode is a second electrically conductive material filling at least a portion of the opening in the support structure lined with the first electrically conductive material and with the dielectric material.