Intel Patents

Intel Corporation designs and manufactures microprocessors and chipsets for computing and communications equipment manufacturers. Its products may be found in desktops, servers, tablets, smartphones and other devices.

Intel Patents by Type

  • Intel Patents Granted: Intel patents that have been granted by the United States Patent and Trademark Office (USPTO).
  • Intel Patent Applications: Intel patent applications that are pending before the United States Patent and Trademark Office (USPTO).
  • Patent number: 10295406
    Abstract: An optical spectral analyzer for measuring an optical multi-channel signal by separating the multi-channel signal and measuring a plurality of single-channel signals simultaneously. The spectral analyzer can include a demultiplexer configured to receive the multi-channel signal. The multi-channel signal can be a multi-channel wavelength range. The demultiplexer can separate the multi-channel signal into the plurality of single-channel signals including a first single-channel signal and a second single-channel signal. The spectral analyzer can include a plurality of optical paths. The plurality of optical paths can include a plurality of respective detectors for measuring an optical power of the respective single-channel signals. The detectors can convert the optical power of the respective single-channel signals to corresponding electrical signals.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Abram M Detofsky, Brett E Klehn
  • Patent number: 10295283
    Abstract: Generally discussed herein are devices and methods for thermal management of a component. An apparatus can include a phase change material substantially at a phase transition temperature of the phase change material, a component near, on, or at least partially in the phase change material, and a heat removal device to transfer heat energy away from the phase change material and maintain the phase change material substantially at the phase transition temperature.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Michael K. Patterson, Andrew C. Alduino
  • Patent number: 10292607
    Abstract: Technology for a wearable heart rate monitoring device is disclosed. The wearable heart rate monitoring device can include a heart rate sensor operable to collect sensor data, a modulator operable to generate a modulated signal that includes the sensor data, a housing configured to engage a body feature or surface in a manner that allows for heart rate detection, and a communication module configured to transmit the sensor data in the modulated signal to a mobile computing device via a wired connection that is power limited. The mobile computing device is typically configured to demodulate the modulated signal in order to extract the sensor data.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Brian K. Vogel, John C. Wei, Fai Angus Yeung
  • Patent number: 10294526
    Abstract: Embodiments of the present invention provide substrates having controllably co-located polymers of different sequences. Methods are provided that allow the fabrication of arrays of polymers on a substrate having controllably co-located polymers in regions of the array. For example, polymers of nucleic acids and peptides having different sequences and or compositions can be co-located within a region of a substrate. Also provided are arrays of DNA polymers wherein polymers having two different sequences are co-located within a region of an array. The co-located DNA polymers can comprise complementary DNA that is able to hybridize and form double stranded DNA. Arrays having regions comprising double stranded DNA are provided.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Yuan Gao, Gunjan Tiwari
  • Patent number: 10296489
    Abstract: A processor including a first vector register for storing a plurality of source data elements, a second vector register for storing a plurality of control elements, and a vector bit shuffle logic. Each of the control elements in the first vector register corresponds to a different source data element and includes a plurality of bit fields. Each of the bit fields is associated with a single corresponding bit position in a destination mask register and identifies a single bit from the corresponding source data element to be copied to the single corresponding bit position in the destination mask register. The vector bit shuffle logic is to read the bit fields from the second vector register and, for each bit field, to identify a single bit from a single corresponding source data element and copy it to a single corresponding bit position in the destination mask register.
    Type: Grant
    Filed: December 27, 2014
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Elmoustapha Ould-Ahmed-Vall, Jesus Corbal San Adrian, Robert Valentine, Mark J. Charney, Guillem Sole, Roger Espasa
  • Patent number: 10296246
    Abstract: Various embodiments are directed to providing integrity protection for a system management mode. During initialization, a hash value of a system management mode control routine may be determined. Subsequently, during operation, the hash value may be compared to a hash value of a system management mode control routine to be executed. The system management mode control routine to be executed may be determined to be authentic if the hash values are the same.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: May 21, 2019
    Assignee: INTEL CORPORATION
    Inventors: Jorge E. Gonzalez Diaz, Juan Manuel Cruz Alcaraz
  • Patent number: 10296464
    Abstract: In one embodiment, an apparatus includes: a storage having a plurality of entries each to store address information of an instruction and a count value of a number of executions of the instruction during execution of code including the instruction; and at least one comparator circuit to compare a count value from one of the plurality of entries to a threshold value, where the instruction is a tagged instruction of the code, the tagged instruction tagged by a static compiler prior to execution of the code. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventor: Ramanathan Sethuraman
  • Patent number: 10296217
    Abstract: Examples are disclosed for configuring a solid state drive (SSD) to operate in a storage mode or a memory mode. In some examples, one or more configuration commands may be received at a controller for an SSD having one or more non-volatile memory arrays. The SSD may be configured to operate in at least one of a storage mode, a memory mode or a combination of the storage mode or the memory mode based on the one or more configuration commands. Other examples are described and claimed.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Blaise Fanning, Mark A. Schmisseur, Raymond S. Tetrick, Robert J. Royer, Jr., David B. Minturn, Shane Matthews
  • Patent number: 10296467
    Abstract: A host central processing unit subsystem that writes information to external memory may provide policy to the external memory. Then every time a write comes from the host subsystem, a memory controller within the memory may check the write against the policy stored in the memory and decide whether or not to implement the write.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, Gilbert M. Wolrich, Kirk S. Yap
  • Patent number: 10296238
    Abstract: Technologies for accessing memory devices of a memory module device includes receiving a memory read request form a host and reading, in response to the memory read request, a rank of active non-volatile memory devices of the memory module device while contemporaneously accessing a volatile memory device of the memory module device. The volatile memory device shares data lines of a data bus of the memory module device with a spare non-volatile memory device associated with the rank of active non-volatile memory devices. During write operations, each of the rank of active non-volatile memory devices and the spare non-volatile memory device associated with the rank of active non-volatile memory devices are written to facilitate proper wear leveling of the non-volatile memory devices. The spare non-volatile memory device may replace a failed non-volatile memory devices of the rank of active non-volatile memory devices.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Kunal A. Khochare, Camille C. Raad, Richard P. Mangold, Shachi K. Thakkar
  • Patent number: 10296457
    Abstract: A processor includes a processing core to execute a transaction with a memory via a cache and a cache controller, associated with the processor, comprising an index mapper circuit to identify a physical memory address associated with the transaction, wherein the physical memory address comprises a plurality of bits, determine, based on the plurality of bits, a first set of bits encoding a tag value, a second set of bits encoding a page index value, and a third set of bits encoding a line index value, determine, based on the tag value, a bit-placement order for combining the second set of bits and the third set of bits, combine, based on the bit-placement order, the second set of bits and the third set of bits to form an index, and generate, based on the index, a mapping from the physical memory address to a cache line index value identifying a cache line in the cache, wherein the processing core is to access, based on the cache line, a memory location referenced by the physical memory address.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Ruchira Sasanka, Rajat Agarwal
  • Patent number: 10296366
    Abstract: Embodiments of an invention for virtualization exceptions are disclosed. In one embodiment, a processor includes instruction hardware, control logic, and execution hardware. The instruction hardware is to receive a plurality of instructions, including an instruction to enter a virtual machine. The control logic is to determine, in response to a privileged event occurring within the virtual machine, whether to generate a virtualization exception. The execution hardware is to generate a virtualization exception in response to the control logic determining to generate a virtualization exception.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Gilbert Neiger, Mayank Bomb, Manohar Castelino, Robert Chappell, David Durham, Barry Huntley, Anton Ivanov, Madhavan Parthasarathy, Scott Rodgers, Ravi Sahita, Vedvyas Shanbhogue
  • Patent number: 10296605
    Abstract: Techniques related to generating dictionaries for example based image processing algorithms are discussed. Such techniques may include iteratively performing example based image processing for candidate look up entries of candidate pairs from a training set database using a current dictionary to determine a test result for each of the look up entries of the candidate pairs and selecting one or more of the candidate pairs for entry in a resultant dictionary based on an error between the test result and a predetermined result entry for the candidate pairs.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Hila Barel, Gilad Michael, Edmond Chalom
  • Patent number: 10296250
    Abstract: In one embodiment, an apparatus comprises a storage device to receive, from a computing host, a request to append data to a data log. The storage device is further to identify a memory location after a last segment of the data log, append the data to the data log by writing the data to the memory location after the last segment of the data log, and provide, to the computing host, a key comprising an identification of the memory location at which the data was appended to the data log.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Benjamin L. Walker, August A. Camber, Jonathan Bryan Stern, Sanjeev Trika, Richard P. Mangold, Jawad Basit Khan, Anand Ramalingam
  • Patent number: 10299172
    Abstract: Technology for facilitating circuit switched fallback (CSFB) for a user equipment (UE) is disclosed. A mobility management entity (MME) can receive an optimized CSFB capability indicator from the UE. The MME can receive a requested service type associated with the UE. The MME can initiate a single radio voice call continuity (SR-VCC) handover of the UE to a circuit switched network based on the optimized CSFB capability of the UE. The MME can send an S1 application protocol (S1-AP) request message to an evolved node B (eNB). The S1AP message can include the optimized CSFB capability indicator and a single radio voice call continuity (SRVCC) indicator for the UE. The MME can receive a handover required message from the eNB.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: May 21, 2019
    Assignee: INTEL IP CORPORATION
    Inventors: Chang Hong Shan, Jerome Parron, Puneet Jain
  • Patent number: 10296333
    Abstract: Vector single instruction multiple data (SIMD) shift and rotate instructions are provided specifying: a destination vector register comprising fields to store vector elements, a first vector register, a vector element size, and a second vector register. Vector data fields of a first element size are duplicated. Duplicate vector data fields are stored as corresponding data fields of twice the first element size. Control logic receives an element size for performing a SIMD shift or rotation operation. Through selectors corresponding to a vector element, portions are selected from the duplicated data fields, the selectors corresponding to any particular vector element select all portions similarly from the duplicated data fields for that particular vector element responsive to the first element size, but selectors corresponding to any particular vector element select at least two portions from the duplicated data fields differently for that particular vector element responsive to a second element size.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Asaf Rubinstein, Tom Aviram
  • Patent number: 10296334
    Abstract: Apparatus, method, and system for performing a vector bit gather are describe herein. One embodiment of a processor includes: a first vector register storing one or more source data elements, a second vector register storing one or more control elements, and a vector bit gather logic. Each of the control elements includes a plurality of bit fields, each of which is associated with a plurality of corresponding bit positions in a destination vector register and is to identify a bit from the one or more corresponding source data element to be copied to each of the plurality of corresponding bit positions. The vector bit shuffle logic is to read the bit fields from the second vector register and, for each bit field, to identify a bit from the source data elements and responsively copy it to each of the plurality of corresponding bit positions in the destination vector register.
    Type: Grant
    Filed: December 27, 2014
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Jesus Corbal San Adrian, Mark J. Charney, Guillem Sole, Roger Espasa
  • Patent number: 10299302
    Abstract: Some demonstrative embodiments include apparatuses, devices, systems and methods peer-to-peer connection session setup. For example, a first peer-to-peer device may set a waiting timer to count a waiting period during a connection session setup of a session with a second peer-to-peer device; and during the waiting period, check whether the second peer-to-peer device is in the connection session setup by transmitting a probe request to the second peer-to-peer device, the probe request including an Information (Info) attribute.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: May 21, 2019
    Assignee: INTEL IP CORPORATION
    Inventors: Emily H. Qi, Elad Levy, Idan Maor
  • Patent number: 10296335
    Abstract: An apparatus and method are described for efficiently processing and reassigning interrupts. For example, one embodiment of an apparatus comprises: a plurality of cores; and an interrupt controller to group interrupts into a plurality of interrupt domains, each interrupt domain to have a set of one or more interrupts assigned thereto and to map the interrupts in the set to one or more of the plurality of cores.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: May 21, 2019
    Assignee: INTEL CORPORATION
    Inventors: Yogesh Deshpande, Pandurang V Deshpande
  • Patent number: 10296342
    Abstract: Systems, methods, and apparatuses for executing an instruction are described. For example, an instruction includes at least an opcode, a field for a packed data source operand, and a field for a packed data destination operand. When executed, the instruction causes for each data element position of the source operand, add to a value stored in that data element position all values stored in preceding data element positions of the packed data source operand and store a result of the addition into a corresponding data element position of the packed data destination operand.
    Type: Grant
    Filed: July 2, 2016
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: William M. Brown, Elmoustapha Ould-Ahmed-Vall
  • Patent number: 10296347
    Abstract: Fusible instructions and logic provide OR-test and AND-test functionality on multiple test sources. Some embodiments include a processor decode stage to decode a test instruction for execution, the instruction specifying first, second and third source data operands, and an operation type. Execution units, responsive to the decoded test instruction, perform one logical operation, according to the specified operation type, between data from the first and second source data operands, and perform a second logical operation between the data from the third source data operand and the result of the first logical operation to set a condition flag. Some embodiments generate the test instruction dynamically by fusing one logical instruction with a prior-art test instruction. Other embodiments generate the test instruction through a just-in-time compiler. Some embodiments also fuse the test instruction with a subsequent conditional branch instruction, and perform a branch according to how the condition flag is set.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Maxim Loktyukhin, Robert Valentine, Julian C. Horn, Mark J. Charney
  • Patent number: 10296343
    Abstract: A processing device including a first shadow register, a second shadow register, and an instruction execution circuit, communicatively coupled to the first shadow register and the second shadow register, to receive a sequence of instructions comprising a first local commit marker, a first global commit marker, and a first register access instruction referencing an architectural register, speculatively execute the first register access instruction to generate a speculative register state value associated with a physical register, responsive to identifying the first local commit marker, store, in the first shadow register, the speculative register state value, and responsive to identifying the first global commit marker, store, in the second shadow register, the speculative register state value.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Vineeth Mekkat, Jason M. Agron, Youfeng Wu
  • Patent number: 10296416
    Abstract: A processor of an aspect includes a decode unit to decode a read from memory instruction. The read from memory instruction is to indicate a source memory operand and a destination storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the read from memory instruction, is to read data from the source memory operand, store an indication of defective data in an architecturally visible storage location, when the data is defective, and complete execution of the read from memory instruction without causing an exceptional condition, when the data is defective. Other processors, methods, systems, and instructions are disclosed.
    Type: Grant
    Filed: July 2, 2016
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Ashok Raj, Ron Gabor, Hisham Shafi, Sergiu Ghetie, Mohan J. Kumar, Theodros Yigzaw, Sarathy Jayakumar, Neeraj S. Upasani
  • Patent number: 10296338
    Abstract: In one embodiment, a processor includes: an accelerator associated with a first address space; a core associated with a second address space and including an alternate address space configuration register to store configuration information to enable the core to execute instructions from the first address space; and a control logic to configure the core based in part on information in the alternate address space configuration register. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Brent R. Boswell, Banu Meenakshi Nagasundaram, Michael D. Abbott, Srikanth Dakshinamoorthy, Jason M. Howard, Joshua B. Fryman
  • Patent number: 10296660
    Abstract: Detailed herein are embodiments of systems, methods, and apparatuses to be used for feature searching using an entry-based searching structure.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: May 21, 2019
    Assignee: INTEL CORPORATION
    Inventor: Hsiang-Tsung Kung
  • Patent number: 10296399
    Abstract: An apparatus for providing data coherency is described herein. The apparatus includes a global persistent memory. The global persistent memory is accessed using a protocol that includes input/output (I/O) semantics and memory semantics. The apparatus also includes a reflected memory region. The reflected memory region is a portion of the global persistent memory, and each node of a plurality of nodes maps the reflected memory region into a space that is not cacheable. Further, the apparatus includes a semaphore memory. The semaphore memory provides a hardware assist for enforced data coherency.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Debendra Das Sharma, Mohan J. Kumar, Balint Fleischer
  • Patent number: 10296766
    Abstract: Technologies for secure enumeration of USB devices include a computing device having a USB controller and a trusted execution environment (TEE). The TEE may be a secure enclave protected secure enclave support of the processor. In response to a USB device connecting to the USB controller, the TEE sends a secure command to the USB controller to protect a device descriptor for the USB device. The secure command may be sent over a secure channel to a static USB device. A driver sends a get device descriptor request to the USB device, and the USB device responds with the device descriptor. The USB controller redirects the device descriptor to a secure memory buffer, which may be located in a trusted I/O processor reserved memory region. The TEE retrieves and validates the device descriptor. If validated, the TEE may enable the USB device for use. Other embodiments are described and claimed.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Soham Jayesh Desai, Reshma Lal, Pradeep Pappachan, Bin Xing
  • Patent number: 10297073
    Abstract: Embodiments provide for a graphics processing apparatus including logic to receive data from an input buffer. The data can define a set of data points, where each data point includes one or more dimensions. The logic is configured to process the received data points to perform in-place construct a left-balanced and complete point k-d tree of the data points within the input buffer.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: May 21, 2019
    Assignee: INTEL CORPORATION
    Inventor: Ingo Wald
  • Patent number: 10296459
    Abstract: Disclosed embodiments relate to remote atomic operations (RAO) in multi-socket systems. In one example, a method, performed by a cache control circuit of a requester socket, includes: receiving the RAO instruction from the requester CPU core, determining a home agent in a home socket for the addressed cache line, providing a request for ownership (RFO) of the addressed cache line to the home agent, waiting for the home agent to either invalidate and retrieve a latest copy of the addressed cache line from a cache, or to fetch the addressed cache line from memory, receiving an acknowledgement and the addressed cache line, executing the RAO instruction on the received cache line atomically, subsequently receiving multiple local RAO instructions to the addressed cache line from one or more requester CPU cores, and executing the multiple local RAO instructions on the received cache line independently of the home agent.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Doddaballapur N. Jayasimha, Samantika S. Sury, Christopher J. Hughes, Jonas Svennebring, Yen-Cheng Liu, Stephen R. Van Doren, David A. Koufaty
  • Patent number: 10296432
    Abstract: Methods for invasive debug of a processor without processor execution of instructions are disclosed. As a part of a method, a memory mapped I/O of the processor is accessed using a debug bus and an operation is initiated that causes a debug port to gain access to registers of the processor using the memory mapped I/O. The invasive debug of the processor is executed from the debug port via registers of the processor.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: May 21, 2019
    Assignee: INTEL CORPORATION
    Inventors: Karthikeyan Avudaiyappan, Brian McGee
  • Patent number: 10296835
    Abstract: Methods and systems may provide for receiving a physiological signal from a sensor configuration associated with a mobile device. A qualitative analysis may be conducted for each of a plurality of noise sources in the physiological signal to obtain a corresponding plurality of qualitative ratings. In addition, at least the plurality of qualitative ratings may be used to determine whether to report the physiological signal to a remote location. In one example, a quantitative analysis is conducted for each of the plurality of noise sources to obtain an overall quality level, wherein the overall quality level is also used to determine whether to report the physiological signal to the remote location.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventor: Amit S. Baxi
  • Patent number: 10297542
    Abstract: A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed circuit board (PCB). The capacitor may be mounted within a cavity formed in the die side surface of the package substrate or the land side surface of the package substrate. Mounting a capacitor within a cavity may reduce the form factor of the package. The die may be mounted within a cavity formed in the die side surface of the package substrate. Solder balls connecting the package to the PCB may be mounted within one or more cavities formed in one or both of the package substrate and the PCB.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: MD Altaf Hossain, Scott A. Gilbert
  • Patent number: 10296823
    Abstract: Associative memory systems, methods and computer program products are provided. An associative memory system includes a distributed associative memory base including a network of networks of associative memory networks. A respective associative memory network includes associations among a respective observer memories and a plurality of observed memories that are observed by the respective observer memory. Ones of the associative memory networks are physically and/or logically independent from other ones of the associative memory networks. A processing system is configured to observe associations into and imagine associations from, the distributed associative memory base using multiple streaming queues that correspond to respective ones of multiple rows in the associative memory networks. The processing system is further configured to determine a cognitive distance between a term and a class of terms, the cognitive distance being returned responsive to a query of the distributed associative memory base.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Paul Hofmann, Manuel Aparicio, IV
  • Patent number: 10297085
    Abstract: Systems, apparatuses and methods of creating virtual objects may provide for segmenting one or more objects in a scene and highlighting a selected object from the segmented one or more objects based on an input from a user. In one example, a scene-based virtual object is created from the selected object and a behavior is assigned to the scene-based virtual object.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventor: Glen J. Anderson
  • Patent number: 10297541
    Abstract: Microelectronic devices having a multiple-component substrate assembly. A primary supports one or more integrated circuits, and an auxiliary substrate is coupled to, and makes electrical connections with, the primary substrate. The primary substrate will define a pinout for some or all contacts of the integrated circuit, and the auxiliary substrate will provide an additional pinout option. Different configurations of a single primary substrate may be adapted to different applications through use of different configurations of auxiliary substrates.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Min Suet Lim, Mooi Ling Chang, Eng Huat Goh, Say Thong Tony Tan, Tin Poay Chuah
  • Patent number: 10297002
    Abstract: An apparatus and method are described for using a touch screen device to control an external display. For example, one embodiment of an apparatus comprises a touch screen to receive user touch input and display images; a processor communicatively coupled to the touch screen; a wireless session management module to establish and maintain a wireless display connection with an extended screen responsive to commands from the processor; and the processor to execute a process responsive to the user touch input to transform the touch screen or a portion thereof to a remote control touchpad device usable to provide control functions for content displayed on the extended screen.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Tri T. Khuong, Chandrasekaran Sakthivel, Kamalakar V. Pawar
  • Patent number: 10297001
    Abstract: Systems and methods may provide a graphics processor that may identify operating conditions under which certain floating point instructions may utilize power to fewer hardware resources compared to when the instructions are executing under other operating conditions. The operating conditions may be determined by examining operands used in a given instruction, including the relative magnitudes of the operands and whether the operands may be taken as equal to certain defined values. The floating point instructions may include instructions for an addition operation, a multiplication operation, a compare operation, and/or a fused multiply-add operation.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Subramaniam Maiyuran, Shubh B. Shah, Ashutosh Garg, Jin Xu, Thomas A. Piazza, Jorge F. Garcia Pabon, Michael K. Dwyer
  • Patent number: 10297047
    Abstract: One embodiment provides for a general-purpose graphics processor comprising a hardware graphics rendering pipeline configured to perform multisample anti-aliasing, the hardware graphics rendering pipeline including pixel processing logic to determine color data for multiple sample locations of each pixel in a set of pixels and to contiguously pack the color data for the multiple sample locations of each pixel for storage to a multisample render target.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Prasoonkumar Surti, Abhishek R. Appu
  • Patent number: 10297046
    Abstract: Various embodiments are generally directed to techniques for reducing storage access bandwidth requirements in retrieving a texture image from a storage for applying textures to rendered objects by rendering the texture image itself into the storage to reduce the storage space in which the texture image is stored and to arrange portions of the texture image to be retrieved with fewer accesses. A device to render images includes a processor component; a color analyzer to determine a clear color of a texture image stored as source texture data; and a rendering routine to render the texture image into a storage as reduced texture data, the rendering routine to selectively store in the reduced texture data pixel color values retrieved from the source texture data that are associated with pixels of the texture image not colored with the clear color. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventor: Bimal Poddar
  • Patent number: 10297302
    Abstract: An apparatus is described that includes a semiconductor chip memory array having resistive storage cells. The apparatus also includes a comparator to compare a first word to be written into the array against a second word stored in the array at the location targeted by a write operation that will write the first word into the array. The apparatus also includes circuitry to iteratively write to one or more bit locations where a difference exists between the first word and the second word with increasing write current intensity with each successive iteration.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Charles Augustine, Shigeki Tomishima, Wei Wu, Shih-Lien Lu, James W. Tschanz, Georgios Panagopoulos, Helia Naeimi
  • Patent number: 10297467
    Abstract: Self-aligned via and plug patterning for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate. The first layer includes a grating of alternating metal lines and dielectric lines in a first direction. A second layer of the interconnect structure is disposed above the first layer. The second layer includes a grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. Each metal line of the grating of the second layer is disposed on a recessed dielectric line having alternating distinct regions of a first dielectric material and a second dielectric material corresponding to the alternating metal lines and dielectric lines of the first layer of the interconnect structure.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Charles H. Wallace, Paul A. Nyhus
  • Patent number: 10296871
    Abstract: Systems and methods for dynamically creating collaborative teams and managing collaborative work of a team are generally disclosed herein. One example embodiment includes the dynamic creation of a collaborative team by creating an association between team members via a managing module. The managing module may be capable of managing, among other things, team members on a team, tasks and goals of each member of the team, as well as documentation associated with the team. In some embodiments, the managing module may use a chat or messaging protocol to manage collaborative modifications to documents of the team.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Stanley Mo, Robert Staudinger, Rita H Wouhaybi, Mubashir A Mian, Tobias Kohlenberg
  • Patent number: 10297499
    Abstract: Techniques and methods related to forming a wrap-around contact on a semiconductor device, and apparatus, system, and mobile platform incorporating such semiconductor devices.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Jeffrey S. Leib, Ralph T. Troeger, Daniel Bergstrom
  • Patent number: 10297567
    Abstract: Described herein are devices and techniques for thermocompression bonding. A device can include a housing, a platform, and a plasma jet. The housing can define a chamber. The platform can be located within the chamber and can be proximate a thermocompression chip bonder. The plasma jet can be located proximate the platform. The plasma jet can be movable about the platform. The plasma jet can include a nozzle arranged to direct a plasma gas onto the platform. Also described are other embodiments for thermocompression bonding.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Donglai David Lu, Jimin Yao, Amrita Mallik, George S. Kostiew, Shawna M. Liff
  • Patent number: 10296224
    Abstract: Provided are an apparatus, system and method for using a validity table indicating whether physical addresses have valid data to optimize write and defragmentation operations. A non-volatile memory storage device has non-volatile memory and a main memory. A memory controller reads and writes to the non-volatile memory and maintains in the main memory a logical-to-physical address table indicating, for each logical address of a plurality of logical addresses, a physical address in the non-volatile memory having data for the logical address. The main memory maintains a validity table indicating for each physical address of a plurality of physical addresses in the non-volatile memory whether the physical address has valid data.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: May 21, 2019
    Assignee: INTEL CORPORATION
    Inventors: Peng Li, William K. Lui, Sanjeev N. Trika
  • Patent number: 10297927
    Abstract: A multilayer package and wireless communication device for high frequency communications, for example large-scale millimeter (mmWave) phased arrays having wide scanning range, wide bandwidth, and high efficiency. The multilayer package comprises a plurality of patch antennas disposed on a first substrate, a plurality of slotted patch antennas disposed on a third substrate, the first substrate and the third substrate being disposed on opposing sides of a second substrate, a plurality of antenna feeds disposed on a fourth substrate, the fourth substrate being disposed adjacent to the third substrate, a plurality of dipoles disposed on the first substrate, the second substrate, the third substrate, and the fourth substrate, and an impedance transformer, disposed within one or more additional substrates. The wireless communication device can include the multilayer package and an integrated circuit, wherein each of the plurality of antenna feeds is coupled to the integrated circuit by the impedance transformer.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventor: Arnaud Lucres Amadjikpe
  • Patent number: 10299147
    Abstract: A method includes receiving a composite signal (R(k)) comprising transmissions from a plurality of cells, and identifying a plurality of candidate cells (Nm) based on a first detection metric (?m) with respect to the composite signal (R(k)). The method also includes filtering the plurality of candidate cells (Nm) with respect to cell identifiers (m) of the plurality of candidate cells to obtain a plurality of filtered candidate cells (Nm?), and selecting from the plurality of filtered candidate cells (Nm?) a plurality of selected cells according to a selection criterion.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: May 21, 2019
    Assignee: Intel IP Corporation
    Inventors: Wen Xu, Xiaojun Ma
  • Patent number: 10299295
    Abstract: Methods, apparatuses, and computer readable media for pre-association frame exchange using random access are disclosed. An apparatus of a high-efficiency wireless local-area network (HEW) master station is disclosed. The apparatus includes transceiver circuitry and processing circuitry which may be configured to generate a trigger frame for uplink random access (TF-R), and transmit the TF-R. The transceiver circuitry and processing circuitry may be further configured to receive one or more responses in accordance with orthogonal frequency division multiple-access (OFDMA) to the trigger frame from one or more pre-association stations where the responses comprise pre-association identifiers corresponding to the one or more pre-association stations.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: May 21, 2019
    Assignee: Intel IP Corporation
    Inventors: Chittabrata Ghosh, Robert J. Stacey
  • Patent number: 10298065
    Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for wireless power transfer with improved device identification and signaling security. A Power Receiving Unit (PRU) may include a receive resonator module to receive power from a Power Transmitting Unit (PTU) over an inductive resonant coupling link. The power may be modulated to provide signaling between the PRU and the PTU over the resonant coupling link. The PRU may also include a signaling link communication module to provide a second type of signaling between the PRU and the PTU over a wireless communication link. The PRU may further include a controller module to receive a random number, generated by the PTU, over the resonant coupling link; calculate an encoded response based on the random number and on an identifier of the PRU; and transmit the encoded response to the PTU over the wireless communication link, for verification by the PTU.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Yongwei Wu, Ahmad Khoshnevis
  • Patent number: 10297670
    Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: May 21, 2019
    Assignee: INTEL CORPORATION
    Inventors: Glenn A. Glass, Anand S. Murthy, Tahir Ghani