Intel Patents

Intel Corporation designs and manufactures microprocessors and chipsets for computing and communications equipment manufacturers. Its products may be found in desktops, servers, tablets, smartphones and other devices.

Intel Patents by Type

  • Intel Patents Granted: Intel patents that have been granted by the United States Patent and Trademark Office (USPTO).
  • Intel Patent Applications: Intel patent applications that are pending before the United States Patent and Trademark Office (USPTO).
  • Publication number: 20180263016
    Abstract: In one embodiment, the present disclosure provides a self-optimizing network (SON) coordination module that includes a conflict detection module configured to receive operational information from at least one capacity and coverage optimization (CCO) module and at least one of an energy savings management (ESM) and/or a cell outage compensation (COC) module, wherein the at least one CCO module and the at least one of the ESM module and/or the COC module are associated with at least one eNodeB (eNB) in communication with the conflict detection module. The conflict detection module is configured to determine a conflict between operational information of the CCO module and at least one of the ESM module and/or the COC module. The SON coordination module also includes a conflict resolution module configured to resolve a conflict between the operational information of the CCO module and at least one of the ESM module and/or the COC module based on, at least in part, one or more conflict resolution rules.
    Type: Application
    Filed: May 11, 2018
    Publication date: September 13, 2018
    Applicant: Intel IP Corporation
    Inventor: JOEY CHOU
  • Publication number: 20180261292
    Abstract: In one embodiment, an apparatus comprises a NAND flash memory device comprising a memory device controller and a memory NAND flash memory array, the NAND flash memory device to program data into a plurality of NAND flash memory cells coupled to a wordline in a single program sequence, wherein the plurality of NAND flash memory cells are coupled to a first plurality of bitlines and a second plurality of bitlines; couple the first plurality of bitlines to a fixed bias voltage in response to a first read command; apply a read voltage to the wordline coupled to the plurality of NAND flash memory cells; and sense, via the second plurality of bitlines, data stored in NAND flash memory cells coupled to the wordline, wherein at least some bitlines of the second plurality of bitlines are each in between and directly adjacent to two respective bitlines coupled to the fixed bias voltage.
    Type: Application
    Filed: March 7, 2017
    Publication date: September 13, 2018
    Applicant: Intel Corporation
    Inventors: Mark Helm, Aaron Yip
  • Publication number: 20180262975
    Abstract: Air interface resource utilization techniques for wireless communication networks are described. According to various such techniques, one or more narrow band resource regions (NBRRs) may be defined for use in conjunction with narrow band (NB) transmissions in an NB cell. In some embodiments, one or more such NBRRs may be designated as broadcast NBRRs, and may be used to carry a majority, most, or all of the broadcasted information within the NB cell. In various embodiments, another NBRR may be designated as a primary NBRR, and may be used to carry synchronization signals for the NB cell. In some such embodiments, the primary NBRR may also be used to carry NB physical broadcast channel (NB-PBCH) transmissions and NB master information blocks (NB-MIBs). Other embodiments are described and claimed.
    Type: Application
    Filed: April 2, 2016
    Publication date: September 13, 2018
    Applicant: Intel IP Corporation
    Inventors: Marta MARTINEZ TARRADELL, Debdeep CHATTERJEE, Ralf BENDLIN
  • Publication number: 20180261785
    Abstract: Embodiments related to emissive devices for displays are discussed. Some embodiments include light emitting diodes including an electron transport layer core having a tube shape with an inner and an outer sidewall, an emission layer on the inner and outer sidewalls, and a hole transport layer on the emission layer, displays and systems including such light emitting diodes, and methods for fabricating them. Other embodiments include emissive laser devices having an emission layer between a hole transport layer and an electron transport layer and first and second metasurface mirrors adjacent to the hole transport layer and the electron transport layer, respectively, displays and systems including such emissive laser devices, and methods for fabricating them.
    Type: Application
    Filed: March 12, 2018
    Publication date: September 13, 2018
    Applicant: Intel Corporation
    Inventors: Khaled AHMED, Ali KHAKIFIROOZ, Richmond HICKS
  • Publication number: 20180263015
    Abstract: Adaptive paging techniques for EC-capable devices are described. In one embodiment, for example, an apparatus may comprise at least one memory and logic for an evolved node B (eNB), at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to receive an S1 paging message comprising a user equipment (UE) identifier (ID) associated with a UE and an extended coverage (EC) capability indicator indicating that the UE is EC-capable and page the UE using an EC paging sequence based on receipt of the S1 paging message, the EC paging sequence to comprise a series of transmissions of a radio resource control (RRC) paging message, the logic to truncate the EC paging sequence based on a determination that the UE has responded to RRC paging. Other embodiments are described and claimed.
    Type: Application
    Filed: May 14, 2018
    Publication date: September 13, 2018
    Applicant: INTEL IP CORPORATION
    Inventors: RICHARD C. BURBIDGE, MARTA MARTINEZ TARRADELL, YOUN HYOUNG HEO, HYUNG-NAM CHOI
  • Publication number: 20180262224
    Abstract: The disclosure generally relates to a method, apparatus and system for identifying non-compliant radio emissions and for enforcing compliance. In one embodiment, the disclosure relates to a dynamic radiation control of a radio by measuring a signal attribute for an outbound signal having a protocol; comparing the signal attribute with a predefined mask, the predefined mask governed by at least one of a radio location or a signal protocol; and determining whether to transmit the outbound signal.
    Type: Application
    Filed: December 8, 2017
    Publication date: September 13, 2018
    Applicant: Intel Corporation
    Inventors: Hossein Alavi, Farhana Sheikh, Markus Dominik Mueck, Vladimir Ivanov
  • Publication number: 20180261694
    Abstract: Monolithic FETs including a channel region of a first semiconductor material disposed over a substrate. While a mask, such as a gate stack or sacrificial gate stack, is covering the channel region, an impurity-doped compositionally graded semiconductor is grown, for example on at least a drain end of the channel region to introduce a carrier-blocking conduction band offset and/or a wider band gap within the drain region of the transistor. In some embodiments, the compositional grade induces a carrier-blocking band offset of at least 0.25 eV. The wider band gap and/or band offset contributes to a reduced gate induced drain leakage (GIDL). The impurity-doped semiconductor may be compositionally graded back down from the retrograded composition to a suitably narrow band gap material providing good ohmic contact. In some embodiments, the impurity-doped compositionally graded semiconductor growth is integrated into a gate-last, source/drain regrowth finFET fabrication process.
    Type: Application
    Filed: September 25, 2015
    Publication date: September 13, 2018
    Applicant: Intel Corporation
    Inventors: Gilbert Dewey, Willy Rachmady, Matthew V. Metz, Chandra S. Mohapatra, Sean T. Ma, Jack T. Kavalieros, Anand S. Murthy, Tahir Ghani
  • Publication number: 20180263006
    Abstract: Logic to “loosely” manage synch frame transmissions in a synch network via the devices synched to the network that implement the logic. Logic may distributedly adjust the frequency of attempting synch frame transmissions without estimating the size of the neighborhood. Logic in devices of a synch network to let each device maintain a Transmission Window (TW). Logic to determine the frequency of attempting synch frame transmissions based upon the TW. Logic to increase TW if the device detects a synch frame transmission. Logic to decrease TW if the device successfully transmits a synch frame. Logic to balance power consumption and discovery timing by adjusting the decrease in TW responsive to a synch transmission in relation to the increase in TW responsive to detection of a synch transmitted by another device.
    Type: Application
    Filed: June 28, 2016
    Publication date: September 13, 2018
    Applicant: Intel IP Corporation
    Inventors: Emily H. Qi, Po-Kai Huang, Minyoung Park, Adrian P. Stephens
  • Publication number: 20180255879
    Abstract: A method for providing pressure feedback is described herein. The method includes receiving, via a processor, pressure sensor data from a plurality of pressure sensors over a period of time. The method also includes receiving, via the processor, movement data from a plurality of sensors over the period of time. The method also further includes sending, via the processor, pressure sensor data and movement data to a data service. The method also includes receiving, via the processor, a feedback from data service.
    Type: Application
    Filed: September 25, 2015
    Publication date: September 13, 2018
    Applicant: INTEL CORPORATION
    Inventors: Joanna R. Taryma, Adrian Weber
  • Publication number: 20180260040
    Abstract: A system for a tracker for cursor navigation is described herein. The system includes a display, camera, memory, and processor. The memory that is to store instructions and is communicatively coupled to the camera and the display. The processor is communicatively coupled to the camera, the display, and the memory. When the processor is to execute the instructions, the processor is to extract an object mask of an object and execute an optical flow on good feature points from the object mask. The processor is also to estimate a movement of the object and render a cursor on the display based on the movement of the object.
    Type: Application
    Filed: May 14, 2018
    Publication date: September 13, 2018
    Applicant: Intel Corporation
    Inventors: Maoz Madmony, Kfir Viente, Ovadya Menadeva, Itamar Glazer
  • Publication number: 20180260965
    Abstract: Techniques are provided for global (non-rigid) scan point registration between a scanned object and an associated model, from an arbitrary initial starting position, based on a combination of iterative coarse registration and fine registration. A methodology implementing the techniques according to an embodiment includes generating a model transformation based on a coarse registration between the model and the point scan. The method further includes calculating an alignment metric based on a distance measurement between the point scan and the transformed model. If the alignment metric exceeds a selected threshold value, a fine registration is performed between the transformed model and the point scan. Otherwise, the method continues by performing a random rotation of the model; a translation of the rotated model towards a centroid of the point scan; and iterating the coarse registration using the translated model until the alignment metric is achieved, after which the fine registration is performed.
    Type: Application
    Filed: March 9, 2017
    Publication date: September 13, 2018
    Applicant: INTEL CORPORATION
    Inventors: Rana Hanocka, Shahar Fleishman, Jackie Assa
  • Patent number: 10071544
    Abstract: A separation apparatus for separating a superposed substrate in which a processing target substrate and a supporting substrate are joined together with an adhesive, into the processing target substrate and the supporting substrate, includes: a first holding unit which holds the processing target substrate; a second holding unit which holds the supporting substrate; a moving mechanism which relatively moves the first holding unit or the second holding unit in a horizontal direction; a load measurement unit which measures a load acting on the processing target substrate and the supporting substrate when the processing target substrate and the supporting substrate are separated; and a control unit which controls the moving mechanism based on the load measured by the load measurement unit.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: September 11, 2018
    Assignees: Tokyo Electron Limited, INTEL CORPORATION
    Inventors: Osamu Hirakawa, Masaru Honda, Akira Fukutomi, Takeshi Tamura, Jiro Harada, Kazutaka Noda, Xavier Francois Brun
  • Patent number: 10073138
    Abstract: An apparatus is described that includes a plurality of circuits each designed to exhibit a unique signature code that is determined from manufacturing tolerances associated with a manufacturing process used to manufacture the circuits. The apparatus also includes error circuitry to determine an error has arisen based on a change in signature codes from the plurality of circuits.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: Suraj Sindia, Robert Kwasnick, Dhruv Singh
  • Patent number: 10073513
    Abstract: In an embodiment, a processor includes a plurality of cores. Each core includes a core power unit to detect one or more power management events, and in response to the one or more power management events, initiate a protected power management mode in the core. Software interrupts to the core may be disabled during the protected power management mode. The core is to execute power management code during the protected power management mode. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: William C. Rash, Martin G. Dixon, Yazmin A. Santiago
  • Patent number: 10073718
    Abstract: Apparatuses, methods and storage medium for computing including determination of work placement on processor cores are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a favored core of the processor cores. The one or more processors, devices, and/or circuitry may be configured to determine whether to migrate a thread to or from the favored core. In some embodiments, the determination may be by a process executed by a driver and/or by an algorithm executed by a power control unit of the processor.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: Guy M. Therien, Michael D. Powell, Venkatesh Ramani, Arijit Biswas, Guy G. Sotomayor
  • Patent number: 10073260
    Abstract: According to the present invention there is provided a method of reducing speckle effects in a projected image which is displayed on a display surface, comprising the steps of transmitting an input light beam to a first interferometer, generating a plurality of primary transmit beams at the first interferometer using the input light beam, using the plurality of primary transmit beams to generate interference fringes at a display surface.
    Type: Grant
    Filed: January 21, 2013
    Date of Patent: September 11, 2018
    Assignee: INTEL CORPORATION
    Inventors: Jonathan Masson, Nicolas Abele
  • Patent number: 10073483
    Abstract: An apparatus is described having a reference voltage circuit. The reference voltage circuit includes a diode to receive first and second currents having first and second respective current densities, where, the first and second current densities are different and determined by circuitry that precisely controls the respective amount of time the first and second currents flow into the diode. The reference voltage circuit also comprises circuitry to form a reference voltage by combining first and second voltages generated from respective voltages of the diode that result from the first and second currents flowing through the diode.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventor: Matthias Eberlein
  • Patent number: 10073495
    Abstract: Particular examples described herein provide for an electronic device, such as a notebook computer or laptop, which includes a circuit board coupled to a plurality of electronic components (which includes any type of hardware, elements, circuitry, etc.). The electronic device may also include a connector assembly that is positioned within at least a portion of a recess of the electronic device, where the connector assembly includes: a first assembly that is to receive a connector; and a second assembly that is to receive an identification module that is to provide an association between a user and the electronic device.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: Sameer Sharma, Douglas Satzger, Gadi Amit, Yoshikazu Hoshino, Chadwick Harber, Daniel Clifton, Philip J. Houdek, II, Stanislav Moiseyenko, Nathan Isaiah Jauvtis
  • Patent number: 10070816
    Abstract: Embodiments of the present disclosure provide techniques and configurations for an orthotic device. In one instance, the device may include an orthotic device body and at least two sensors spatially disposed inside the orthotic device body. A first sensor may provide a first output responsive to pressure resulting from application of mechanical force to the orthotic device body. A second sensor may provide a second output responsive to flexing resulting from the application of mechanical force to the orthotic device body. The device may also include a control unit communicatively coupled with the sensors to receive and process the outputs provided by the sensors in response to pressure and flexing. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: Nicholas P. Cowley, Ruchir Saraswat, Richard J. Goldman
  • Patent number: 10073659
    Abstract: A method is described. The method includes receiving an indication of an activity of load circuitry of a power supply. The method includes, in response to the indication, generating a first signal that describes the activity and a second signal that describes whether the event is initiating or completing. The method includes determining a weight amount from the first signal and adjusting a credit count by the weight amount up or down based on the second signal. The method includes comparing the credit count against a first threshold. The method includes calculating an average credit count that accounts for the credit count and previous credit counts and comparing the average credit count against a second threshold. The method includes adjusting an activity level of the load circuitry if either threshold is crossed.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: James Alexander, Muthukumar P. Swaminathan, Richard P. Mangold
  • Patent number: 10073695
    Abstract: A method of an aspect includes receiving a floating point round-off amount determination instruction. The instruction indicates a source of one or more floating point data elements, indicates a number of fraction bits after a radix point, and indicates a destination storage location. A result including one or more result floating point data elements is stored in the destination storage location in response to the floating point round-off amount determination instruction. Each of the one or more result floating point data elements includes a difference between a corresponding floating point data element of the source in a corresponding position, and a rounded version of the corresponding floating point data element of the source that has been rounded to the indicated number of the fraction bits. Other methods, apparatus, systems, and instructions are disclosed.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: Cristina S. Anderson, Bret L. Toll, Robert Valentine, Simon Rubanovich, Amit Gradstein
  • Patent number: 10073977
    Abstract: Technologies for authenticity assurance for I/O data include a computing device with a cryptographic engine and one or more I/O controllers. A metadata producer of the computing device performs an authenticated encryption operation on I/O data to generate encrypted I/O data and an authentication tag. The metadata producer stores the encrypted I/O data in a DMA buffer and the authentication tag in an authentication tag queue. A metadata consumer decrypts the encrypted I/O data from the DMA buffer and determines whether the encrypted I/O data is authentic using the authentication tag from the authentication tag queue. For input, the metadata producer may be embodied as the cryptographic engine and the metadata consumer may be embodied as a trusted software component. For output, the metadata producer may be embodied as the trusted software component and the metadata consumer may be embodied as the cryptographic engine. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: Pradeep M. Pappachan, Reshma Lal, Bin Xing, Steven B. McGowan, Siddhartha Chhabra, Reouven Elbaz
  • Patent number: 10073964
    Abstract: An input device of a secure authentication protocol system may receive at least one user authentication factor in a pre-boot session. The input device may verify the received authentication factors and may store the verified authentication factors. During a post-boot session, the input device may communicate the verified authentication factor and a stored post-boot session credential received during a prior post-boot session to an authentication engine executing in a trusted execution environment. The authentication engine verifies the received post-boot session credential is logically associated with an immediately preceding post-boot session. Upon successful verification of the received post-boot session credential, the verified authentication factors or data indicative of a successfully verified authentication factor received during the pre-boot session are used in the current post-boot session.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: Michael Raziel, Abhilasha Bhargav-Spantzel, Hormuzd M. Khosravi
  • Patent number: 10074034
    Abstract: Apparatuses, methods and storage medium associated with processing an image are disclosed herein. In embodiments, a method for processing one or more images may include generating a plurality of pairs of keypoint features for a pair of images. Each pair of keypoint features may include a keypoint feature from each image. Further, for each pair of keypoint features, corresponding adjoin features may be generated. Additionally, for each pair of keypoint features, whether the adjoin features are similar may be determined. Whether the pair of images have at least one similar object may also be determined, based at least in part on a result of the determination of similarity between the corresponding adjoin features. Other embodiments may be described and claimed.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: Tao Wang, Lianrui Fu, Qiang Li, Jianguo Li, Yurong Chen, Ya-ti Peng, Yimin Zhang, Anbang Yao
  • Patent number: 10073727
    Abstract: Memory corruption detection technologies are described. A method can include receiving, from the application, an allocation request for an allocation of one or more contiguous memory blocks of the memory for a memory object. The method can further include allocating, by a processor, the one or more contiguous memory blocks for the memory object in view of a size of the memory object requested. The method can further include writing, into a MCD table, a first memory corruption detection (MCD) unique identifier associated with the one or more contiguous memory blocks. The method can further include creating a pointer with a memory address of the memory object and a second MCD unique identifier associated with the memory object. The method can further include sending, to the application, the pointer.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: Tomer Stark, Ady Tal, Ron Gabor
  • Patent number: 10074072
    Abstract: Apparatus and method to facilitate determination of item locations are disclosed herein. One or more storage medium to store a plurality of initial tag to item holder mappings that define associations between select ones of a plurality of tags associated with items to select ones of a plurality of item holders that hold the items; one or more processors; and read rate and match modules to be executed by the one or more processors may be provided. The read rate module is to generate a current detection rate by one or more antennas for each tag identified in a plurality of filtered current tag to antenna mappings. The match module is to determine at least one item holder at which each respective tag identified in the plurality of filtered current tag to antenna mappings is most likely to be currently located to provide a location of the item.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: Michael Wu, Addicam V. Sanjay, Daniel Gutwein
  • Patent number: 10074162
    Abstract: Techniques are provided for spatially adaptive tone mapping with dynamic brightness control. A methodology implementing the techniques according to an embodiment includes converting luminance data, from a received HDR image, to a logarithm domain and decomposing the converted data into a base layer, and one or more detail layers. The method also includes adjusting the layers, through shifting and scaling of the base layer and scaling of the detail layers, to map the amplitude data into a selected range. The method further includes converting the adjusted layers from the logarithm domain to a linear domain and calculating a tone compression parameter based on statistics of the adjusted log domain base layer. The statistics are associated with brightness of the received image. The method further includes applying a global tone compression function, based on the tone compression parameter, to the converted linear domain base layer to generate compressed linear domain layers.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventor: Dragomir El Mezeni
  • Patent number: 10073986
    Abstract: Embodiments of apparatus, computer-implemented methods, systems, and computer-readable media are described herein for a virtual machine manager, wherein the virtual machine manager is configured to selectively employ different views with different permissions to map guest physical memory of a virtual machine of the apparatus to host physical memory of the apparatus, to regulate access to and protect different portions of an application of the virtual machine that resides in different portions of the physical memory. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: Harshawardhan Vipat, Ravi L. Sahita, Roshni Chatterjee, Madhukar Tallam
  • Patent number: 10074151
    Abstract: Described herein are technologies related to technologies to facilitate real-time computer vision applications, especially those with autonomous or semi-autonomous locomotive robots (e.g., drones or self-driving cars). More particularly, the technologies described herein facilitate, for example, real-time motion estimation using dense optical flow. The technologies accelerate dense optical flow (DOF) processing of images by using the parallel processing techniques of a single-instruction, multiple data (SIMD) computing system.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventor: Avigdor Eldar
  • Patent number: 10073775
    Abstract: An apparatus and method are described for a triggered prefetch operation. For example, one embodiment of a processor comprises: a first core comprising a first cache to store a first set of cache lines; a second core comprising a second cache to store a second set of cache lines; a cache management circuit to maintain coherency between one or more cache lines in the first cache and the second cache, the cache management circuit to allocate a lock on a first cache line to the first cache; a prefetch circuit comprising a prefetch request buffer to store a plurality of prefetch request entries including a first prefetch request entry associated with the first cache line, the prefetch circuit to cause the first cache line to be prefetched to the second cache in response to an invalidate command detected for the first cache line.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: Christopher B. Wilerkson, Ren Wang, Antoine Kaufmann, Anil Vasudevan, Robert G. Blankenship, Venkata Krishnan, Tsung-Yuan C. Tai
  • Patent number: 10073780
    Abstract: Systems and methods for tracking addresses stored in non-home locations in a cache. A method includes determining if an address that is to be stored in a cache is to be stored in a non-home location, determining if a directory has a location available for storing an identifier of the non-home location and if one or more locations of the directory are available for storing an identifier of the non-home location, storing an identifier of the non-home location in one of the one or more locations of the directory. The method further includes invalidating a non-home location in the cache that corresponds to one of the one or more locations of the directory, if none of the one or more locations of the directory are available for storing an identifier of the non-home location, and storing an identifier of the non-home location in the one of the one or more locations.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventor: Karthikeyan Avudaiyappan
  • Patent number: 10074205
    Abstract: Methods, apparatus, and systems to create, output, and use animation programs comprising keyframes, objects, object states, and programming elements. Objects, object states, and programming elements may be created through image analysis of image input. Animation programs may be output as videos, as non-linear interactive experiences, and/or may be used to control electronic actuators in articulated armatures.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: Glen J. Anderson, David I. Poisner, Ravishankar Iyer, Mark Francis, Michael E. Kounavis, Omesh Tickoo
  • Patent number: 10073719
    Abstract: In one embodiment, a processor includes an execution unit and at least one last branch record (LBR) register to store address information of a branch taken during program execution. This register may further store a transaction indicator to indicate whether the branch was taken during a transactional memory (TM) transaction. This register may further store an abort indicator to indicate whether the branch was caused by a transaction abort. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: Ravi Rajwar, Peter Lachner, Laura A. Knauth, Konrad K. Lai
  • Patent number: 10074213
    Abstract: An architecture for pixel shading, enables flexible control of shading rates and automatic shading reuse between triangles in tessellated primitives in some embodiments. The cost of pixel shading may then be decoupled from the geometric complexity. Wider use of tessellation and fine geometry may be made more feasible, even at very limited power budgets. Shading may be done over small local grids in parametric patch space, with reusing of shading for nearby samples. The decomposition of shaders into multiple parts is supported, which parts are shaded at different frequencies. Shading rates can be locally and adaptively controlled, in order to direct the computations to visually important areas and to provide performance scaling with a graceful degradation of quality. Another important benefit, in some embodiments, of shading in patch space is that it allows efficient rendering of distribution effects, which further closes the gap between real-time and offline rendering.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: Franz P. Clarberg, Tomas G. Akenine-Moller, Robert M. Toth, Carl J. Munkberg
  • Patent number: 10074003
    Abstract: This application is directed to dynamic control for data capture. A device may comprise a capture logic module to receive at least one of biometric data from a biometric sensing module, context data from a context sensing module or content data from a content sensing module. The capture logic module may determine if a capture scenario exists based on at least one of the biometric data and context data. The determination may be weighted based on an operational mode. If a capture scenario is determined to exist, the capture logic module may then determine whether to capture data based on at least the content data. Captured data may be stored in a capture database in the device (e.g., along with enhanced metadata based on at least one of the biometric data, the context data or the content data). The device may also comprise a feedback database including feedback data.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: Yan Xu, Maha El Choubassi, Joshua Ratcliff
  • Patent number: 10073742
    Abstract: Technologies for providing manageability redundancy for micro server and clustered System-on-a-Chip (SoC) deployments are presented. A configurable multi-processor apparatus may include multiple integrated circuit (IC) blocks where each IC block includes a task block to perform one or more assignable task functions and a management block to perform management functions with respect to the corresponding IC block. Each task block and each management block may include one or more instruction processors and corresponding memory. Each IC block may be controllable to perform a function of one or more other IC blocks. The IC blocks may communicate with each other via a management communication infrastructure that may include a communication path from each of the management blocks to each of the other management blocks. Via the management communication infrastructure, the management blocks may bridge communication paths between pairs of management blocks.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: Robert C. Swanson, Mariusz Oriol, Janusz Jurski, Piotr Sawicki, Robert W. Cone, William J. O'Sullivan, Mariusz Stepka, Babak Nikjou, Madhusudhan Rangarajan, Pawel Szymanski, Piotr Kwidzinski, Robert Bahnsen, Mallik Bulusu
  • Patent number: 10073779
    Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: Herbert H. Hum, Brinda Ganesh, James R. Vash, Ganesh Kumar, Leena K. Puthiyedath, Scott J. Erlanger, Eric J. Dehaemer, Adrian C. Moga, Michelle M. Sebot, Richard L. Carlson, David Bubien, Eric Delano
  • Patent number: 10074409
    Abstract: An integrated circuit may have configurable storage blocks. A configurable storage block may include a memory array, and arithmetic and control circuitry. The arithmetic and control circuitry may be used to determine whether to operate the configurable storage block in a first mode which may provide random access to the memory array or in a second mode which may provide access to the memory array in a predefined order. Thus, the configurable storage block may implement simple first-in first-out modules and shift registers in addition to implementing memory modules with random access. Arithmetic and control circuitry may include a multiplexer that determines whether the configurable storage block is implementing simple first-in first-out modules or shift registers. When the configurable storage block implements first-in first-out modules, an up-down counter may be activated to generate a count value received at the multiplexer.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: Simon Finn, Carl Ebeling
  • Patent number: 10073796
    Abstract: Method and apparatus for sending packets using optimized PIO write sequences without sfences. Sequences of Programmed Input/Output (PIO) write instructions to write packet data to a PIO send memory are received at a processor supporting out of order execution. The PIO write instructions are received in an original order and executed out of order, with each PIO write instruction writing a store unit of data to a store buffer or a store block of data to the store buffer. Logic is provided for the store buffer to detect when store blocks are filled, resulting in the data in those store blocks being drained via PCIe posted writes that are written to send blocks in the PIO send memory at addresses defined by the PIO write instructions. Logic is employed for detecting the fill size of packets and when a packet's send blocks have been filled, enabling the packet data to be eligible for egress.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: Mark Debbage, Yatin M. Mutha
  • Patent number: 10074591
    Abstract: Embodiments of the present disclosure provide techniques and configurations for providing a thermal interface to a PCB. In some embodiments, the system for providing a thermal interface to a PCB may include a heat sink couplable to a printed circuit board (PCB) via a thermal interface. The heat sink may include a base configured to accommodate a plurality of heat pipes. The system may further include a heater block couplable to the base with the plurality of heat pipes, to conduct heat generated by the heater block to the base via the plurality of heat pipes, to heat the thermal interface, and cause the thermal interface to spread substantially evenly between the heat sink and the PCB. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: Devdatta P. Kulkarni, Russell S. Aoki
  • Patent number: 10073781
    Abstract: Systems and methods for invalidating a way of a directory for non-home locations (DNHL) set that stores an identifier of a home location of an address is disclosed. As a part of a method, a request to store data in a location of a special cache that is being tracked by the way of the DNHL set is accessed, it is determined if an address stored in the location of the special cache is stored in a non-home location, a DNHL set is identified that tracks the location of the special cache if the address is not stored in a non-home location, and a set and way of the location of the special cache is compared with a set and way identifier stored in each way of the DNHL set. The way of the DNHL set that stores a matching set and way identifier is invalidated.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventor: Karthikeyan Avudaiyappan
  • Patent number: 10074718
    Abstract: Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three-dimensional group III-V material body with a channel region. A source and drain material region is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack is disposed in the trench and on the exposed portion of the channel region. The gate stack includes first and second dielectric layers and a gate electrode.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Marko Radosavljevic, Ravi Pillarisetty, Benjamin Chu-Kung, Niloy Mukherjee
  • Patent number: 10073808
    Abstract: Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: Zuoguo J. Wu, Mahesh Wagh, Debendra Das Sharma, Gerald S. Pasdast, Ananthan Ayyasamy, Xiaobei Li, Robert G. Blankenship, Robert J. Safranek
  • Patent number: 10074919
    Abstract: Embodiments of the present disclosure may relate to a printed circuit board (PCB) that includes a first outer layer and a second outer layer opposite the first outer layer. The PCB may further include a routing layer between the first outer layer and the second outer layer, and an interconnect positioned within the first outer layer and coupled with the routing layer. The interconnect may include a contact within an opening in the first outer layer, wherein the contact is within a plane defined by an outer surface of the first outer layer. The interconnect may further include a plated via directly coupled with the contact and the routing layer. Other embodiments may be described or claimed.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: September 11, 2018
    Assignee: INTEL CORPORATION
    Inventors: Zhen Zhou, Daqiao Du, Anne M. Sepic, Kai Xiao
  • Patent number: 10073807
    Abstract: A logic-based decoder recovers binary data from ternary Crosstalk-Harnessed Signaling (CHS) streams with lower part cost, complexity and power consumption than analog/digital converter (ADC)-based CHS decoders. The decoders use inverters, latches, gates, latching circuits, and one comparator per bit pair to carry out the decoding calculations to produce a reconstructed binary signal with very low crosstalk noise that is largely insensitive to routing density. System-on-chip, multi-chip package, printed circuit board, and wired network applications are discussed.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: Chaitanya Sreerama, Stephen H. Hall
  • Patent number: 10073703
    Abstract: In one embodiment, the present invention includes a method for generating a list of files accessed during an operating system (OS) boot process to profile the OS boot process, and optimizing the list of files to generate an optimized file list for use in future OS boot processes, where the optimizing is according to a first optimization technique if the files were accessed from a solid state medium and according to a second optimization technique if the files were accessed from a rotating medium. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventor: Adriaan Van De Ven
  • Patent number: 10074920
    Abstract: Embodiments of the present disclosure are directed to an interconnect cable including a edge finger connector, and associated configurations and methods. The edge finger connector may be disposed at a first end of the interconnect cable and may connect the interconnect cable to an edge finger included in or coupled to a package substrate. The package substrate may be included in a processor package assembly, and a processor may be mounted on the substrate. The interconnect cable may include one or more elongate conductors, with contacts directly coupled to respective conductors. A second connector may be disposed at a second end of the interconnect cable, and may couple the interconnect cable to a small form-factor pluggable (SFP) case that is configured to connect the interconnect cable to an SFP cable. Other embodiments may be described and claimed.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: September 11, 2018
    Assignee: INTEL CORPORATION
    Inventors: Donald T. Tran, Rajasekaran Swaminathan
  • Patent number: 10073715
    Abstract: A dynamic runtime scheduling system includes task manager circuitry capable of detecting a correspondence in at least a portion of the output arguments from one or more first tasks with at least a portion of the input arguments to one or more second tasks. Upon detecting the output arguments from the first task represents a superset of the second task input arguments, the task manager circuitry apportions the first task into a plurality of new subtasks. At least one of the new subtasks includes output arguments having a 1:1 correspondence to the second task input arguments. Upon detecting the output arguments from an first task represents a subset of the second task input arguments, the task manager circuitry may autonomously apportion the second task into a plurality of new subtasks. At least one of the new subtasks may include input arguments having a 1:1 correspondence to first task output arguments.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: Chunling Hu, Tatiana Shpeisman, Rajkishore Barik, Justin E. Gottschlich
  • Patent number: 10073809
    Abstract: Technologies for one-side remote memory access communication include multiple computing nodes in communication over a network. A receiver computing node receives a message from a sender node and extracts a segment identifier from the message. The receiver computing node determines, based on the segment identifier, a segment start address associated with a partitioned global address space (PGAS) segment of its local memory. The receiver computing node may index a segment table stored in the local memory or in a host fabric interface. The receiver computing node determines a local destination address within the PGAS segment based on the segment start address and an offset included in the message. The receiver computing node performs a remote memory access operation at the local destination address. The receiver computing node may perform those operations in hardware by the host fabric interface of the receiver computing node. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: James Dinan, Mario Flajslik
  • Patent number: 10073731
    Abstract: Apparatus, systems, and methods for error correction in memory are described. In one embodiment, a controller comprises logic to receive a read request from a host device for data stored in a memory, retrieve the data and an associated error correction codeword, send the data to a host device, apply an error correction routine to decode the error correction codeword retrieved with the data, and in response to an error in the error correction codeword, send a location of data associated with the error to the host device. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: Ravi H. Motwani, Kiran Pangal