Abstract: For example, a Digital Power Amplifier (PA) (DPA) may include a dual Level Shifter (LS) configured to generate a differential LS output based on a differential input signal including a negative input signal and a positive input signal. The dual LS may include a first LS to provide a first single-ended LS output including a first LS output based on a first input signal, which is based on the negative input signal; and a second LS to provide a second single-ended LS output including a second LS output based on a second input signal, which is based on the positive input signal. The DPA may include first PA circuitry to generate a first PA signal based on the first LS output, and second PA circuitry to generate a second PA signal based on the second LS output.

Abstract: An image processing unit performs scene-adaptive illumination balancing by computing a correction table for a pixel correction circuit based on low-resolution image statistics and a base correction table. Statistics generation logic generates the image statistics, optionally as a luminance grid having a lower spatial resolution than image data. In some examples, illumination balancing logic identifies darker and brighter illumination regions, selects an illumination boundary threshold using an aggregate gradient metric over thresholded adjacent cells, and generates a spatial correction map using a three-part function providing smooth transitions. The spatial correction map may be modified based on one or more of a detected object region, an adaptive correction strength, or a maximum enhancement limit. The spatial correction map is resized and combined with the base correction table.

Abstract: Techniques and mechanisms for sequestering addresses for translation with circuitry which is coupled to a memory management unit (MMU). In an embodiment, a filter unit identifies addresses which are each to be translated. The filter unit maintains a registry of filters to be used for determining whether a given address is to be sequestered, rather than provided to a translation lookaside buffer (TLB) pipeline of a MMU. A precedent address, which is in an address set that does not correspond to any currently enabled filter in the registry, is sent to the MMU for translation, and also results in the registration of a filter for the address set. A subsequent address, which is in the address set, is sequestered based on the filter. In another embodiment, a translation of the precedent address by the MMU results in the filter unit translating the sequestered addresses, and a deregistering of the filter.

Abstract: This disclosure describes systems, methods, and devices related to optimized frame protection. A device may negotiate control frame protection with a peer station. The device may establish a pairwise transient key security association (PTKSA) with the peer station. The device may receive a control frame from the peer station. The device may discard the control frame based on the control frame being included in a discard control frame list and after the PTKSA being established.

Abstract: Systems and methods are provided for latency-optimized artificial intelligence (AI) audio processing. A shared feature encoder converts a time-domain audio signal into feature-domain data for processing by multiple AI models in an audio processing pipeline. The multiple AI models generate feature masks, and mask-processed data is generated based on the feature masks. Each AI model may process the feature-domain data, previously generated mask-processed data, or both to generate a corresponding feature mask. A shared feature decoder converts mask-processed data into processed time-domain audio after processing by the multiple AI models. Expanded audio-frame information including time-domain data, feature-domain data, and feature-mask data may be transmitted between audio processing modules, such as endpoint effect modules, mode effect modules, and copier modules.

Abstract: Example electronic devices having inlets for airflow management and related systems and methods are disclosed. An example apparatus includes a housing; a blower having a blower inlet, the blower in the housing; and an inlet defined by a surface of the housing, the inlet having a first inlet portion defined by a first portion of the surface and a second inlet portion defined by a second portion of the surface, the second portion of the surface extending over a portion of the blower inlet.

Abstract: Embodiments of the present disclosure include multi-die packages incorporating shielding dies that cover packaged dies and inter-die connectivity signals. The shielding die is electrically conductively coupled to the packaged dies, and certain functionality of the packaged dies is to be disabled in response to the shielding die being tampered with or removed, preventing access to confidential or otherwise sensitive information by would-be attackers.

Abstract: Embodiments of a microelectronic assembly, including a first integrated circuit (IC) die having a surface and including a first substrate attached to first metallization stacks on either side of the first substrate along respective planar interfaces orthogonal to the surface; and a second IC die coupled to the first IC die on the surface, the second IC die comprising a second substrate attached to second metallization stacks on either side of the second substrate along respective planar interfaces orthogonal to the surface, wherein the first metallization stacks and the second metallization stacks include respective conductive traces orthogonal to the surface.

Abstract: In one embodiment, an integrated circuit device includes a substrate, an electronic integrated circuit (EIC), a photonics integrated circuit (PIC) electrically coupled to the EIC, and a glass block at least partially in a cavity defined by the substrate and at an end of the substrate. The glass block defines an optical path with one or more optical elements to direct light between the PIC and a fiber array unit (FAU) when attached to the glass block.

Abstract: For example, a non Access Point (AP) (non-AP) station (STA) may be configured to transmit a Request to Send (RTS) frame; and determine measurement information based on a measurement of a Clear to Send (CTS) frame received from an AP based on the RTS frame. For example, an AP may be configured to process an RTS frame received from a non-AP STA; and to transmit a CTS frame based on the RTS frame. For example, the AP may be configured to transmit the CTS frame using a beacon frame transmit power used by the AP for transmission of beacon frames.

Abstract: Methods and apparatus for pillar bending improvement by cut tiers pattern implementation. The method uses a cut tier pattern in a staircase region of a 3D memory structure to reduce pillar bending in a pillar array region. The pillar array region includes a plurality of memory tiers comprising wordline layers interposed between isolation layers, where a memory tier comprises a two-dimensional (2D) array of memory cells. A plurality of vertical structures comprising pillars pass through memory cells in the wordline layers and pass through the isolation layers. The staircase structure is disposed adjacent to the pillar array region and includes vertical wordline drivers coupled to the wordline layers. A cut tier pattern comprising vertical trenches is formed in the staircase structure toward a side of the staircase structure adjacent to the pillar array region. The cut tier pattern includes one or more breaks used for routing circuitry in the wordlines.

Abstract: Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. The perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers. Growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. The lattice-matched layers can be etched away, leaving the doped semiconductor layers as fins for a ribbon FET. A ferroelectric layer can be conformally grown on the fins, creating a high-quality ferroelectric layer above and below the fins. A gate can then be grown on the ferroelectric layer.

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for techniques for creating a wall within a forkFET transistor structure, where the wall is adjacent to a first stack of nanoribbons on a first side of the wall and a second stack of nanoribbons on a second side of the wall opposite the first side of the wall. In embodiments, the wall extends beyond the top of the first stack of nanoribbons and electrically isolates a first gate metal coupled with the first stack of nanoribbons and a second gate metal coupled with the second stack of nanoribbons from each other. Other embodiments may be described and/or claimed.

Abstract: Integrated circuit interconnect structure compatible with single damascene techniques and that includes a non-copper via comprising metal(s) of low resistivity that can be deposited at low temperature in a manner that also ensures good adhesion. Metal(s) suitable for the non-copper via may have BCC crystallinity that can advantageously template favorable crystallinity within a diffusion barrier of the upper-level interconnect feature, further reducing electrical resistance of an interconnect structure.

Abstract: An integrated circuit structure includes a device layer including a first set of devices and a second set of devices. An interconnect layer is above the device layer, where the interconnect layer includes one or more conductive interconnect features within dielectric material. In an example, a first ring structure including conductive material extends within the interconnect layer, and a second ring structure including conductive material extends within the interconnect layer. In an example, the second ring structure is non-overlapping with the first ring structure. In an example, the first ring structure is above the first set of devices of the device layer, and the second ring structure is above the second set of devices of the device layer.

Abstract: Methods, apparatus, systems, and articles of manufacture to reduce impedance discontinuities and crosstalk in integrated circuit packages are disclosed. A disclosed apparatus includes: a package substrate, and a ball grid array on a first surface of the package substrate. The ball grid array includes a first ball and a second ball adjacent the first ball. The ball grid array is to enable the package substrate to be electrically coupled to a circuit board. The apparatus further includes a metal interconnect within the package substrate. The metal interconnect is electrically coupled to the first ball. The metal interconnect includes an inductive loop that extends toward the second ball.

Abstract: Transistor cell architectures have three MO routing tracks within a single cell height. The cell architectures include at least one p-type transistor formed over a p-type diffusion region and at least one n-type transistor formed over an n-type diffusion region. Each diffusion region extends primarily in a particular direction, and the MO routing tracks extending in the same direction as the diffusion regions. One MO routing track may be formed over each of the diffusion regions, and a third MO routing track formed between the diffusion regions.

Abstract: An accelerator may include one or more data processing units that perform deep learning operations in neural networks. A data processing unit includes a memory and a compute engine. The memory may include memory banks and clock domain crossing (CDC) buffers. Each memory bank may have its own CDC buffer(s). The memory banks may be grouped into bank groups. The memory may also include a group selection module and bank selection modules, each of which is associated with a different bank group. The group selection module may select a bank group for a data transfer request from the compute engine. The bank selection module of the selected bank group may select a memory bank from the selected bank group and store the data transfer request in a CDC buffer of the selected memory bank. The data transfer request may be transmitted to the selected memory bank from the CDC buffer.

Abstract: An apparatus to facilitate compression of memory data is disclosed. The apparatus comprises one or more processors to receive uncompressed data, adapt a format of the uncompressed data to a compression format, perform a color transformation from a first color space to a second color space, perform a residual computation to generate residual data, compress the residual data via entropy encoding to generate compressed data and packing the compressed data.

Abstract: Embodiments herein relate to a sampling phase-locked loop (PLL) with a compensation circuit for reducing ripples due to the use of a fractional N divider. The compensation circuit includes a ripple amplifier and a ripple divider. The ripple amplifier receives an output voltage, Vmain, of a main sampling circuit of the PLL and amplifies its alternating current (AC) components. The amplified output voltage is provided to a ripple integrator which samples the minimum and maximum values to provide inputs to an operational amplifier (op amp). An output of the op amp is fed back to a digital-to-analog converter (DAC), which provides a corresponding compensation voltage, Vcomp. Vcomp is added to Vmain to provide a final output control voltage, Vctrl, to control a voltage-controlled oscillator (VCO) of the PLL.

Abstract: Apparatuses, capacitor structures, assemblies, and techniques related to package substrate embedded capacitors are described. A capacitor architecture includes a multi-layer capacitor structure at least partially within an opening extending through an insulative material layer of a package substrate or on a package substrate. The multi-layer capacitor structure includes at least two capacitor dielectric layers interleaved with a plurality of conductive layers such that the capacitor dielectric layers are at least partially within the opening and one of the conductive layers are on a sidewall of the opening.

Abstract: A system detects a powerdown event, such as a power loss event, and performs a flush of volatile memory to persistent memory during a powerdown sequence. The system includes an energy backup device to power the system during the powerdown sequence. The system is configurable with optional settings that configure the powerdown sequence specific to a type of the energy backup device.

Abstract: A processor may determine, based on a length of an input key, whether to compute a hash value based on the input key or cause an accelerator device coupled to the processor to compute the hash value based on the input key. The processor may cause a hash table lookup operation to be performed based on the hash value.

Abstract: Methods and apparatus for maintaining the cooling systems of distributed compute systems are disclosed. An example apparatus disclosed herein includes memory, machine readable instructions, and programmable circuitry to at least one of instantiate or execute the machine readable instructions to input operational data into a machine-learning model, the operational data including first information relating to a workload of a server and second information relating to an ambient condition of the server, compare a predicted cooling power requirement for a time period with a predicted cooling power availability for the time period, the predicted cooling power requirement based on an output of the machine-learning model, and generate a cooling plan based on the comparison, the cooling plan to define operation of at least one of the server or a cooling system used to cool the server during the time period.

Abstract: Embodiments detailed herein relate to matrix operations. In particular, the loading of a matrix (tile) from memory. For example, support for a loading instruction is described in the form of decode circuitry to decode an instruction having fields for an opcode, a destination matrix operand identifier, and source memory information, and execution circuitry to execute the decoded instruction to load groups of strided data elements from memory into configured rows of the identified destination matrix operand to memory.

Abstract: Embodiments described herein provide a technique enable a broadcast load from an L1 cache or shared local memory to register files associated with hardware threads of a graphics core. One embodiment provides a graphics processor comprising a cache memory and a graphics core coupled with the cache memory. The graphics core includes a plurality of hardware threads and memory access circuitry to facilitate access to memory by the plurality of hardware threads. The graphics core is configurable to process a plurality of load request from the plurality of hardware threads, detect duplicate load requests within the plurality of load requests, perform a single read from the cache memory in response to the duplicate load requests, and transmit data associated with the duplicate load requests to requesting hardware threads.

Abstract: A circuitry including a first winding coupled to a second winding; a first terminal coupled to a first end of the first winding; a second terminal coupled to a second end of the first winding, wherein there is an imbalance between the first terminal and the second terminal when a current flows through the first winding; and a third terminal coupled to the second winding, wherein a terminal position of the third terminal along the second winding mitigates the imbalance on the first winding.

Abstract: Various embodiments provide apparatuses, systems, and methods for a register file array with a plurality of sets of memory cells, wherein individual sets of memory cells of the plurality of sets of memory cells are coupled to a respective local bit line (LBL). A merge circuitry may include a multiplexer with inputs coupled to the respective LBLs, wherein the multiplexer is to couple a selected one of the LBLs to a LBL merge node. Read circuitry may be coupled to the LBL merge node to read data from a first memory cell via the selected LBL. In some embodiments, the LBL may be precharged to a supply voltage (e.g., Vcc) minus a threshold voltage, Vt, of the multiplexer transistor, as opposed to being precharged to Vcc as in prior techniques. Other embodiments may be described and claimed.

Abstract: For example, a wireless communication device may be configured to generate a Short Training Field (STF) according to a millimeter Wave (mmWave) Physical layer (PHY) Protocol Data Unit (PPDU) format. For example, the STF may include a plurality of repetitions of an STF structure. For example, the STF structure may include a plurality of repetitions of a short training Orthogonal Frequency Division Multiplexing (OFDM) symbol, which may include a training sequence over a plurality of OFDM tones. For example, the wireless communication device may be configured to transmit an mm Wave PPDU including the STF according to the mmWave PPDU format over an mmWave wireless communication channel in an mmWave frequency band.

Abstract: An integrated circuit includes a first device and a laterally adjacent second device. The first device includes a first body including semiconductor material extending from a first source region to a first drain region, and a first gate structure on the first body. The second device includes a second body including semiconductor material extending from a second source region to a second drain region, and a second gate structure on the second body. A gate cut including dielectric material is between and laterally separates the first gate structure and the second gate structure. The first body is separated laterally from the gate cut by a first distance, and the second body is separated laterally from the gate cut by a second distance. In an example, the first and second distances differ by at least 2 nanometers. In an example, the first and second devices are fin-based devices or gate-all-around devices.

Abstract: Integrated circuit structures having fin isolation regions recessed for gate contact are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires over a first sub-fin. A gate structure is over the vertical stack of horizontal nanowires and on the first sub-fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure but is on a second sub-fin. A dielectric gate cut plug is between the gate structure and the dielectric structure. A recess is in the dielectric structure and in the dielectric gate cut plug. A conductive structure is in the recess, the conductive structure in lateral contact with a gate electrode of the gate structure.

Abstract: Microelectronic integrated circuit package structures include a first die and a second die both coupled to a bridge structure at an interface. A first thermally conductive mold material is on a first side of the interface and surrounds the first die and the second die. A second mold material is on a second, opposing side of the interface and surrounds the bridge structure.

Abstract: Disclosed herein are microelectronic packages having thermally conductive layers and methods for manufacturing the same. The microelectronics packages may include a substrate and a plurality of dies connected to the substrate and/or each other to form a die stack. The dies may have a perimeter. A thermally conductive layer may be located in between the respective dies. The thermally conductive layers may extend past at least a portion of the perimeters, thereby providing enhanced cooling of the die stack.

Abstract: Embodiments disclosed herein include package substrates. In an embodiment, a package substrate comprises a core, a first layer on the core, where the first layer comprises a first plane, a second layer on the first layer, where the second layer comprises first traces and second traces arranged in an alternating pattern, a third layer on the second layer, where the third layer comprises third traces and fourth traces arranged in an alternating pattern, and a fourth layer over the third layer, where the fourth layer comprises a second plane.

Abstract: Methods, systems, apparatus, and articles of manufacture to cool integrated circuit packages having glass substrates are disclosed. An example glass core of an integrated circuit (IC) package disclosed herein includes a fluid inlet to receive a cooling fluid, a fluid outlet, and a channel to fluidly couple the fluid inlet to the fluid outlet, the cooling fluid to flow through the channel from the fluid inlet to the fluid outlet, the channel fluidly isolated from one or more vias extending between a first surface and a second surface of the glass core.

Abstract: A microelectronic assembly is provided, comprising: an interposer having a first face and a second face opposite to the first face; a package substrate coupled to the first face; an integrated circuit die coupled to the second face; and an edge ring in the interposer. The interposer comprises a core comprising a first dielectric material and a redistribution layer (RDL), the RDL being on the first face or the second face, the RDL comprising a second dielectric material different from the first dielectric material, and the edge ring comprises: a metal trace in contact with the second dielectric material, the metal trace being along a periphery of the interposer, and a plurality of metal vias through the RDL, the plurality of metal vias in contact with the metal trace.

Abstract: An integrated circuit (IC) module includes a photonic IC, an electrical IC, and a switchable waveguide device that, using a signal from the electrical IC, controls optical signals to or from the photonic IC. The switchable waveguide device may be formed by coupling metallization structures on both sides of, and either level with or below, a nonlinear optical material. The metallization structures may be in the photonic or electrical IC. The nonlinear optical material may be above the electrical IC in the photonic IC or on a glass substrate. The photonic and electrical ICs may be hybrid bonded or soldered together. The IC module may be coupled to a system substrate.

Abstract: Particular embodiments described herein provide for an electronic device that can be configured to include a chassis, where the chassis includes a first chassis portion and a second chassis portion, a flexible display supported by the chassis, and a hinge. The hinge includes a first chassis attachment housing coupled to the first chassis portion, a first chassis portion lift arm coupled to the first chassis attachment housing, a first hinge pivot coupled to the first chassis portion lift arm, a second chassis attachment housing coupled to the second chassis portion, a second chassis portion lift arm coupled to the second chassis attachment housing, and a second hinge pivot coupled to the second chassis portion lift arm.

Abstract: A graphics processor includes multiple levels of memory units, including a memory device and a cache device located near a graphics component. The graphics processor includes distributed compression/decompression, including a module between the cache device and the memory device. The module can perform compression of write data when the write data is moved from the cache device to the memory device, and perform decompression of read data when the read data is moved from the memory device to the cache device. The graphics processor can include a second level of cache with another compression module between the first level of cache and the second level of cache.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to allocate accelerator usage. An apparatus to allocate accelerator usage comprises: at least one memory, machine readable instructions, and processor circuitry to at least one of instantiate or execute the machine readable instructions to: store data identifying at least one processing unit in communication with a processing circuitry and at least one class; predict an execution of the at least one processing unit workload based on at least one capability; and schedule which processing unit the workload to run on based on at least one of (i) processor circuitry or (ii) user priority parameters.

Abstract: A machine-readable storage medium having program code that when processed by one or more processing cores causes a method to be performed. The method includes determining from program code that is scheduled for execution and/or is being scheduled for execution that an accelerator is expected to be invoked by the program code. The program code to implement one or more application software processes. The method also includes, in response to the determining, causing the accelerator to wake up from a sleep state before the accelerator is first invoked from the program code's execution.

Abstract: Systems, apparatus, and methods for measuring heart rate are disclosed. An example system includes a transmitter to emit electromagnetic waves; a first sensor to output signals representative of the electromagnetic waves reflected by a subject; a second sensor to generate image data, the image data including data corresponding to a chest of the subject; machine readable instructions; and processor circuitry to at least one of instantiate or execute the machine readable instructions to generate heartbeat data by cancelling harmonics associated with respiration by the subject from data corresponding to the output signals of the first sensor based on the image data, and determine a heart rate for the subject based on the heartbeat data.

Abstract: An apparatus to facilitate supporting and load balancing multiple double precision pipelines in a graphics environment is disclosed. The apparatus includes a processing core having at least one processing resource comprising: a first double precision (DP) pipeline to support double float operations, the first DP pipeline comprising a first set of floating point units (FPUs) configured in a pipelined configuration to enable new instructions to be issued to the first DP pipeline before previous instructions are complete; and a second DP pipeline to support the double float operations, wherein the second DP pipeline comprising a second set of FPUs configured in a pipelined configuration to enable new instructions to be issued to the first DP pipeline before previous instructions are complete.

Abstract: An apparatus to facilitate cross-thread register sharing for matrix multiplication compute is disclosed. The apparatus includes matrix acceleration hardware comprising a plurality of data processing units, wherein the respective plurality of data processing units are to: receive a decoded instruction for a first thread having a first register space, wherein the decoded instruction is for a matrix multiplication operation and comprises an indication to utilize a second register space of a second thread for an operand of the decoded instruction for the first thread; access the second register space of the second thread to obtain data for the operand of the decoded instruction; and perform the matrix multiplication operation for the first thread using the data for the operand from the second register space of the second thread.

Abstract: Magnetically actuated doors are disclosed. A disclosed example apparatus includes a door to be movably coupled to a frame of a computing device, a first magnet, a magnet array including a second magnet and a third magnet, the door to support the first magnet or the magnet array, and a slide. The slide includes a body supporting the other of the first magnet or the magnet array, and a guide, the body to move along a path defined by the guide, wherein the body in a first location of the path causes the magnet array to attract the first magnet and close the door relative to the frame, and wherein the body in a second location of the path causes the magnet array to repel the first magnet and open the door relative to the frame.

Abstract: An accelerator device may generate and submit descriptors to be processed by the accelerator device. Software executing on a processor may submit descriptors to the accelerator device to be processed in parallel.

Abstract: Technology herein provides a performance-enhanced memory device including a memory array including a local word line circuit and a plurality of local word lines coupled to the local word line circuit, a word line (WL) sense circuit coupled to an access node in the local word line circuit, the WL sense circuit to sense a voltage level in the local word line circuit while bypassing a disturbance to operation of the local word lines and to provide an output signal that indicates when the voltage level has reached a high voltage threshold value to enable a read operation. The technology also provides read logic coupled to the WL sense circuit, the read logic to receive the output signal from the WL sense circuit, and trigger a read operation for one or more cells in the memory array when the output signal indicates that the voltage level has reached the high voltage threshold value.

Abstract: Composite integrated circuit (IC) device processing, including selective removal of inorganic dielectric material. Inorganic dielectric material may be deposited, modified with laser exposure, and selectively removed. Laser exposure parameters may be adjusted using surface topography measurements. Inorganic dielectric material removal may reduce surface topography. Vias and trenches of varying size, shape, and depth may be concurrently formed without an etch-stop layer. A composite IC device may include an IC die, a conductive via, and a conductive line adjacent a compositionally homogenous inorganic dielectric material.

Abstract: Disclosed herein are microelectronics package architectures having self-aligned air gaps and methods of manufacturing the same. The microelectronics packages may include first and second substrates, first and second traces, and a photosensitive material. The first trace may be attached to the first substrate and comprise a first sidewall. The second trace may be attached to the first substrate and comprise a second sidewall. The second traced may be spaced a distance from the first trace with the second sidewall facing the first sidewall. First and second portions of the photosensitive material may be attached to the first and second sidewalls, respectively. The second substrate may be attached to the first and second traces. The first and second substrates and the first and second traces may form the air gap in between the first and second traces.

Abstract: Embodiments of the present disclosure are directed to a photonic integrated circuit (PIC) that includes a micro-ring modulator (MRM) that is coupled with termination circuitry to reduce the reflection coefficient of the MRM when the PIC is electrically coupled to a driver. In embodiments, the termination circuitry may include one or more passive elements. Other embodiments may be described and/or claimed.