Intel Patents

Intel Corporation designs and manufactures microprocessors and chipsets for computing and communications equipment manufacturers. Its products may be found in desktops, servers, tablets, smartphones and other devices.

Intel Patents by Type

  • Intel Patents Granted: Intel patents that have been granted by the United States Patent and Trademark Office (USPTO).
  • Intel Patent Applications: Intel patent applications that are pending before the United States Patent and Trademark Office (USPTO).
  • Patent number: 9980228
    Abstract: Embodiments of low-power wake-up packet generation are generally described herein. A wireless device modulates an LP-WUR (low-power wake-up radio) bit sequence with an LP-WUR pulse to obtain a plurality of modulated LP-WUR signals, each modulated LP-WUR signal having a 1× symbol duration. The wireless device multiplexes, in a time domain, an OFDMA (orthogonal frequency division multiple access) signal with a 4× symbol duration with four modulated LP-WUR signals, to generate a multiplexed signal. The wireless device encodes for transmission of the multiplexed signal to a peer device to wake up a WLAN (wireless local area network) radio of the peer device and to another device with an OFDMA signal.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventors: Juan Fang, Shahrnaz Azizi, Minyoung Park, Thomas J. Kenney
  • Patent number: 9980200
    Abstract: In one embodiment, a mobile communication system is provided comprising a base station, a relay station, and a mobile station, a determiner configured to determine the distance between the mobile station and the base station or between the mobile station and the relay station, a decider configured to decide whether data transmission between the base station and the mobile station is carried out in a first relaying mode or a second relaying mode based on the determined distance and a controller configured to control the mobile communication system based on the result of the decision by the decider.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: May 22, 2018
    Assignee: INTEL DEUTSCHLAND GMBH
    Inventors: Tommaso Balercia, Markus Dominik Mueck
  • Patent number: 9975241
    Abstract: This disclosure pertains to machine object determination based on human interaction. In general, a device such as a robot may be capable of interacting with a person (e.g., user) to select an object. The user may identify the target object for the device, which may determine whether the target object is known. If the device determines that target object is known, the device may confirm the target object to the user. If the device determines that the target object is not known, the device may then determine a group of characteristics for use in determining the object from potential target objects, and may select a characteristic that most substantially reduces a number of potential target objects. After the characteristic is determined, the device may formulate an inquiry to the user utilizing the characteristic. Characteristics may be selected until the device determines the target object and confirms it to the user.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventors: Gila Kamhi, Amit Moran, Kobi Nistel, David Chettrit
  • Patent number: 9980412
    Abstract: Apparatuses, systems and methods associated with flexible heat spreader design are disclosed herein. In embodiments, an electronic device may include a component, a heat dissipation member, and a flexible member. The heat dissipation member may be coupled to the component via a flexible portion of the electronic device, the component located on a first side of the flexible portion and the heat dissipation member located on a second side of the flexible portion. The flexible member may be thermally coupled to the component and the heat dissipation member, wherein the flexible member extends along the flexible portion from the first side to the second side and is to transfer heat from the component to the heat dissipation member. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventors: Bo Qiu, Xi Guo, James C. Raupp, Michael Ahrens, David Pidwerbecki, Steven J. Lofland, George H. Daskalakis, Stacy L. Yee, Mark MacDonald
  • Patent number: 9980105
    Abstract: A mobile communications device and a method for controlling a mobile communications device including a radio processing circuit and a baseband processing circuit adapted to interact with the radio processing circuit, the mobile communications device configured to: receive a page, obtain message identification information from the page, process the obtained message identification information, and control an ongoing network connection resulting from the processed message identification information.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: May 22, 2018
    Assignee: INTEL IP CORPORATION
    Inventors: Alok Saxena, Rishav Dev
  • Patent number: 9977663
    Abstract: Technologies for optimizing sparse matrix code include a target computing device having a processor and a field-programmable gate array (FPGA). A compiler identifies a performance-critical loop in a sparse matrix source code and generates optimized executable code, including processor code and FPGA code. The target computing device executes the optimized executable code, using the processor for the processor code and the FPGA for the FPGA code. The processor executes a first iteration of the loop, generates reusable optimization data in response to executing the first iteration, and stores the reusable optimization data in a shared memory. The FPGA accesses the optimization data in the shared memory, executes additional iterations of the loop, and optimizes the additional iterations of the loop based on the optimization data. The optimization data may include, for example, loop-invariant data, reordered data, or alternate data storage representations. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventors: Hongbo Rong, Gilles A. Pokam
  • Patent number: 9979566
    Abstract: Disclosed herein are high performance systems with low latency error correction as well as related devices and methods. In some embodiments, high performance systems may include: central processing units, adapter chips, and switch chips connected via channels, each chip including link level forward error correction and link level replay, where errors at or below a threshold level are corrected by forward error correction and remaining errors are corrected using replay. In some embodiments, high performance systems may include: central processing units, adapter chips, and switch chips connected via channels, each chip including link level forward error correction, link level replay, and a multiplexer for determining which error correction technique to use based on the number of errors and an error threshold level.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventors: Brent R. Rothermel, Todd M. Rimmer
  • Patent number: 9976265
    Abstract: Technologies for communicating roadway information includes a plurality of roadway markers configured to propagate communications amongst each other. To do so, each roadway marker is configured to transmit communications to one or more other roadway markers. The communications may include sensor data generated by a sensor of a roadway marker. One or more roadway markers may transmit the sensor data to a roadway controller. Additionally or alternatively, the communication may include an alert message. A roadway marker may include a local alert device and be configured to activate the alert device in response to receiving an alert message. Additionally, one or more roadway markers may communicate with a roadway controller, a roadway traffic device, and/or an in-vehicle computing system of a vehicle to propagate roadway marker sensor data and/or alert messages. The roadway controller may be configured to control the roadway traffic devices, roadway makers, and/or communicate with remote computing devices.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventors: Michael T. Moran, Charles Baron
  • Patent number: 9977075
    Abstract: Embodiments detailed herein include an apparatus that includes a reliability assessment engine (RAE) stored in non-volatile memory and processing circuitry to execute the RAE to: receive data of at least one physical condition from a plurality of intra-die variation monitoring circuits, apply the received data least one to at least one reliability physics model, and calculate at least one of an estimated amount of lifetime consumed and an estimated amount of lifetime remaining.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventors: Christopher F. Connor, Bruce Querbach, Gordon McFadden, Rahul Khanna
  • Patent number: 9977054
    Abstract: Etching for probe wire tip is described particularly well suited to microelectronic device test. In one example, wires of a probe head are covered with an encapsulation material, the wires being attached to a test probe head substrate, each of the wires having two ends, the first end being attached to the substrate and the second end being opposite the substrate, each wire having an outer coating around a core. The wires are etched to remove the outer coating at the second end of the wires. The encapsulation material is then removed.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventors: Todd P. Albertson, David M. Craig, David Shia, Joseph D. Stanford
  • Patent number: 9979640
    Abstract: Devices and techniques for reorder resilient transport are described herein. A device may store data packets in sequential positions of a flow queue in an order in which the data packets were received. The device may retrieve a first data packet from a first sequential position and a second data packet from a second sequential position that is next in sequence to the first sequential position in the flow queue. The device may store the first data packet and the second data packet in a buffer and refrain from providing the first data packet and the second data packet to upper layer circuitry if the packet order information for the first data packet and the second data packet indicate that the first data packet and the second data packet were received out of order. Other embodiments are also described.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventors: Anil Vasudevan, Parthasarathy Sarangam, Eric Mann, Daniel Cohn
  • Patent number: 9977618
    Abstract: An apparatus for pooling memory resources across multiple nodes is described herein. The apparatus includes a shared memory controller, wherein each node of the multiple nodes is connected to the shared memory controller. The apparatus also includes a pool of memory connected to the shared memory controller, wherein a portion of the pool of memory is allocated to each node of the multiple nodes.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventors: Debendra Das Sharma, Mohan J. Kumar, Balint Fleischer
  • Patent number: 9977478
    Abstract: Provided is a memory device, comprising a non-volatile memory, an energy store coupled to the non-volatile memory, and a power management module configurable to power up the non-volatile memory and provide read access to the non-volatile memory, in response to the energy store being charged to at least a first predetermined level. Provided also is a computational device that includes the memory device. Provided also is a method in which an energy store coupled to a non-volatile memory of a memory device is charged to at least a first predetermined level. The non-volatile memory is powered up and read access is provided to the non-volatile memory, in response to charging the energy store to at least the first predetermined level.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: May 22, 2018
    Assignee: INTEL CORPORATION
    Inventors: Andrew Morning-Smith, Adrian Mocanu, Zeljko Zupanc
  • Patent number: 9977682
    Abstract: Various configurations and methods for disabling system management mode (SMM) and verifying a disabled status of SMM in a computing system are disclosed. In various examples, SMM may be disabled through a hardware strap, soft-straps, or firmware functions, and the indication of the SMM disabled status may be included in a model specific register (MSR) value accessible to the central processing unit (CPU). Additionally, techniques for verifying whether SMM is disabled in hardware or firmware, preventing access of SMM functionality, and handling secure software operations are disclosed.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventors: Robert Swanson, Vincent J. Zimmer
  • Patent number: 9977477
    Abstract: In an embodiment, processor includes at least one logic circuit to generate information to be output from the processor; an input/output (IO) interface circuit coupled to the at least one logic circuit to receive and transmit the information; a voltage regulator to provide an operating voltage to the IO interface circuit; and a controller to control the voltage regulator to provide the operating voltage at an adjusted level from a nominal operating voltage based on a process variation of at least a portion of a die including the IO interface circuit. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventors: Sunil Kumar C. R., Aruna Kumar, Prakash K. Radhakrishnan
  • Patent number: 9977674
    Abstract: Disclosed are an apparatus, system, and method for implementing predicated instructions using micro-operations. A micro-code engine receives an instruction, decomposes the instruction, and generates a plurality of micro-operations to implement the instruction. Each of the decomposed micro-operations indicates a single destination register. For predicated instructions, the decomposed micro-operations include “conditional move” micro-operations to select between two potential output values. Except in the case that one of the potential output values is a constant, the decomposed micro-operations for a predicated instruction also include an append instruction that saves the incoming value of a destination register in a temporary variable. For at least one embodiment, the qualifying predicate for a predicated instruction is appended to the incoming value stored in the temporary register.
    Type: Grant
    Filed: October 14, 2003
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventors: Jeffrey P. Rupley, II, Edward A. Brekelbaum, Edward T. Grochowski, Bryan P. Black
  • Patent number: 9977482
    Abstract: An apparatus and method for managing a frequency of a computer processor. The apparatus includes a power control unit (PCU) to manage power in a computer processor. The PCU includes a data collection module to obtain transaction rate data from a plurality of communication ports in the computer processor and a frequency control logic module coupled to the data collection module, the frequency control logic to calculate a minimum processor interconnect frequency for the plurality of communication ports to handle traffic without significant added latency and to override the processor interconnect frequency to meet the calculated minimum processor interconnect frequency.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventors: Ankush Varma, Ian M. Steiner, Krishnakanth V. Sistla, Matthew M. Bace, Vivek Garg, Martin T. Rowland, Jeffrey S. Wilder
  • Patent number: 9980313
    Abstract: A mobile communications device is described including a wireless transceiver, a radio resource control (RRC) circuit connected to the transceiver, the RRC circuit including at least one timer configured to measure at least one mode trigger, a mode selector responsive to said timer, the mode selector configured to transition among a plurality of support modes, each of the support modes corresponding to at least one task, wherein each of the tasks is associated with a task frequency, a context detection circuit configured to detect at least one context information, a task frequency adaptation circuit configured to adjust at least one of said task frequency to an adjusted task frequency, responsive to the at least one context information.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: May 22, 2018
    Assignee: Intel IP Corporation
    Inventors: Tian Yan Pu, Christian Drewes
  • Patent number: 9978449
    Abstract: Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventor: Hernan A. Castro
  • Patent number: 9977950
    Abstract: Techniques are provided for facial recognition using decoy-based matching of facial image features. An example method may include comparing extracted facial features of an input image, provided for recognition, to facial features of each of one or more images in a gallery of known faces, to select a closest gallery image. The method may also include calculating a first distance between the input image and the selected gallery image. The method may further include comparing the facial features of the input image to facial features of each of one or more images in a set of decoy faces, to select a closest decoy image and calculating a second distance between the input image and the selected decoy image. The method may further include recognizing a match between the input image and the selected gallery image based on a comparison of the first distance and the second distance.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: May 22, 2018
    Assignee: INTEL CORPORATION
    Inventors: Hyungsoo Lee, Yeongjae Cheon, Sumin Lee, Minje Park
  • Patent number: 9978014
    Abstract: A processing device includes a processor core and a number of calculation modules that each is configurable to perform any one of operations for a convolutional neuron network system. A first set of the calculation modules are configured to perform convolution operations, a second set of the calculation modules are reconfigured to perform averaging operations, and a third set of the calculation modules are reconfigured to perform dot product operations.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventors: Marc Lupon, Enric Herrero Abellanas, Ayose Falcon, Fernando Latorre, Pedro Lopez, Frederico Pratas
  • Patent number: 9977743
    Abstract: A processing device includes a first counter having a first count value of a number of child pages among a plurality of child pages present in an enclave memory of a first virtual machine (VM). The plurality of child pages are associated with a parent page in the enclave memory. The processing device includes a second counter having a second count value of a number of child pages among the plurality of child pages not present in the enclave memory and being shared by a second VM, wherein the second VM is different from the first VM. A non-zero value of at least one of the first counter or the second counter prevents eviction of the parent page from the enclave memory.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventors: Rebekah M. Leslie-Hurd, Francis X. McKeen, Carlos V. Rozas, Somnath Chakrabarti, Asit Mallick
  • Patent number: 9978147
    Abstract: A method and apparatus for performing inbuilt calibration of camera system that performs three-dimensional measurements and depth reconstruction are described. In one embodiment, the method includes displaying, using a projector of a capture device, a fiducial projection pattern in response to calibration of the capture device. The method may also include capturing, with a camera of the capture, an image of the fiducial projection pattern. The method may also include determining calibration coefficient values indicative of relative physical relationships of one or more components of the depth camera system based on analysis of the captured image of the fiducial projection pattern.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: May 22, 2018
    Assignee: INTEL CORPORATION
    Inventors: Sundeep Raniwala, Bidhan P. Chaudhuri, Anders Grunnet-Jepsen
  • Patent number: 9977888
    Abstract: Systems and techniques for privacy protected input-output port control are described herein. In an example, an indication may be obtained that a protected port is disabled. A set of application attributes stored in a secure memory location may be compared to a set of attested application attributes to create a verification flag. At least one port attribute of the protected port may be obtained based on the verification flag. The protected port may be enabled using the at least one port attribute. Other examples, for controlling an input-output port using computer firmware and trusted execution techniques are further disclosed.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventors: Nitin V. Sarangdhar, Raul Gutierrez
  • Patent number: 9979181
    Abstract: Described is an apparatus which comprises a pass-gate; and a control unit to control gate terminal of the pass-gate according to first availability of first or second power supplies, the control unit including: a voltage detector to detect the second power supply; and a supply switching circuit to generate a local supply for controlling the gate terminal of the pass-gate according to an output of the voltage detector.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: May 22, 2018
    Assignee: INTEL CORPORATION
    Inventor: Chee Hong Aw
  • Patent number: 9977953
    Abstract: Systems and techniques for a sensor network for trick classification are described herein. A first data stream may be received from a first sensor array affixed to a first free-moving body of a sporting device. A second data stream may be received from a second sensor array affixed to a second free-moving body of the sporting device. A trick region of a predetermined length of the first data stream corresponding with an occurrence of a trick may be determined using data from the first data stream. The trick may be classified using a first set of data from the first data stream corresponding with the trick region and a second set of data from the second data stream. The second set of data may be obtained by aligning the trick region of the first data stream with the second data stream.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventors: Stephanie Moyerman, Tyler Fetters, James Brian Hall
  • Patent number: 9978533
    Abstract: An energy storage device includes a middle section (610) including a plurality of double-sided porous structures (500), each of which contain multiple channels (511) in two opposing surfaces (515, 525) thereof, an upper section (620) comprising a single-sided porous structure (621) containing multiple channels (622) in a surface (625) thereof, and a lower section (630) including a single-sided porous structure (631) containing multiple channels (632) in a surface (635) thereof.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventors: Donald S. Gardner, Tomm V. Aldridge, Charles W. Holzwarth, Cary L. Pint, Zhaohui Chen, Wei C. Jin, Yang Liu, John L. Gustafson
  • Patent number: 9978397
    Abstract: Embodiments include a wearable device, such as a head-worn device. The wearable device includes a first microphone to receive a first sound signal from a wearer of the wearable device; a second microphone to receive a second sound signal from the wearer of the wearable device; and a processor to process the first sound signals and the second sound signals to determine that the first and second sound signals originate from the wearer of the wearable device.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventors: Swarnendu Kar, Gauri Phatak, Saurin Shah
  • Patent number: 9978636
    Abstract: Isolated and bulk semiconductor devices formed on a same bulk substrate and methods to form such devices are described. For example, a semiconductor structure includes a first semiconductor device having a first semiconductor body disposed on a bulk substrate. The first semiconductor body has an uppermost surface with a first horizontal plane. The semiconductor structure also includes a second semiconductor device having a second semiconductor body disposed on an isolation pedestal. The isolation pedestal is disposed on the bulk substrate. The second semiconductor body has an uppermost surface with a second horizontal plane. The first and second horizontal planes are co-planar.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventors: Annalisa Cappellani, Kelin J. Kuhn, Rafael Rios, Harry Gomez
  • Patent number: 9979375
    Abstract: A communication matching network for multi-harmonic suppression includes a communication circuit configured to provide a signal. The communication matching network further includes a matching circuit configured to receive the signal from the communication circuit and suppress one or more harmonics of the received signal to generate a filtered signal, wherein the matching circuit includes a transformer comprising a first winding and a second winding, wherein the first winding includes a first inductance and the second winding includes a second inductance and wherein the matching network includes a harmonic trap including a third inductance such that the third inductance is located inside or within a physical layout of the first winding and/or the second winding. The communication matching network further includes a receiver circuit configured to receive the filtered signal from the matching circuit for further processing.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: May 22, 2018
    Assignee: Intel IP Corporation
    Inventors: Stephan Leuschner, Jose Pedro Diogo Faisca Moreira
  • Patent number: 9979009
    Abstract: A system and method for an energy storage device, such as a battery, having an electrode tab, an electrode, and a laser weld coupling the electrode tab to the electrode. The electronic storage device or battery may be installed in an electronic device. Fabrication of the energy storage device may involve placing an electrode tab adjacent a surface of a thin layer of the electrode, and laser welding the electrode tab to the thin layer.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventor: Prabhat Tiwari
  • Patent number: 9978432
    Abstract: Apparatus, systems, and methods for write operations in spin transfer torque (STT) memory are described. In one embodiment, a memory comprises at least one spin-transfer torque (STT) memory device, temperature sensor proximate the STT memory device and a controller comprising logic, at least partially including hardware logic, to monitor an output of the temperature sensor, implement a first write operation protocol when the output of the temperature sensor fails to exceed a threshold temperature, and implement a second write operation protocol when the output of the temperature sensor exceeds the threshold temperature. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventor: Helia Naeimi
  • Patent number: 9978722
    Abstract: Embodiments of the present disclosure describe integrated circuit (IC) package assemblies having one or more wires that extend beyond a topmost component in the IC package assembly, computing devices incorporating the IC package assemblies, methods for formation of the IC package assemblies, and associated configurations. An IC package assembly may include a substrate having a first side and a second side opposite the first side, an IC die having a first side and a second side opposite the first side, where the first side of the IC die faces the first side of the substrate, a wire electrically coupled with the IC die, where an end of the wire extends beyond a topmost component in the IC package assembly, and an overmold coupled with the topmost component. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventors: William T. Glennan, Frank D. Madrigal
  • Patent number: 9978447
    Abstract: Described is an apparatus and system for improving write margin in memory cells. In one embodiment, the apparatus comprises: a first circuit to provide a pulse signal with a width; and a second circuit to receive the pulse signal and to generate a power supply for the memory cell, wherein the second circuit to reduce a level of the power supply below a data retention voltage level of the memory cell for a time period corresponding to the width of the pulse signal. In one embodiment, the apparatus comprises a column of memory cells having a high supply node and a low supply node; and a charge sharing circuit positioned in the column of memory cells, the charge sharing circuit coupled to the high and low supply nodes, the charge sharing circuit operable to reduce direct-current (DC) power consumption.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventors: Yih Wang, Muhammad M. Khellah, Fatih Hamzaoglu
  • Patent number: 9979749
    Abstract: A method and apparatus for network security elements using endpoint resources. An embodiment of a method includes receiving a request for access to a network at an endpoint server. The method further includes detecting that the request for access to the network includes a request that is unauthorized. The request for access to the network is directed to a network security element.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: May 22, 2018
    Assignee: INTEL CORPORATION
    Inventors: Omer Ben-Shalom, Uri Blumenthal
  • Patent number: 9979538
    Abstract: A processor includes a decode unit to decode an SM3 two round state word update instruction. The instruction is to indicate one or more source packed data operands. The source packed data operand(s) are to have eight 32-bit state words Aj, Bj, Cj, Dj, Ej, Fj, Gj, and Hj that are to correspond to a round (j) of an SM3 hash algorithm. The source packed data operand(s) are also to have a set of messages sufficient to evaluate two rounds of the SM3 hash algorithm. An execution unit coupled with the decode unit is operable, in response to the instruction, to store one or more result packed data operands, in one or more destination storage locations. The result packed data operand(s) are to have at least four two-round updated 32-bit state words Aj+2, Bj+2, Ej+2, and Fj+2, which are to correspond to a round (j+2) of the SM3 hash algorithm.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Vlad Krasnov
  • Patent number: 9979771
    Abstract: An adaptive variable fidelity media provision system and method are provided herein.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventors: Amol Shukla, Aaron J. Colwell
  • Patent number: 9979668
    Abstract: A first packet-switched reservation request is received. Data associated with the first packet-switched reservation request is communicated through a first circuit-switched channel according to a best effort communication scheme. A second packet-switched reservation request is received. Data associated with the second packet-switched reservation request is communicated through a second circuit-switched channel according to a guaranteed throughput communication scheme.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventors: Gregory K. Chen, Mark A. Anders, Himanshu Kaul, Ram K. Krishnamurthy, Aaron T. Stillmaker
  • Patent number: 9980168
    Abstract: This application discusses apparatus and methods of saving power using a quadrature receiver by enabling a single string reception mode of the quadrature receiver. In an example, a receiver for receiving communication information can include an analog front end configured to receive a modulated, information-carrying radio frequency signal at a first frequency band and to provide a digital representation of the modulated, information-carrying radio frequency signal at a second frequency band, a digital front end configured to receive the digital representation at the second frequency and to provide the communication information, for example, to a baseband processor. In a first processing mode of the receiver, the analog front end can provide either one of in-phase symbol information of the modulated, information-carrying radio frequency signal or quadrature symbol information of the modulated, information-carrying radio frequency signal at the second frequency band.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventors: David Arditti Ilitzky, Thomas A. Tetzlaff, Edgar Borrayo, Stefano Pellerano
  • Patent number: 9980136
    Abstract: A technology that is operable to authenticate content access for dynamic adaptive streaming over hypertext transfer protocol (HTTP) (DASH) is disclosed. In one embodiment, a client device is configured with circuitry to communicate, to a content server, a request for a media presentation description (MPD). An MPD message is received from the content server indicating one or more content authorization elements to access content at the content server. A request for authorization of the client device to access content at the content server is communicated to an authorization server, when the client device is configured to perform the content authorization elements in the MPD message. An authorization message is received from the authorization server. A content request message requesting one or more DASH segments is communicated to the content server.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: May 22, 2018
    Assignee: INTEL IP CORPORATION
    Inventor: Ozgur Oyman
  • Patent number: 9980299
    Abstract: Technology for using an open mobile alliance (OMA) management object (MO) for congestion control in mobile networks is described. A novel type of OMA MO for application specific access control (ASAC) can include internet protocol (IP) flow descriptions that can be used to characterize applications with fine granularity. Priorities can be assigned to IP flows based on the IP flow descriptions. A user equipment (UE) can receive such an OMA MO and also receive application-barring information regarding a congestion level in a mobile network with which an application at the UE wishes to connect. The UE can have a connectivity manager (CM) that determines whether to allow the application to establish a connection with the mobile network based on the priority level of the application's associated IP flow and the application-barring information.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: May 22, 2018
    Assignee: Intel IP Corporation
    Inventors: Robert Zaus, Martin Kolde, Jerome Parron, Ana Lucia A. Pinheiro, Marta Martinez Tarradell, Hyung-Nam Choi, Vivek Gupta, Chen-Ho Chin, Richard C. Burbidge, Candy Yiu
  • Publication number: 20180139194
    Abstract: Generally, this disclosure provides systems, methods and computer readable media for secure sharing of user annotated subscription media content with trusted devices. The shared content may include user specified snapshots of the media along with user supplied annotations. The system may include a host processor configured to arrange a secure session with a server and to receive the subscription media content from the server in an encrypted format. The system may also include a trusted execution environment (TEE) comprising a secure processor and secure storage configured to decrypt and store the media content, based on a content encryption key obtained from the server. The system may further be configured to: receive a snapshot frame request and annotations from the user; generate a composite image of the snapshot and an overlay including the annotations; and encrypt the composite image for sharing with other users.
    Type: Application
    Filed: October 24, 2017
    Publication date: May 17, 2018
    Applicant: Intel Corporation
    Inventors: RAJESH POORNACHANDRAN, SAURABH DADU, NED M. SMITH
  • Publication number: 20180137074
    Abstract: Bridge logic is provided to receive a request from a device, where the request references an address of a secondary address space. The secondary address space corresponds to a subset of addresses in a configuration address space of a system, and the secondary address space corresponds to a first view of the configuration address space. The bridge logic uses a mapping table to translate the address into a corresponding address in the configuration address space, where addresses of the configuration address space correspond to a different second view of the configuration address space.
    Type: Application
    Filed: December 20, 2015
    Publication date: May 17, 2018
    Applicant: Intel Corporation
    Inventors: Prashant Sethi, Michael T. Klinglesmith, David J. Harrimann, Reuven Rozic
  • Publication number: 20180137669
    Abstract: Methods and apparatus relating to techniques for. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to determine a first line and a second line which define a chord to approximate a curve in two-dimensional (2D) space; and extend first line and the second line to a three-dimensional (3D) space using a line approximation between the 2D space and the 3D space. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: November 14, 2016
    Publication date: May 17, 2018
    Applicant: Intel Corporation
    Inventor: Kiran C. Veernapu
  • Publication number: 20180137383
    Abstract: Combinatorial shape regression is described as a technique for face alignment and facial landmark detection in images. As described stages of regression may be built for multiple ferns for a facial landmark detection system. In one example a regression is performed on a training set of images using face shapes, using facial component groups, and using individual face point pairs to learn shape increments for each respective image in the set of images. A fern is built based on this regression. Additional regressions are performed for building additional ferns. The ferns are then combined to build the facial landmark detection system.
    Type: Application
    Filed: June 26, 2015
    Publication date: May 17, 2018
    Applicant: Intel Corporation
    Inventors: Anbang YAO, Yurong CHEN
  • Publication number: 20180136971
    Abstract: Examples may include techniques for virtual machine (VM) migration. Examples may include selecting a VM for live migration from a source node to a destination node, predicting a time period associated with the live migration, and selecting another VM from which allocated source node bandwidth may borrowed to facilitate the live migration within the predicted time.
    Type: Application
    Filed: June 26, 2015
    Publication date: May 17, 2018
    Applicant: Intel Corporation
    Inventors: YAO ZU DONG, KUN TIAN
  • Publication number: 20180139015
    Abstract: One embodiment provides an apparatus. The example apparatus includes a root mean square (RMS) distortion determination module configured to determine an RMS distortion error and a signal to noise and distortion ratio (SNDR), the RMS distortion error determined based, at least in part, on a portion of a transmitted pulse centered at or near a transmitted pulse maximum amplitude and the SNDR determined based, at least in part, on the RMS distortion error.
    Type: Application
    Filed: November 21, 2017
    Publication date: May 17, 2018
    Applicant: Intel Corporation
    Inventors: Adee O. Ran, Kent C. Lusted
  • Publication number: 20180139027
    Abstract: A method and apparatus for acknowledge mode data (AMD) re-segmentation are disclosed. An AMD protocol data unit (PDU) is generated from at least one RLC SDU. The AMD PDU size is within a flexible maximum AMD PDU size. The original AMD PDU is stored in a retransmission buffer, and transmitted. If transmission of the original AMD PDU fails and the original AMD PDU size is larger than an updated maximum AMD PDU size, the original AMD PDU is segmented to segmented AMD PDUs. If transmission of one of the segmented AMD PDUs fails, the original AMD PDU may be re-segmented to smaller size AMD PDUs.
    Type: Application
    Filed: October 30, 2017
    Publication date: May 17, 2018
    Applicant: INTEL CORPORATION
    Inventors: Diana Pani, Christopher R. Cave, Stephen E. Terry, Paul Marinier
  • Publication number: 20180137668
    Abstract: Methods and apparatus relating to techniques for dynamically selecting optimum graphics logic frequency and/or graphics logic power gating configuration are described. In an embodiment, multi-rate control logic determines processor active slice count and processor frequency based at least in part on a target Frames Per Second (FPS) value and a current FPS value. The multi-rate control logic includes slow rate control logic to determine slice gating and operating frequency and a fast rate control logic to determine operating frequency of the processor. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: November 13, 2017
    Publication date: May 17, 2018
    Applicant: Intel Corporation
    Inventors: Pietro Mercati, Raid Ayoub, Michael Kishinevsky, Eric C. Samson, Marc Beuchat, Francesco Paterna
  • Patent number: D818649
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventor: Amruta Ranade