Abstract: A compiler may identify tensor operations in a deep learning model. For each tensor operation, the compiler may generate schedules arranged in a hierarchical structure. The compiler may select one or more schedules from the lowest level of the hierarchical structure by inputting the schedules at the lowest level and optionally other data into a trained model. The trained model may output a selection of one or more schedules. After selecting schedules for the tensor operations, the compiler may generate a graph including edges representing connections between the schedules. Each edge connects a schedule for a producing tensor operation to a schedule for a consuming tensor operation. The compiler may determine a weight for each edge and select a path based on the weights of the edges. The schedules along the path constitute a combined schedule to be used to transform loops of the deep learning model.

Abstract: Disclosed herein are examples of integrated circuit (IC) structures with engineered substrates that may mitigate problems that may be encountered when epitaxially growing III-N semiconductor materials, such as gallium nitride. Examples of engineered substrates for epitaxial growth of III-N semiconductor materials and III-N transistors include a thicker silicon substrate, a lattice-matched substrate, and a trap-rich silicon-on-insulator (SOI) substrate. In one example, an IC structure includes a lattice-matched and/or SOI substrate including a polycrystalline semiconductor material, an oxide layer over the polycrystalline semiconductor material, and a monocrystalline semiconductor material over the oxide layer. The IC structure may include a III-N semiconductor material over the monocrystalline silicon layer.

Abstract: Technologies for thermal management of the base die in high-bandwidth memory (HBM) die stacks are disclosed. In an illustrative embodiment, the interface logic region of the base die is a hot spot, as all of the high-speed signals into and out of the HBM die stack pass through the interface logic region. The memory dies stacked above the base die may not extend all the way across the HBM die stack, leaving space above the interface logic region of the base die. A stack of one or more heat transfer layers can be deposited on the base die above the interface logic region, removing heat and conducting it up to the top of the HBM die stack, where a heat sink or integrated heat spreader may be. The stack of one or more heat transfer layers may be any suitable material, such as silicon, dielectric packaging mold, etc.

Abstract: Accordingly, substrates for multi-die IC packages, and related assemblies, devices and methods, are disclosed herein. For example, in some embodiments, a substrate may include a dielectric material having a first surface and an opposing second surface, wherein the first surface includes a protruding portion; a conductive contact on the protruding portion of the first surface of the dielectric material; and a conductive pathway through the dielectric material and coupled to the conductive pathway. In some embodiments, the protruding portion of the first surface of the dielectric material has a thickness between 3 microns and 10 microns.

Abstract: Technologies for base die placement in high-bandwidth memory (HBM) systems are disclosed. In an illustrative embodiment, the base die or interface die for an HBM die stack may be positioned in the middle of the HBM die stack. Positioning the interface die in the middle can balance timings between various memory dies in the HBM die stack better than positioning the interface die at the bottom. The balanced timing can improve performance, allowing for higher bandwidth and/or more HBM memory dies in the stack. Through-silicon vias extend from the interface die, through one or more memory dies, and to microbumps at the bottom of the HBM die stack. In some embodiments, the interface die may be positioned closer to or at the top of the HBM die stack, closer to the heat sink. Such a placement may facilitate heat removal from the interface die.

Abstract: Disclosed herein are examples of integrated circuit (IC) structures fabricated using semiconductor/dielectric interface engineering techniques for III-N transistors. Semiconductor/dielectric interface engineering techniques for III-N transistors may include, for example, a thermal treatment, a chemical treatment, a plasma treatment, and/or introduction of an interlayer (e.g., between the III-N semiconductor material and the gate insulator material and/or between the polarization material and an insulator material). The resulting semiconductor/dielectric interface may in turn result in higher performance and/or higher gate dielectric reliability.

Abstract: A machine-readable medium having program code stored thereon which, when executed by one or more processors, causes the operations of: isolating a static resource associated with a graphics processor, the static resource to be utilized by a plurality of virtualized instances of the graphics processor; configuring, by a virtual machine monitor (VMM) or other trusted supervisory software, a shared memory partition corresponding to a physical function; uploading the static resource to the shared memory partition and configuring the shared memory partition as read-only with respect to the virtualized instances; mapping the shared region to each of a plurality of guest virtual machines (VMs); and wherein each guest VM is to locate and directly access the shared memory partition.

Abstract: This disclosure describes systems, methods, and devices for receiving network assisted multi-user multiple input multiple output (MU-MIMO) signaling. A user equipment (UE) device may decode a MU-MIMO set-up field in a radio resource control (RRC) message sent from a Next Generation NodeB device; determine, based on at least two bits in the MU-MIMO set-up field, that a MU-MIMO transmission is enabled; and determine, based on that least two bits, a modulation scheme for co-scheduled UE devices.

Abstract: Logic may determine, based on a PRS configuration, a frequency range of a PRS, wherein the PRS configuration defines resource blocks of frequency layers of the PRS. Logic may determine a number of frequency hops between frequency layers associated with the frequency range of the PRS during repetitions of one measurement gap based on a per UE measurement gap configuration or up to two measurement gaps based on a per frequency range (FR) measurement gap configuration, to perform measurements of the PRS within at least one measurement delay. Logic may perform the number of frequency hops and measurements of the PRS during each of the repetitions of the one measurement gap or the up to two measurement gaps. And logic may cause transmission of at least one positioning measurement report via the interface.

Abstract: Systems and methods are provided for context-aware, real-time speaker prioritization and enhancement. A speech encoder is provided that enables real-time prioritization of the speaker who is contextually most important rather than merely the loudest. The system uses a single-pass architecture and integrates comprehensive semantic analysis with acoustic speaker identification so that speaker focus is directed based on contextual importance rather than acoustic prominence. Comprehensive semantic analyses can include content-relevance assessment, vocabulary domain detection, identification of speaker roles, evaluation of dialogue context, and tracking of conversational continuity. The system simultaneously generates a transcript of the prioritized speech. A self-calibration loop monitors enhanced audio and transcript quality indicators and automatically adjusts fusion weights and enhancement parameters over time, enabling robust performance across changing acoustic conditions and conversation styles.

Abstract: Disclosed herein is a fabrication method that allows forming backside source and/or drain (S/D) contacts that are self-aligned to corresponding S/D regions of a transistor, and related integrated circuit (IC) structures and devices. In one aspect, a resulting IC structure may include a transistor and a nanoribbon comprising a semiconductor material. A channel portion of the transistor includes a portion of the semiconductor material of the nanoribbon and has a front side and a back side. A first conductive contact is at the front side of the channel portion and is in conductive contact with a first S/D region of the transistor. A second conductive contact is at the back side of the channel portion and is in conductive contact with a second S/D region of the transistor. Furthermore, the second conductive contact is self-aligned to the second S/D region of the transistor.

Abstract: AI-based workload scheduling across an iGPU and dGPU. For example, one embodiment of an apparatus comprises: graphics processing circuitry of an in-vehicle infotainment (IVI) system, the graphics processing circuitry including an integrated graphics processor (iGPU) and a discrete graphics processor (dGPU); a processor to execute program code from a memory to implement a graphics task scheduler, the graphics task scheduler to operate in accordance with a trained machine-learning (ML) model to: determine features associated with a next artificial intelligence (AI) or 3D graphics task to be executed by the graphics processing circuitry; determine metrics associated with a current state, the metrics to include: current power consumption conditions, current thermal conditions, and current resource utilization conditions; and select either the iGPU or the dGPU to execute the next AI or 3D graphics task based on at least one of: the features and the metrics associated with the current state.

Abstract: Techniques are provided herein to form an integrated circuit having different semiconductor devices with different backside epitaxial regions to improve the ohmic contact between the backside epitaxial regions and backside contact structures. FETs (field effect transistors) each includes semiconductor material extending in a first direction between source and drain regions. Different epitaxial grown material may be formed on the underside of the n-channel source or drain regions compared to the p-channel source or drain regions. Epitaxial growth on the underside of a p-channel source or drain region can include silicon germanium (SiGe) doped with both boron (B) and gallium (Ga) with a higher concentration of germanium (Ge) compared to the p-channel source or drain region. Additional epitaxial growth on the underside of a n-channel source or drain region can include silicon (Si) doped with a higher electrically active % of phosphorous (P) compared to the n-channel source or drain region.

Abstract: Disclosed herein are integrated circuit (IC) structures with nanoribbon transistors and C-clamp source and/or drain (S/D) contacts, and related methods and devices. In one aspect, an example IC structure may include a transistor having a channel portion in a nanoribbon, and a conductive contact to a region of the transistor, where the region is one of a source region or a drain region of the transistor and where, in a cross-sectional side view of the IC structure, the conductive contact has a C-shape.

Abstract: Disclosed herein are integrated circuit (IC) structures with convex interfaces at source/drain (S/D) contacts, and related methods and devices. In one aspect, an example IC structure includes a nanoribbon transistor including a S/D region and further includes a contact structure connected with the S/D region, where, in a cross-sectional side view of the IC structure, a shape of the S/D region at an interface with the contact structure is convex.

Abstract: Disclosed herein are IC structures with nanoribbon transistors and S/D contacts at opposite sides of nanoribbons, and related methods and devices. An example IC structure includes a nanoribbon; a transistor including a channel portion in a portion of the nanoribbon, a first S/D region, and a second S/D region; a first conductive contact in conductive contact with the first S/D region, the first conductive contact being at the front side of the channel portion; a second conductive contact in conductive contact with the second S/D region, the second conductive contact being at the back side of the channel portion; and an insulator structure in contact with the first S/D region, the insulator structure being at the back side of the channel portion, where, in a cross-sectional side view of the IC structure, a shape of the insulator structure at an interface with the first S/D region is convex.

Abstract: Methods, apparatus, and systems are disclosed for approximating numerical computations in deep neural networks. An example apparatus includes at least one memory, machine readable instructions, and programmable circuitry to at least one of instantiate or execute the machine readable instructions to generate a lookup table based on input elements, index the lookup table using tensor values, the tensor values associated with an output index, and output a vector in destination numeric format based on the lookup table, the vector including output values in a floating-point representation.

Abstract: Disclosed herein are embodiments of a waveguide structure, comprising: a deep rib waveguide on a slab and a plurality of shallow rib waveguides on the slab. The deep rib waveguide has a first etch-depth, the plurality of shallow rib waveguides has a second etch-depth, and the first etch-depth is greater than the second etch-depth.

Abstract: Embodiments herein relate to systems, apparatuses, techniques for an optical waveguide that includes a plurality of pillar structures that are in an optical path between the optical waveguide and a PIC. In embodiments, the plurality of pillar structures form an evanescent coupling structure that increases the alignment tolerance between the PIC and the optical waveguide. In embodiments, an end of each of the plurality of pillar structures may include a mass of material, such as gold, silver, or copper, that light from the PIC interacts with in a Plasmon effect to focus the light on to the optical waveguide. Other embodiments may be described and/or claimed.

Abstract: Examples described herein relate to a network interface device that includes circuitry and a memory. In some examples, the circuitry is to perform image construction operations, wherein the image construction operations comprise access to a base image of an application from the memory in the network interface device. In some examples, the circuitry is to provide a host server access to a constructed image bundle of the application.

Abstract: One embodiment provides for a graphics processor comprising a cache memory and a graphics core coupled with the cache memory. The graphics core includes circuitry configured to generate an approximate weight matrix including a set of one-hot coded weights, perform a forward compute pass with mini batch samples to compute a loss function, perform a backward compute pass to compute a gradient update via stochastic gradient descent according to a loss update, and update the approximate weight matrix based on the gradient update to generate an updated weight matrix.

Abstract: Techniques and mechanisms for efficiently saving and recovering state of a processor core. In an embodiment, a processor core fetches and decodes a first instruction to generate a first decoded instruction, wherein the first instruction comprises a first opcode which corresponds to one or more components of the processor core. Execution of the first instruction comprises saving microarchitectural state of the one or more components to a memory of the core. In another embodiment, a processor core fetches and decodes a second instruction to generate a second decoded instruction, wherein the second instruction comprises a second opcode which corresponds to the same one or more components. Execution of the second instruction comprises restoring the microarchitectural state from the memory to the one or more components.

Abstract: Examples described herein relate to offload service mesh management and selection of memory pool accessed by services associated with the service mesh to a switch. Based on telemetry data of one or more nodes and network traffic, one or more processes can be allocated to execute on the one or more nodes and a memory pool can be selected to store data generated by the one or more processes.

Abstract: Embodiments herein relate to a circuit which allows the re-use of an existing power supply units having main power rails and an auxiliary power rail, while supporting large memory configurations in a sleep state to avoid data loss. A processor determines whether a power requirement of memory modules in a computing device exceeds an available power of the auxiliary power rail. If this is the case, the processor asserts an override signal which is used by a logic circuit to force the power supply to remain on in the sleep state. A set of switches disconnect the main rails from other components which can be turned off in the sleep state. A select circuit selects one of the main rails to power the memory modules.

Abstract: A neural network, which can solve conic optimization problems may include a first layer, a second layer, and a third layer. The first layer includes first neurons encoding constraint coefficients of the conic optimization problem. The second layer includes second neurons encoding decision variables of the conic optimization problem. The third layer includes an integrator neuron. Data may be sent from a first neuron to a second neuron or from the second neuron to the first neuron. A neuron, after receiving data from another neuron, may update its internal state parameter based on the data and the weight of the connection between the two neurons. The communication may be triggered by the internal state parameter of the neuron sending the data meets a criterion. After the internal state parameter of the integrator neuron meets a criterion, the integrator neuron may output a solution to the conic optimization problem.

Abstract: Various embodiments herein may relate to system information blocks (SIBs) for augmented computing in cellular networks. In particular, some embodiments may be directed to system information associated with computing service support in cellular networks. Other embodiments may be disclosed or claimed.

Abstract: Embodiments provides for a package substrate, including: a core comprising insulative material; first conductive traces in contact with a surface of the core; and buildup layers in contact with the first conductive traces and the surface of the core, the buildup layers comprising second conductive traces in an organic dielectric material. The first conductive traces comprise at least a first metal and a second metal, the first conductive traces comprise a first region proximate to and in contact with the core and a second region distant from the core, parallel and opposite to the first region, a relative concentration of the first metal to the second metal is higher in the first region than in the second region, and the relative concentration of the first metal to the second metal between the first region and the second region varies non-uniformly.

Abstract: This disclosure describes systems, methods, and devices related to sensing authorization. A device may transmit a request for sensing services to a network, the request including one or more parameters related to sensing. The device may receive an authorization response from the network based on a UE's subscription status and privacy settings. The device may execute sensing functions locally on the UE upon receiving authorization from the network. The device may transmit sensing data to the network for exposure to authorized clients. The device may update a UE's privacy profile related to sensing data via a communication with a network function.

Abstract: Some embodiments are related to a fifth generation (5G) or sixth generation (6G) wireless communications system and network components to generate performance measurements for subscriber data and parameter provisioning in a unified data management system. Some embodiments are related to a wireless communications system and network components to generate data volume performance measurement for network functions supporting edge computing. Other embodiments are described and claimed.

Abstract: For example, a wireless communication station (STA) may be configured to set flow-group Quality of Service (QoS) information corresponding to a Medium Access Control (MAC) Service Data Unit (MSDU) in a traffic flow belonging to a flow group including a plurality of traffic flows. For example, the flow-group QoS information corresponding to the MSDU may include a flow identifier (ID) to identify the traffic flow, a flow group ID to identify the flow group, and MSDU set information corresponding to an MSDU set including the MSDU. For example, the STA may be configured to transmit a Physical Layer (PHY) Protocol Data Unit (PPDU) including the MSDU, wherein the PPDU includes the flow-group QoS information corresponding to the MSDU.

Abstract: Various embodiments herein provide techniques for uplink transport block transmission over multiple slots, e.g. using bit interleaving and/or rate matching. Other embodiments may be described and claimed.

Abstract: Integrated circuit interconnect structures including a metallization line with a bottom barrier material, and a metallization via lacking a bottom barrier material. Barrier material at a bottom of the metallization line may, along with barrier material on a sidewall of the metallization line, mitigate the diffusion or migration of fill metal from the line. An absence of barrier material at a bottom of the via may reduce via resistance and/or facilitate the use of a highly resistive barrier material that may enhance the scalability of interconnect structures. A number of masking materials and patterning techniques may be integrated into a dual damascene interconnect process to provide for both a barrier material and a low resistance via unburden by the barrier material.

Abstract: An integrated circuit structure includes a first layer comprising silicon and at least one of carbon, oxygen, or hydrogen, and a device layer including a plurality of transistors above the first layer. A first interconnect structure is above the device layer and includes first conductive interconnect features. A second interconnect structure is below the first layer and includes second conductive interconnect features. In an example, one or more of the second conductive interconnect features pass through a bottom surface of the first layer. One or more third conductive interconnect features vertically extend through the device layer to a top surface of the first layer. In an example, the one or more third conductive interconnect features are in contact with the corresponding one or more of the second conductive interconnect features that pass through the bottom surface of the first layer.

Abstract: A microelectronic assembly is provided, comprising: a first plurality of integrated circuit (IC) dies in a first layer; a second plurality of IC dies in a second layer; and a third plurality of IC dies in a third layer, in which: the second layer is between the first layer and the third layer, an interface between two adjacent layers comprises interconnects having a pitch of less than 10 micrometers between adjacent ones of the interconnects, and each of the first layer, the second layer, and the third layer comprises a dielectric material, and further comprises conductive traces in the dielectric material.

Abstract: Systems, apparatuses, and methods may provide for technology for forming a gate polysilicon for 3D-NAND complementary metal-oxide semiconductor under array (CuA) on a substrate with a barrier and spacer structure. For example, the technology includes forming a titanium nitride (TiN) barrier adjacent the gate polysilicon and forming a silicon nitride (SiN) spacer around the polysilicon gate and the titanium nitride barrier.

Abstract: Systems, apparatuses, methods, and computer-readable media are provided for user equipment (UE) trajectory-assisted handovers. In particular, some embodiments may include artificial intelligence (AI) or machine learning (ML) to predict UE location information. Other embodiments may be described and/or claimed.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for socket interconnect structures and related methods. An example socket interconnect apparatus includes a housing defining a plurality of first openings and a plurality of second openings and a ground structure coupled to the housing. The ground structure defines a plurality of third openings. The third openings of the ground structure align with the second openings of the housing when the ground structure is coupled to the housing. A plurality of ground pins are located in respective ones of the second openings and third openings. The ground structure is to electrically couple the ground pins. A plurality of signal pins are located in respective ones of the first openings of the housing. The signal pins are electrically isolated from the ground structure.

Abstract: A memory device with non-volatile memory and persistent predictive prefetching provides highspeed storage to a computer system. The memory device uses a non-volatile memory to store data and a volatile memory to cache the data from the non-volatile memory. The computer system sends access requests to obtain data in the non-volatile memory. A prediction engine in the memory device receives the access requests. The prediction engine compute access histories based on the access requests and stores them in an access history table. The prediction engine computes prediction of non-volatile memory addresses that will be accessed in the future based on the stored access history table. The prediction engine causes to store the data from the predicted addresses of the non-volatile memory in the volatile memory. The memory device stores the prediction in the non-volatile memory so the past predictions can be used after restarting the computer system.

Abstract: Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache memory that is coupled to the processing resources. The cache controller is configured to set an initial aging policy using an aging field based on age of cache lines within the cache memory and to determine whether a hint or an instruction to indicate a level of aging has been received.

Abstract: System and techniques to manage vehicles as part of a vehicle data center are described herein. Vehicle management may include the acquisition of a virtual instance definition for the vehicle data center, which outlines the parking spaces that make up the virtual instance and required hardware specifications. Upon detection of an incoming or present vehicle at the parking facility, the vehicle computing capabilities are evaluated. If these capabilities align with those by the virtual instance definition, the vehicle may be assigned to that virtual instance. If assigned, the vehicle is instructed to occupy a designated parking spot, as per the virtual instance definition, where the vehicle will contribute on-board hardware to perform tasks that are either currently running or scheduled to run on the vehicle data center virtual instance.

Abstract: Described are microelectronic devices including an embedded microelectronic package for use as an integrated voltage regulator with a microelectronic system. The microelectronic package can include a substrate and a magnetic foil. The substrate can define at least one layer having one or more of electrically conductive elements separated by a dielectric material. The magnetic foil can have ferromagnetic alloy ribbons and can be embedded within the substrate adjacent to the one or more of electrically conductive elements. The magnetic foil can be positioned to interface with and be spaced from the one or more of electrically conductive element.

Abstract: Various embodiments herein provide techniques related to a cellular network. Specifically, a cyber attack detection function (CDAF) of the cellular network may be configured to: identify operation state data from an analytics logical function (AnLF), wherein the operation state data corresponds to an analytics output of the AnLF; identify, based on the operation state data, a cyber-attack of at least one element of the cellular network; and transmit, based on the identification of the cyber-attack, a report that includes an indication of the cyber-attack. Other embodiments may be described and/or claimed.

Abstract: The present disclosure describes edge computing over disaggregated radio access network (RAN) infrastructure through dynamic edge data extraction. Edge data is extracted at intermediate stages of RAN processing, provided to edge compute functions, and inserted back into the RAN processing pipeline. These mechanisms allow for the processing of edge data traffic much closer to the data source than existing approaches, which decreases the overall latency and delay. Additionally, these mechanisms do not require changes to already existing network protocols, allowing for non-complex adoption and implementation.

Abstract: This disclosure describes systems, methods, and devices related to performance measurements. A device may decode a service request received from a management service consumer for the 5G system (5GS), wherein the service request may be associated with a performance measurement collection service to be delivered by the service producer to the service consumer related to a network exposure function (NEF). The device may detect performance measurements data received from the NEF. The device may decode from the performance measurements data a measurement label associated with the performance measurements data based on the service request. The device may encode a service response based on the performance measurements data received from the NEF.

Abstract: Bits are stored in an array with multiple capacitors per access transistor. An array of multiple ferroelectric capacitors shares a nanowire or nanosheet as a common plate and stores information accessed by a single common select transistor, which uses the nanowire or nanosheet for its channel. In an integrated circuit (IC) system, a group of bitlines is connected to a capacitor array by arrays of nanowires or nanosheets and wordline-controlled non-planar transistors. An IC die with a capacitor array accessed by a single select transistor and sharing a nanowire or nanosheet is coupled to a power supply and a cooling structure.

Abstract: Embodiments disclosed herein include integrated circuit structures and methods of forming such structures. In an embodiment, an integrated circuit structure comprises a dielectric layer with a first surface and a second surface, and an opening through the dielectric layer. In an embodiment, the opening is defined by sidewalls. In an embodiment, a graphene liner contacts the first surface of the dielectric layer and the sidewalls of the opening. In an embodiment, a conductive material at least partially fills a remainder of the opening.

Abstract: An IC device includes a multilayer metal line that is at least partially surrounded by one or more electrical insulators. The multilayer metal line may be formed by stacking four layers on top of one another. The four layers may include a first layer between a second layer and a third layer. The first layer may include Al. The second or third layer may include W. The fourth layer may be a conductive or dielectric layer. The second layer, third layer, and fourth layer can protect the first layer from defects in Al core layer during fabrication or operation of the multilayer metal line. Substrative etch may be performed on the stack of the four layers to form openings. An electrical insulator may be deposited into to the openings to form multiple metal lines that are separated by the electrical insulator. A via may be formed over the third layer.

Abstract: Embodiments of an integrated circuit (IC) package are disclosed. In some embodiments, the IC package includes a semiconductor die, a glass substrate, and a package substrate. The semiconductor die includes a micro light emitting diode (LED). The semiconductor die is at least partially embedded within the glass substrate and the glass substrate including a through glass via (TGV) embedded in the glass substrate wherein the TGV is electrically coupled to the semiconductor die to provide power to the micro LED. The package substrate that is coupled to the TGV.

Abstract: Embodiments of a power regulation circuit that ameliorates a first and second droop in a power source voltage that powers a processing core are disclosed. The power regulation circuit includes a first droop detector, a second droop detector and a frequency slowdown detection circuit. The first droop detector generates a first droop detection signal in a first detection state in response to detecting a first droop in the power source voltage. The second droop detector generates a second droop detection signal in a second detection state in response to detecting a second droop in the power source voltage. The frequency slowdown detection circuit to generate a frequency slowdown signal in a slowdown state in response to at least one of the first droop detection signal being in the first detection state and the second droop detection signal being in the second detection state.

Abstract: A memory device includes a group of ferroelectric capacitors with a shared plate that extends through the ferroelectric capacitors, has a greatest width between ferroelectric capacitors, and is coupled to an access transistor. The shared plate may be vertically between ferroelectric layers of the ferroelectric capacitors at the shared plate's greatest width. The memory device may include an integrated circuit die and be coupled to a power supply. Forming a group of ferroelectric capacitors includes forming an opening through an alternating stack of insulators and conductive plates, selectively forming ferroelectric material on the conductive plates rather than the insulators, and forming a shared plate in the opening over the ferroelectric material.