Intel Patents

Intel Corporation designs and manufactures microprocessors and chipsets for computing and communications equipment manufacturers. Its products may be found in desktops, servers, tablets, smartphones and other devices.

Intel Patents by Type

  • Intel Patents Granted: Intel patents that have been granted by the United States Patent and Trademark Office (USPTO).
  • Intel Patent Applications: Intel patent applications that are pending before the United States Patent and Trademark Office (USPTO).
  • Publication number: 20180332262
    Abstract: An optical micro-projection system comprising the following components: at least one laser light source (200, 400, 402, 600); at least one movable mirror (102, 103, 203) for deviating light from said light source to allow generation of images on a projection surface (104, 301, 303, 306, 603); a self mixing module for measurement of the distance (604) between the projection source and a projection surface, said self mixing module comprising: —at least one photodiode (401, 601) for monitoring the light emission power of the laser light source; —an optical power variation counter for counting optical power variations (605); successive displacements of said mirror allowing the self mixing module providing successive projection distance measurements of a plurality of points of said projection surface. A projection method for optical micro-projection system and a distance measurement method are also provided.
    Type: Application
    Filed: March 5, 2018
    Publication date: November 15, 2018
    Applicant: INTEL CORPORATION
    Inventors: LUCIO KILCHER, FAOUZI KHECHANA
  • Publication number: 20180332259
    Abstract: According to the present invention there is provided a method of reducing speckle in a primary light spot which is projected onto a surface by a projection device which comprises a laser, wherein a primary light spot is defined by two or more secondary light spots, the method comprising the steps of (a) consecutively providing the laser with “n” different input currents so that the laser consecutively outputs “n” different light beams, wherein each one of the “n” different light beams defines a secondary light spot on the surface, wherein “n” is an integer value greater than one; and (b) superposing the secondary light spots. There is further provided a corresponding method of projecting a pixel.
    Type: Application
    Filed: July 23, 2018
    Publication date: November 15, 2018
    Applicant: INTEL CORPORATION
    Inventors: Christophe Le Gros, Nicolas Abele
  • Publication number: 20180331472
    Abstract: A system board is provided that includes a connector. The connector includes a pinfield. The pinfield includes a set of differential signal conductors to correspond to pins of a set of differential signaling pairs; a set of one or more auxiliary signal conductors to carry auxiliary signals; and a plurality of thru-hole ground vias adjacent to a particular one of the auxiliary signal conductors in the set of auxiliary signal conductors.
    Type: Application
    Filed: July 23, 2018
    Publication date: November 15, 2018
    Applicant: Intel Corporation
    Inventor: Timothy D. Wig
  • Publication number: 20180331082
    Abstract: Techniques are disclosed for forming monolithic integrated circuit semiconductor structures that include a III-V portion implemented with III-N semiconductor materials, such as gallium nitride, indium nitride, aluminum nitride, and mixtures thereof. The disclosed semiconductor structures may further include a CMOS portion implemented with semiconductor materials selected from group IV of the periodic table, such as silicon, germanium, and/or silicon germanium (SiGe). The disclosed techniques can be used to form highly-efficient envelope tracking devices that include a voltage regulator and a radio frequency (RF) power amplifier that may both be located on the III-N portion of the semiconductor structure. Either of the CMOS or III-N portions can be native to the underlying substrate to some degree. The techniques can be used, for example, for system-on-chip integration of a III-N voltage regulator and RF power amplifier along with column IV CMOS devices on a single substrate.
    Type: Application
    Filed: December 21, 2015
    Publication date: November 15, 2018
    Applicant: INTEL CORPORATION
    Inventors: HAN WUI THEN, SANSAPTAK DASGUPTA, MARKO RADOSAVLJEVIC, SEUNG HOON SUNG, SANAZ GARDNER
  • Publication number: 20180331318
    Abstract: An electronic device may include an organic light emitting display (OLED), a heat generating device, and a heat spreading device.
    Type: Application
    Filed: December 10, 2015
    Publication date: November 15, 2018
    Applicant: INTEL CORPORATION
    Inventors: Praveen VISHAKANTAIAH, Zhiming J. ZHUANG, Hong W. WONG
  • Publication number: 20180331749
    Abstract: Apparatuses, computer readable media, and methods for uplink and downlink sounding for wireless networks are disclosed. An apparatus of a wireless device is disclosed. The apparatus comprising processing circuity configured to: encode a trigger frame for sounding (TF-S), the TF-S comprising an indication of whether a sounding is for uplink (UL) sounding or (DL) sounding, and the TF-S comprising an indication of stations to participate in the UL sounding or the DL sounding; and configure the wireless device to transmit the TF-S to the stations. The processing circuitry may be further configured to: if the sounding is for the DL sounding, encode a null data packet announcement (NDP-A), encode a null data packet (NDP), configure the wireless device to transmit the NDP-A, and configure the wireless device to transmit the NDP.
    Type: Application
    Filed: June 30, 2016
    Publication date: November 15, 2018
    Applicant: Intel IP Corporation
    Inventor: Chittabrata Ghosh
  • Publication number: 20180331182
    Abstract: Techniques are disclosed for forming self-aligned transistor structures including two-dimensional electron gas (2DEG) source/drain tip portions or tips. In some cases, the 2DEG source/drain tips utilize polarization doping to enable ultra-short transistor channel lengths of less than 20 nm, for example, and create highly conductive, thin source/drain tip portions in transistor devices. In some instances, the 2DEG source/drain tips can be formed by self-aligned regrowth of a polarization layer over a base III-V compound layer and on either side of a dummy gate, in locations to be substantially covered by spacers. In some cases, the III-V base layer may include gallium nitride (GaN) or indium gallium nitride (InGaN), for example, and the polarization layer may include aluminum indium nitride (AlInN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), or aluminum indium gallium nitride (AlInGaN), for example.
    Type: Application
    Filed: December 7, 2015
    Publication date: November 15, 2018
    Applicant: INTEL CORPORATION
    Inventors: HAN WUI THEN, SANSAPTAK DASGUPTA, MARKO RADOSAVLJEVIC, SANAZ K. GARDNER, SEUNG HOON SUNG
  • Publication number: 20180331900
    Abstract: An embodiment of a device manager apparatus may include a request processor to process a request for a reconfiguration of a reconfigurable device, a configuration controller communicatively coupled to the request processor to reconfigure the reconfigurable device based on the request, and a pseudo-device manager communicatively coupled to the request processor to create a pseudo device based on the request which corresponds to a functionality of the reconfiguration.
    Type: Application
    Filed: May 11, 2017
    Publication date: November 15, 2018
    Applicant: Intel Corporation
    Inventors: Utkarsh Y. Kakaiya, Joshua D. Fender, Joseph Grecco, Prashant Sethi, Nagabhushan Chitlur, Pratik M. Marolia, Henry M. Mitchel
  • Publication number: 20180331227
    Abstract: Substrates, assemblies, and techniques for enabling a p-channel oxide semiconductor. For example, some embodiments can include an oxide semiconductor, where the oxide semiconductor includes an indium gallium zinc oxide (IGZO) sulfur alloy as a semiconducting material. The semiconducting material can be included in a thin-film-transistor that includes one or more p-channels.
    Type: Application
    Filed: December 22, 2015
    Publication date: November 15, 2018
    Applicant: Intel Corporation
    Inventors: Khaled Ahmed, Prashant Majhi
  • Publication number: 20180331222
    Abstract: Techniques are disclosed for increasing the performance of III-N p-channel devices, such as GaN p-channel transistors. Increased performance is obtained by applying compressive strain to the GaN p-channel. Compressive strain is applied to the GaN p-channel by epitaxially growing a source/drain material on or in the GaN. The source/drain material has a larger lattice constant than does the GaN and puts the p-channel under compressive strain.
    Type: Application
    Filed: December 9, 2015
    Publication date: November 15, 2018
    Applicant: INTEL CORPORATION
    Inventors: SANSAPTAK DASGUPTA, MARKO RADOSAVLJEVIC, HAN WUI THEN
  • Publication number: 20180331156
    Abstract: Techniques are disclosed for forming a monolithic integrated circuit semiconductor structure that includes a radio frequency (RF) frontend portion and may further include a CMOS portion. The RF frontend portion includes componentry implemented with column III-N semiconductor materials such as gallium nitride (GaN), indium nitride (InN), aluminum nitride (AlN), and compounds thereof, and the CMOS portion includes CMOS logic componentry implemented with semiconductor materials selected from group IV of the periodic table, such as silicon, germanium, and/or silicon germanium (SiGe). Either of the CMOS or RF frontend portions can be native to the underlying substrate to some degree. The techniques can be used, for example, for system-on-chip integration of III-N transistors and/or RF filters, along with column IV CMOS devices on a single substrate.
    Type: Application
    Filed: December 21, 2015
    Publication date: November 15, 2018
    Applicant: INTEL CORPORATION
    Inventors: HAN WUI THEN, SANSAPTAK DASGUPTA, MARKO RADOSAVLJEVIC
  • Publication number: 20180329434
    Abstract: Various embodiments are generally directed to providing information capture by multiple drones, which may operate in a swarm, while maintaining rights and/or value assigned to the content authored by each drone or by subsets of drones. In general, the present disclosure provides that drones participating in content acquisition may attest to their authenticity to establish trust between drones in the swarm.
    Type: Application
    Filed: May 14, 2018
    Publication date: November 15, 2018
    Applicant: INTEL CORPORATION
    Inventors: Ned M. Smith, Rajesh Poornachandran
  • Publication number: 20180329650
    Abstract: Methods and apparatus related to fabric resiliency support for atomic writes of many store operations to remote nodes are described. In one embodiment, non-volatile memory stores data corresponding to a plurality of write operations. A first node includes logic to perform one or more operations (in response to the plurality of write operations) to cause storage of the data at a second node atomically. The plurality of write operations are atomically bound to a transaction and the data is written to the non-volatile memory in response to release of the transaction. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: March 31, 2016
    Publication date: November 15, 2018
    Applicant: Intel Corporation
    Inventors: Francesc Guim Bernat, Thomas Willhalm, Karthik Kumar, Martin P. Dimitrov, Raj K. Ramanujan
  • Publication number: 20180331070
    Abstract: Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.
    Type: Application
    Filed: December 26, 2015
    Publication date: November 15, 2018
    Applicant: Intel IP Corporation
    Inventors: Georg SEIDEMANN, Klaus REINGRUBER, Christian GEISSLER, Sven ALBERS, Andreas WOLTER, Marc DITTES, Richard PATTEN
  • Publication number: 20180329572
    Abstract: The present disclosure is directed to autonomous determination of global touch event coordinates on a system that includes at least two touchscreen devices configured to display a scene in a collage display mode. In the collage display mode the image in a first touchscreen device is apportioned between and displayed on a plurality of touchscreen devices. The collage display mode beneficially provides enhanced resolution, greater fluidity, and less disruption or discontinuities as objects and/or moving objects included in the scene transition between touchscreen devices while enabling full touchscreen functionality across the plurality of touchscreen devices including the image displayed in collage mode.
    Type: Application
    Filed: May 11, 2017
    Publication date: November 15, 2018
    Applicant: Intel Corporation
    Inventors: Meenakshi Gupta, James Edwards
  • Publication number: 20180329462
    Abstract: An apparatus including a hinge assembly is described herein. The hinge assembly including a plurality of substantially parallel hinges, each said hinge of the plurality being attached to at least one adjacent said hinge, wherein a first outermost hinge is coupled to a first housing and a second outermost hinge is coupled to a second housing, each said hinge of the plurality to provide a respective range of rotation to the hinge assembly such that the first and second housings may be rotated relative to each other about the hinge assembly within a range of approximately between 0 degrees and 360 degrees.
    Type: Application
    Filed: December 26, 2015
    Publication date: November 15, 2018
    Applicant: INTEL CORPORATION
    Inventors: Denica N. Larsen, Chunlin Bai, Prosenjit Ghosh
  • Publication number: 20180327887
    Abstract: Refractory metal alloy targets for reducing particles in physical vapor deposition processing and refractory metal-based layer for integrated circuit applications (for example, crystallization barrier layers in non-volatile memory devices) are disclosed herein. An exemplary method for reducing particles in a PVD chamber include positioning a refractory metal alloy target in the PVD chamber, positioning a substrate in the PVD chamber a distance from the refractory metal alloy target, and sputtering material from the refractory metal alloy target to form a refractory metal-based layer over the substrate. The refractory metal alloy target includes a refractory metal (for example, tungsten or molybdenum) alloyed with a body-centered cubic (BCC) metal (for example, niobium, tantalum, vanadium, or a combination thereof). The BCC metal has a Young's modulus lower than a Young's modulus of the refractory metal.
    Type: Application
    Filed: December 18, 2015
    Publication date: November 15, 2018
    Applicant: Intel Corporation
    Inventors: Christopher J. WIEGAND, Philip YASHAR, Anurag CHAUDHRY
  • Publication number: 20180329762
    Abstract: Methods and apparatus relating to event-driven framework for GPU (Graphics Processing Unit) programming are described. In an embodiment, event-driven logic receives a signal that indicates detection of an event by a device. Memory stores information corresponding to a kernel that is to be associated with the event. The event-driven logic causes a Graphics Processing Unit (GPU) to execute the kernel to process one or more operations in response to the event. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: December 25, 2015
    Publication date: November 15, 2018
    Applicant: Intel Corporation
    Inventors: Yuanyuan Li, Yuting Yang, Yong Jiang, Yao Wang
  • Publication number: 20180329713
    Abstract: Systems and methods may provide for a fitness sensor that is located and operates in a sensor hub. The fitness sensor may link to a Bluetooth link controller, a communications hub and numerous environmental and physical sensors in a platform that is conducive to low power utilization. Awakening a host processor only when valid content-oriented sensor data is available may assist to reduce a footprint of power consumption and time spent in computer processing fitness models.
    Type: Application
    Filed: December 10, 2014
    Publication date: November 15, 2018
    Applicant: Intel Corporation
    Inventors: Ke Han, Yong Hu, Ke Ding, Claire E. Jackoski, Ray Kacelenga, Lama Nachman
  • Publication number: 20180329612
    Abstract: An apparatus for interfacing is described herein. The apparatus includes logic, at least partially including hardware logic, to detect that a blow input received by the apparatus is from a human breath. A characteristic of the blow input is identified. An active application is determined to be running on the apparatus. The blow input is translated to an instruction based on the characteristic and the active application. The instruction is transmitted to the active application.
    Type: Application
    Filed: December 26, 2015
    Publication date: November 15, 2018
    Applicant: INTEL CORPORATION
    Inventors: Jiancheng Tao, Xiaoguo Liang, Hong W. Wong, Yanbing Sun, Wah Yiu Kwong
  • Publication number: 20180329729
    Abstract: A microservice infrastructure that securely maintains the currency of computing platform microservices implemented within a process virtual machine is provided. The computing platform microservices maintained by the infrastructure may include protected methods that provide and control access to components of the underlying computing environment. These components may include, for example, storage devices, peripherals, and network interfaces. By providing a software-defined microservice layer between these hardware components and workflows that specify high-level application logic, the embodiments disclosed herein have enhanced flexibility and scalability when compared to conventional technology.
    Type: Application
    Filed: May 9, 2017
    Publication date: November 15, 2018
    Applicant: INTEL CORPORATION
    Inventors: Mingqiu Sun, Noah Zentzis, Vincent J. Zimmer, Peggy J. Irelan, Timothy E. Abels, Gopinatth Selvaraje, Rajesh Poornachandran
  • Publication number: 20180329759
    Abstract: First and second circuits in an integrated circuit that generate local hot spots are activated at different times in order to reduce heat generation within each of the first and second circuits. The first and second circuits in the integrated circuit have the same circuit architecture. The first circuit processes data during a first time period, and heat generation is reduced in the second circuit during the first time period. A data path of the data is then switched from the first circuit to the second circuit. The second circuit then processes the data during a second time period after the first time period, and heat generation is reduced in the first circuit during the second time period. The data path of the data is then switched from the second circuit back to the first circuit. The first circuit then processes the data again.
    Type: Application
    Filed: May 11, 2017
    Publication date: November 15, 2018
    Applicant: Intel Corporation
    Inventors: David Mendel, Rajiv Kane
  • Publication number: 20180329724
    Abstract: A processor includes a core within a package and layers of programmable fabric within the same package as the core. The core includes logic to execute an instruction by loading a configuration file to one of the layers of programmable fabric. The configuration is to program an identified execution functionality. The execution functionality is to execute at least part of the instruction.
    Type: Application
    Filed: July 23, 2018
    Publication date: November 15, 2018
    Applicant: Intel Corporation
    Inventor: Leo A. Linsky
  • Publication number: 20180330778
    Abstract: An integrated circuit is provided that includes memory elements that exhibit immunity to soft error upset (SEU) events when subjected to high-energy atomic particle strikes. Each memory element may include at least two inverting circuits coupled in a feedback loop. Transistors in the memory element may be grouped in one contiguous region or divided into multiple separate regions. The memory element may include a long gate conductor that extends outside the boundary of the one contiguous region or the multiple separated regions. The long gate conductor may serve to provide parasitic resistance in the feedback loop to help mitigate SEU disturbances.
    Type: Application
    Filed: May 15, 2017
    Publication date: November 15, 2018
    Applicant: Intel Corporation
    Inventors: Weimin Zhang, Nelson Joseph Gaspard, Yanzhong Xu
  • Publication number: 20180331081
    Abstract: Methods and apparatus relating to integrating System in Package (SiP) with Input/Output (IO) board for platform miniaturization are described. In an embodiment, a SiP board includes a plurality of logic components. An IO board is coupled to the SiP board via a grid array. The plurality of logic components is provided on both sides of the SiP board and one or more of the plurality of logic components are to positioned in an opening in the IO board. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: December 21, 2015
    Publication date: November 15, 2018
    Applicant: Intel Corporation
    Inventors: Eng Huat Goh, Wee Hoe, Khang Choong Yong, Ping Ping Ooi
  • Publication number: 20180331004
    Abstract: A system in package and method of making as system in package are disclosed. The system in package has a substrate (102) with a plurality of passive devices (104) mounted thereon. A molding compound (106) envelopes the plurality of passive devices (104) to define a flat surface (116) substantially parallel to a surface of the substrate (102). A plurality of integrated circuit dies (110) is coupled successively to the flat surface (116).
    Type: Application
    Filed: December 16, 2015
    Publication date: November 15, 2018
    Applicant: Intel Corporation
    Inventors: Mao GUO, John G. MEYERS, Yong SHE, Bin LIU, Lingyan L. TAN
  • Publication number: 20180329737
    Abstract: A virtual machine migration controller may perform the live migration of a plurality of virtual machines from a first physical host system to a second physical host system. The virtual machine migration controller may determine a memory page dirty rate for each of a plurality of virtual machines. The virtual machine migration controller may additionally identify virtual machines that share memory pages and/or map to different memory pages having, at least in part, identical data or information. The virtual machine migration controller may group virtual machines demonstrating commonality among mapped memory pages. The virtual machine migration controller may determine a projected migration time based on the dirtying rate, the commonality of memory pages, and the available bandwidth. The virtual machine migration controller orders and transfers virtual machine groups based on the projected migration time.
    Type: Application
    Filed: December 18, 2015
    Publication date: November 15, 2018
    Applicant: Intel Corporation
    Inventors: Yao Zu Dong, Yuyang Du, Mingqiu Sun
  • Publication number: 20180331184
    Abstract: Techniques are disclosed for fabricating semiconductor transistor devices configured with a sub-fin insulation layer that reduces parasitic leakage (i.e., current leakage through a portion of an underlying substrate between a source region and a drain region associated with a transistor). The parasitic leakage is reduced by fabricating transistors with a sacrificial layer in a sub-fin region of the substrate below at least a channel region of the fin. During processing, the sacrificial layer in the sub-fin region is removed and replaced, either in whole or in part, with a dielectric material. The dielectric material increases the electrical resistivity of the substrate between corresponding source and drain portions of the fin, thus reducing parasitic leakage.
    Type: Application
    Filed: December 24, 2015
    Publication date: November 15, 2018
    Applicant: INTEL CORPORATION
    Inventors: GLENN A. GLASS, KARTHIK JAMBUNATHAN, ANAND S. MURTHY, CHANDRA S. MOHAPATRA, SEIYON KIM, JUN SUNG KANG
  • Patent number: 10127058
    Abstract: Apparatuses, methods and storage medium associated with content consumption are disclosed herein. In embodiments, an apparatus may include a decoder, a user interface engine, and a presentation engine. The decoder may be configured to receive and decode a streaming of the content. The user interface engine may be configured to receive user commands. The presentation engine may be configured to present the content as the content is decoded from the stream, in response to received user commands. Further, the decoder, the user interface engine, the presentation engine, and/or combination/sub-combination thereof, may be arranged to adapt the presentation to enhance user experience during response to a skip back command, where the adaption is in addition to a nominal response to the skip back command, e.g., display of closed captions. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: November 13, 2018
    Assignee: INTEL CORPORATION
    Inventor: Johannes P. Schmidt
  • Patent number: 10126950
    Abstract: Methods and apparatus to allocating and/or configuring persistent memory are described. In an embodiment, memory controller logic configures non-volatile memory into a plurality of partitions at least in part based on one or more attributes. One or more volumes (visible to an application or operating system) are formed from one or more of the plurality of partitions. Each of the one or more volumes includes one or more of the plurality of partitions having at least one similar attribute from the one or more attributes. In another embodiment, memory controller logic configures a Non-Volatile Memory (NVM) Dual Inline Memory Module (DIMM) into a persistent region and a volatile region. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: November 13, 2018
    Assignee: Intel Corporation
    Inventors: Scott W. Kirvan, Andy M. Rudoff, Mahesh S. Natu, Murugasamy K. Nachimuthu
  • Patent number: 10124764
    Abstract: Various systems and methods for intrusion detection are described herein. An electronic device for intrusion detection includes memory circuitry to store a set of signature voltage ratios and a corresponding set of node identifiers, each node identifier corresponding to a unique signature voltage ratio; and security circuitry to: compare voltages received at a first and second measuring point on a bus, the voltages resulting from a message transmitted by a sending node on the bus, the first measuring point providing a first voltage and the second measuring point providing a second voltage; calculate a test voltage ratio from the first voltage and the second voltage; determine whether the test voltage ratio is in the set of signature voltage ratios; and initiate a security response based on whether the test voltage ratio is in the set of signature voltage ratios.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: November 13, 2018
    Assignee: Intel Corporation
    Inventors: Shabbir Ahmed, Marcio Rogerio Juliato, Li Zhao, Manoj R. Sastry
  • Patent number: 10125013
    Abstract: Apparatuses, systems, and methods associated with placement of magnets within a microelectromechanical system device are disclosed herein. In embodiments, a method of affixing at least one magnet in a microelectromechanical system, may include affixing an electromagnetic actuator to a base structure of the microelectromechanical system, the affixing including affixing the electromagnetic actuator within a recess formed in the base structure. The method may further include placing a magnet within the recess, wherein the recess includes at least a portion of a spring, the spring affixed to the base structure and extending into the recess, the placing including placing the magnet on a side of the electromagnetic actuator, between the spring and the side of the electromagnetic actuator, the spring pressing the magnet against the side of the electromagnetic actuator and maintaining a position of the magnet in response to the placing the magnet within the recess.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: November 13, 2018
    Assignee: Intel Corporation
    Inventors: Robert Starkston, Amanuel M. Abebaw, Liwei Wang, Mark Saltas, Sandeep S. Iyer, Nick Labanok
  • Patent number: 10127991
    Abstract: A method is described. The method includes, within a semiconductor memory device comprising a three dimensional storage cell array, pumping a voltage and detecting a level of the pumped voltage. The method also includes causing a voltage level of an access control signal that is applied to the three dimensional storage cell array and whose voltage is derived from the pumped voltage to change in response to the detecting of the level of the pumped voltage. An apparatus is also described. The apparatus includes a semiconductor memory device comprising a three dimensional storage cell array. The semiconductor memory device includes a voltage pumping circuit to produce a pumped voltage, a waveform shaping circuit and a controller circuit.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: November 13, 2018
    Assignee: Intel Corporation
    Inventor: Toru Tanzawa
  • Patent number: 10127887
    Abstract: Techniques related to accelerating color conversion are discussed. Such techniques may include generating a converted color value based on an array of ordered coefficients associated with a subsection of a section of a color conversion space and input color channel value offsets within the section of the color conversion space.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: November 13, 2018
    Assignee: Intel Corporation
    Inventors: Stewart N. Taylor, Yuenian Yang, Ryan Metcalfe
  • Patent number: 10127406
    Abstract: Various embodiments are generally directed to the provision re-provision of encryption keys to access encrypted media. Encryption keys may be provisioned and re-provisioned to components, such as, processor elements, of a system based on power state transitions of the components. An encryption key may be provisioned to a component and then re-provisioned to the component before or after the component transitions from an active power state to another power state and back to the active power state.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: November 13, 2018
    Assignee: INTEL CORPORATION
    Inventors: Rajesh Poornachandran, Ned M. Smith
  • Patent number: 10127101
    Abstract: An error check and scrub (ECS) mode enables a memory device to perform error checking and correction (ECC) and count errors. An associated memory controller triggers the ECS mode with a trigger sent to the memory device. The memory device includes multiple addressable memory locations, which can be organized in segments such as wordlines. The memory locations store data and have associated ECC information. In the ECS mode, the memory device reads one or more memory locations and performs ECC for the one or more memory locations based on the ECC information. The memory device counts error information including a segment count indicating a number of segments having at least a threshold number of errors, and a maximum count indicating a maximum number of errors in any segment.
    Type: Grant
    Filed: December 26, 2015
    Date of Patent: November 13, 2018
    Assignee: Intel Corporation
    Inventors: John B Halbert, Kuljit S Bains
  • Patent number: 10127039
    Abstract: A processor saves micro-architectural contexts to increase the efficiency of code execution and power management. A save instruction is executed to store a micro-architectural state and an architectural state of a processor in a common buffer of a memory upon a context switch that suspends the execution of a process. The micro-architectural state contains performance data resulting from the execution of the process. A restore instruction is executed to retrieve the micro-architectural state and the architectural state from the common buffer upon a resumed execution of the process. Power management hardware then uses the micro-architectural state as an intermediate starting point for the resumed execution.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: November 13, 2018
    Assignee: Intel Corporation
    Inventors: Efraim Rotem, Eliezer Weissmann, Michael Mishaeli, Boris Ginzburg, Alon Naveh
  • Patent number: 10127072
    Abstract: The present disclosure is directed to enhanced virtual function capabilities in a virtualized network environment. In general, devices may comprise physical and virtualized resources. The physical resources may comprise at least a network adaptor that may handle incoming data from a network and outgoing data to the network. The virtualized resources may comprise at least one virtual machine (VM) and a corresponding interface. The corresponding interface may be one of a physical interface, a virtual interface or a “super” virtual interface. The physical interface may provide a first set of capabilities allowing the VM to access (e.g., control) at least the network adaptor. The virtual interface may provide a second set of capabilities that is a subset of the first set. The super virtual interface may provide a third set of capabilities including the second set of capabilities and at least one additional capability from the first set of capabilities.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: November 13, 2018
    Assignee: Intel Corporation
    Inventors: Stephen T. Palermo, Scott P. Dubal, Trevor Cooper, Anjali S. Jain, Iosif Gasparakis, Jr-Shian Tsai, Mike Bursell, Pradeepsunder Ganesh, Parthasarathy Sarangam, Jesse C. Brandeburg
  • Patent number: 10127012
    Abstract: An apparatus for managing input/output (I/O) data may include a streaming I/O controller to receive data from a load/store domain component and output the data as first streaming data of a first data type comprising a first data movement type and first data format type. The apparatus may also include at least one accelerator coupled to the streaming I/O controller to receive the first streaming data, transform the first streaming data to second streaming data having a second data type different than the first data type, and output the second streaming data. In addition, the apparatus may include a streaming interconnect to conduct the second data to a peer device configured to receive data of the second data type.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: November 13, 2018
    Assignee: INTEL CORPORATION
    Inventors: John Howard, Steven B. McGowan, Krzysztof Perycz
  • Patent number: 10127187
    Abstract: A system and method is described for simplifying implementation of repeater (e.g., re-driver/re-timer) module implementation in high-data-rate interconnects that carry a relatively low-data-rate clock signal as well as the data stream (e.g., PCIe). At the endpoint, any information critical to the function of the repeater (e.g., the most recent data rate negotiated by a pair of endpoints communicating through the repeater) is embedded in the clock signal by pulse-width modulation as ordered sets. The repeater only needs to read the clock-embedded information rather than decoding the data stream. Thus repeaters for such applications reconstruct the high-rate data-stream while actually decoding only the low-rate clock signal. Because the clock-signal protocol is independent of the data-stream protocol, the repeater's operation is protocol-agnostic with respect to the data-stream.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: November 13, 2018
    Assignee: INTEL CORPORATION
    Inventors: Huimin Chen, Duane G. Quiet
  • Patent number: 10126775
    Abstract: A method and apparatus for performing current control for an integrated circuit are described. In one embodiment the apparatus comprises core logic coupled to receive a first current; a clock generator to generate a first clock signal; and a closed loop current controller coupled to the clock generator and coupled to provide a second clock signal to the core logic based on the first clock signal, the current controller to control an amount of the first current received by the core logic by changing the first clock signal to generate the second clock signal.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: November 13, 2018
    Assignee: INTEL CORPORATION
    Inventors: Alexander Gendler, Kosta Luria, Arye Albahari, Ohad Nachshon
  • Patent number: 10126985
    Abstract: A processor includes a processing core to generate a memory request for an application data in an application. The processor also includes a virtual page group memory management (VPGMM) unit coupled to the processing core to specify a caching priority (CP) to the application data for the application. The caching priority identifies importance of the application data in a cache.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: November 13, 2018
    Assignee: Intel Corporation
    Inventors: Subramanya R. Dulloor, Rajesh M. Sankaran, David A. Koufaty, Christopher J. Hughes, Jong Soo Park, Sheng Li
  • Patent number: 10127042
    Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.
    Type: Grant
    Filed: December 31, 2016
    Date of Patent: November 13, 2018
    Assignee: Intel Corporation
    Inventors: Kirk S. Yap, Gilbert M. Wolrich, James D. Guilford, Vinodh Gopal, Erdinc Ozturk, Sean M. Gulley, Wajdi K. Feghali, Martin G. Dixon
  • Patent number: 10127968
    Abstract: In one embodiment, an apparatus comprises a processor core and a power control unit. The power control unit is to identify the occurrence of a power loss from a primary power source, instruct the I/O controller to block further write requests from the one or more I/O devices and to send at least one pending write request stored by the I/O controller to the memory controller, and instruct the memory controller to complete at least one pending write request stored by the memory controller and to cause the memory to be placed into a self-refresh mode.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: November 13, 2018
    Assignee: Intel Corporation
    Inventors: Samantha J. Edirisooriya, Shanker R. Nagesh, K L Siva Prasad Gadey N V, Blaine R. Monson, Pankaj Kumar
  • Patent number: 10126958
    Abstract: Techniques are disclosed for write suppression to improve endurance rating of non-volatile memories, such as QLC-NAND SSDs or other relatively slow, low endurance non-volatile memories. In an embodiment, an SSD is configured with a fast frontend non-volatile memory, a relatively slow lower endurance backend non-volatile memory, and a frontend manager that selectively transfers data from the fast memory to the slow memory based on transfer criteria. In operation, write data from the host is initially written to the fast memory by the frontend manager. The data is moved from the fast memory to the slow memory in bands. For each data band stored in the fast memory, the frontend manager tracks invalid data counts and data age. Only bands that still remain valid are transferred to the slow memory. After a given band has been fully transferred, it is erased and re-usable for other incoming writes by the frontend manager.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: November 13, 2018
    Assignee: INTEL CORPORATION
    Inventor: Anand S. Ramalingam
  • Patent number: 10127959
    Abstract: Embodiments include a sense amplifier circuit including first and second paths that may be selectively coupled to a memory cell or a reference cell as part of a two-phase read process. The sense amplifier may include a biasing circuit to provide an adaptive bias voltage to a transistor of the first and/or second path to cause the transistor to provide a voltage across the memory cell and/or reference cell that is substantially constant across process corners. Additionally, or alternatively, the sense amplifier may include a DC-coupled regenerative latch circuit to generate a digital output signal based on a voltage difference between nodes of the first and second paths at or near the end of the second phase. Additionally, or alternatively, trimmable offset resistors may adjust a resistance value provided to the sense amplifier by the memory cell and/or reference cells. Other embodiments may be described and claimed.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: November 13, 2018
    Assignee: Intel IP Corporation
    Inventors: Cyrille Dray, El Mehdi Boujamaa
  • Patent number: 10127162
    Abstract: Described is a host interface, a device interface, a downstream translation circuitry, an upstream translation circuitry, and a host line-state state machine. The host interface may comprise a host line-state output. The device interface may comprise a device line-state output. The downstream translation circuitry may be operable to process a transaction received on the host interface and to generate a transaction for the device interface. The upstream translation circuitry may be operable to process a transaction received on the device interface and to generate a transaction for the host interface. The host line-state state machine may be operable to set the host line-state output to a value that is one of: an SE0-state value, a J-state value, or a K-state value.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: November 13, 2018
    Assignee: Intel Corporation
    Inventors: Suketu U. Bhatt, Lakshminarayana Pappu, Satheesh Chellappan
  • Patent number: 10128177
    Abstract: Embodiments of the present disclosure describe a multi-layer package with antenna and associated techniques and configurations. In one embodiment, an integrated circuit (IC) package assembly includes a first layer having a first side and a second side disposed opposite to the first side a second layer coupled with the first side of the first layer, one or more antenna elements coupled with the second layer and a third layer coupled with the second side of the first layer, wherein the first layer is a reinforcement layer having a tensile modulus that is greater than a tensile modulus of the second layer and the third layer. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: November 13, 2018
    Assignee: INTEL CORPORATION
    Inventors: Telesphor Kamgaing, Adel A. Elsherbini, Torrey W. Frank
  • Patent number: 10127177
    Abstract: The present disclosure is directed to a unified device interface for a multi-bus system. In at least one embodiment, a system may comprise more than one data bus. Each data bus may be to convey data between an operating system (OS) and at least one device in the system, wherein a plurality of driver instances may facilitate interaction between the OS and a device via one or more of the data buses. In one embodiment, a main driver instance may be determined from the plurality of driver instances to present the device to the OS and coordinate operation of other driver instances. The other driver instances may map addresses in the memory of processing entities corresponding to each of the data buses and report these mappings to the main driver instance. Alternatively, a supervisory driver may be loaded to present the device and to control operation of the driver instances.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: November 13, 2018
    Assignee: Intel Corporation
    Inventors: Eliezer Tamir, Eliel Louzoun
  • Patent number: D833450
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: November 13, 2018
    Assignee: Intel Corporation
    Inventor: Nicholas Oakley