Intel Patents

Intel Corporation designs and manufactures microprocessors and chipsets for computing and communications equipment manufacturers. Its products may be found in desktops, servers, tablets, smartphones and other devices.

Intel Patents by Type
  • Intel Patents Granted: Intel patents that have been granted by the United States Patent and Trademark Office (USPTO).
  • Intel Patent Applications: Intel patent applications that are pending before the United States Patent and Trademark Office (USPTO).
  • Publication number: 20240089083
    Abstract: A method comprises receiving, from a remote device, a first encrypted data set encrypted using a first encryption scheme, performing a set of computations on the first encrypted data set to generate a first set of encrypted results, encrypting the first set of encrypted results using a second encryption scheme to generate a second set of encrypted results, sending the second set of encrypted results to the remote device, receiving, from the remote device, third set of encrypted results in which the first encryption scheme has been decrypted, and generating a set of decrypted results by applying a decryption algorithm to the third set of encrypted results to decrypt the second encryption scheme.
    Type: Application
    Filed: September 12, 2022
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Kylan Race, Ernesto Zamora Ramos, Jeremy Bottleson, Jingyi Jin
  • Publication number: 20240090025
    Abstract: For example, an Access Point (AP) may be configured to transmit a frame including a prioritized-access enabled/disabled field to indicate whether a prioritized-access contention mechanism is to be enabled or disabled over a wireless medium. For example, the prioritized-access contention mechanism may be configured to allow a prioritized station (STA) to transmit a reservation signal over the wireless medium at a reservation signal transmission time, and to contend the wireless medium according to a high-priority contention policy to obtain a Transmit Opportunity (TxOP) after transmission of the reservation signal. For example, the reservation signal transmission time may be based on an end of a predefined time duration from a start of a contention period. For example, the reservation signal may be configured to indicate a busy Clear Channel Assessment (CCA) to a receiving STA.
    Type: Application
    Filed: September 30, 2023
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Laurent Cariou, Thomas J. Kenney, Dmitry Akhmetov, Dibakar Das
  • Publication number: 20240088035
    Abstract: Described herein are full wafer devices that include passive devices formed in a power delivery structure. Power is delivered to the full wafer device on a backside of the full wafer device. A passive device in a backside layer is formed using an additive process that results in a seam running through the passive device. The seam may be, for example, an air gap, a change in material structure, or a region with a different chemical makeup from the surrounding passive device.
    Type: Application
    Filed: September 9, 2022
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Tahir Ghani, Wilfred Gomes, Anand S. Murthy
  • Publication number: 20240086357
    Abstract: Systems and methods for updating remote memory side caches in a multi-GPU configuration are disclosed herein. In one embodiment, a graphics processor for a multi-tile architecture includes a first graphics processing unit (GPU) having a first memory, a first memory side cache memory, a first communication fabric, and a first memory management unit (MMU). The graphics processor includes a second graphics processing unit (GPU) having a second memory, a second memory side cache memory, a second memory management unit (MMU), and a second communication fabric that is communicatively coupled to the first communication fabric. The first MMU is configured to control memory requests for the first memory, to update content in the first memory, to update content in the first memory side cache memory, and to determine whether to update the content in the second memory side cache memory.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Altug Koker, Joydeep Ray, Aravindh Anantaraman, Valentin Andrei, Abhishek Appu, Sean Coleman, Nicolas Galoppo Von Borries, Varghese George, Pattabhiraman K, SungYe Kim, Mike Macpherson, Subramaniam Maiyuran, Elmoustapha Ould-Ahmed-Vall, Vasanth Ranganathan, James Valerio
  • Publication number: 20240086064
    Abstract: Embodiments described herein enable the offload of address calculations required to access a data element within an array of data elements from primary compute resources of a graphics processor to the memory access circuitry of the graphics processor. The memory access circuitry is configured to receive a message to access a data element of an array of data elements in the memory, the message to include an index of the data element in the array of data elements, calculate a byte address for the data element based in part on the index of the data element in the array of data elements, and submit a memory access request to the memory to access the data element at the byte address.
    Type: Application
    Filed: September 14, 2022
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: John Wiegert, Joydeep Ray, Timothy Bauer, James Valerio
  • Publication number: 20240089082
    Abstract: A method comprises receiving, from an input device, an input speech signal, encoding the input speech signal to generate a first homomorphically encrypted string, sending the homomorphically encrypted string to a remote device via communication link, receiving, from the remote device, a reply comprising a second homomorphically encrypted string, decoding the second homomorphically encrypted string into an output speech signal, and outputting the output speech signal on an audio output device.
    Type: Application
    Filed: September 9, 2022
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Jeremy Bottleson, Ernesto Zamora Ramos, Kylan Race, Fillipe Dias Moreira de Souza, Hubert de Lassus, Jingyi Jin
  • Publication number: 20240086199
    Abstract: An apparatus to facilitate thread scheduling is disclosed. The apparatus includes logic to store barrier usage data based on a magnitude of barrier messages in an application kernel and a scheduler to schedule execution of threads across a plurality of multiprocessors based on the barrier usage data.
    Type: Application
    Filed: August 4, 2023
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Balaji Vembu, Abhishek R. Appu, Joydeep Ray, Altug Koker
  • Publication number: 20240089601
    Abstract: Multi-camera dynamic calibration can be performed using three or more images, each from a separate camera viewing the same 3D scene. Multi-camera translation magnitude can be determined by incorporating information from an additional image. A relative translation scale is determined for a configuration of three cameras using a ratio of translation magnitudes. The translation scale can be expanded to configurations having more than three cameras using the relative scale of the pair-wise camera translations to determine translation scales for a multi-camera set-up. If the ground-truth translation is known for a pair of cameras, then the translation magnitude can be determined for all pairs of cameras to ground-truth accuracy. Multi-camera scale estimation is divided into smaller overlapping triplet-camera scale estimation, and the translation scale determination corresponding to each image pair is applied iteratively to overlapping sets of three images.
    Type: Application
    Filed: November 13, 2023
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventor: Avinash Kumar
  • Publication number: 20240088029
    Abstract: Described herein are full wafer devices that include interconnect layers on a back side of the device. The backside interconnect layers couple together different dies of the full wafer device. The backside interconnect layers include an active layer that includes active devices, such as transistors. The active devices may act as switches, e.g., to control routing of signals between different dies of the full wafer device.
    Type: Application
    Filed: September 9, 2022
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Tahir Ghani, Wilfred Gomes, Anand S. Murthy, Sagar Suthram
  • Publication number: 20240086329
    Abstract: An apparatus to facilitate data prefetching is disclosed. The apparatus includes a cache, one or more execution units (EUs) to execute program code, prefetch logic to maintain tracking information of memory instructions in the program code that trigger a cache miss and compiler logic to receive the tracking information, insert one or more pre-fetch instructions in updated program code to prefetch data from a memory for execution of one or more of the memory instructions that triggered a cache miss and download the updated program code for execution by the one or more EUs.
    Type: Application
    Filed: September 20, 2023
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Vasileios Porpodas, Guei-Yuan Lueh, Subramaniam Maiyuran, Wei-Yu Chen
  • Publication number: 20240086258
    Abstract: An apparatus to facilitate disaggregated computing for a distributed confidential computing environment is disclosed. The apparatus includes one or more processors to facilitate receiving a manifest corresponding to graph nodes representing regions of memory of a remote client machine, the graph nodes corresponding to a command buffer and to associated data structures and kernels of the command buffer used to initialize a hardware accelerator and execute the kernels, and the manifest indicating a destination memory location of each of the graph nodes and dependencies of each of the graph nodes; identifying, based on the manifest, the command buffer and the associated data structures to copy to the host memory; identifying, based on the manifest, the kernels to copy to local memory of the hardware accelerator; and patching addresses in the command buffer copied to the host memory with updated addresses of corresponding locations in the host memory.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Reshma Lal, Pradeep Pappachan, Luis Kida, Soham Jayesh Desai, Sujoy Sen, Selvakumar Panneer, Robert Sharp
  • Publication number: 20240086683
    Abstract: An apparatus to facilitate workload scheduling is disclosed. The apparatus includes one or more clients, one or more processing units to processes workloads received from the one or more clients, including hardware resources and scheduling logic to schedule direct access of the hardware resources to the one or more clients to process the workloads.
    Type: Application
    Filed: September 21, 2023
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Liwei Ma, Nadathur Rajagopalan Satish, Jeremy Bottleson, Farshad Akhbari, Eriko Nurvitadhi, Chandrasekaran Sakthivel, Barath Lakshmanan, Jingyi Jin, Justin E. Gottschlich, Michael Strickland
  • Publication number: 20240086161
    Abstract: Described herein is a technique for automatic generation of optimized RTL via redundant code removal. By automatically introducing local mutations into the original RTL and using equivalence checking tools to confirm that the functionality it is not affected, optimized RTL can be produced automatically without requiring human intervention.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Theo Drane, Emiliano Morini, Jordan Schmerge, Samuel Coward
  • Publication number: 20240088069
    Abstract: Disclosed herein are integrated circuit (IC) supports with microstrips, and related embodiments. For example, an IC support may include a plurality of microstrips and a plurality of conductive segments. Individual ones of the conductive segments may be at least partially over at least two microstrips, a dielectric material may be between the plurality of microstrips and the plurality of conductive segments, and the conductive segments are included in a tape.
    Type: Application
    Filed: February 26, 2021
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Wenzhi Wang, Xiaoning Ye, Yunhui Chu, Chunfei Ye, James A. McCall
  • Publication number: 20240087077
    Abstract: Embodiments described herein provide a technique to merge partial cache line writes to a cache memory. One embodiment provides a graphics processor comprising a graphics core, a cache coupled with the graphics core, and memory access circuitry to process memory access messages received from the graphics core. The memory access circuitry includes partial cache line write merge circuitry configured to merge a first partial write to a cache line of the cache with a second partial write to the cache line of the cache.
    Type: Application
    Filed: September 14, 2022
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Joydeep Ray, Abhishek R. Appu, Prathamesh Raghunath Shinde, John Wiegert
  • Publication number: 20240088296
    Abstract: A nanowire device includes one or more nanowire having a first end portion, a second end portion, and a body portion between the first end portion and the second end portion. A first conductive structure is in contact with the first end portion and a second conductive structure is in contact with the second end portion. The body portion of the nanowire has a first cross-sectional shape and the first end portion has a second cross-sectional shape different from the first cross-sectional shape. Integrated circuits including the nanowire device and a method of cleaning a semiconductor structure are also disclosed.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Erica J. THOMPSON, Aditya Kasukurti, Jun Sung Kang, Kai Loon Cheong, Biswajeet Guha, William Hsu, Bruce Beattie
  • Publication number: 20240086356
    Abstract: Embodiments described herein provide techniques to facilitate instruction-based control of memory attributes. One embodiment provides a graphics processor comprising a processing resource, a memory device, a cache coupled with the processing resources and the memory, and circuitry to process a memory access message received from the processing resource. The memory access message enables access to data of the memory device. To process the memory access message, the circuitry is configured to determine one or more cache attributes that indicate whether the data should be read from or stored the cache. The cache attributes may be provided by the memory access message or stored in state data associated with the data to be accessed by the access message.
    Type: Application
    Filed: October 20, 2023
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Joydeep Ray, Altug Koker, Varghese George, Mike Macpherson, Aravindh Anantaraman, Abhishek R. Appu, Elmoustapha Ould-Ahmed-Vall, Nicolas Galoppo von Borries, Ben J. Ashbaugh
  • Publication number: 20240088199
    Abstract: Techniques for a glass core inductor are disclosed. In the illustrative embodiment, an integrated circuit component includes a glass substrate and a fully-integrated voltage regulator (FIVR). The FIVR includes a glass core inductor that is embedded in the glass substrate. Each inductor turn of the inductor includes two angled through-glass vias and a trace on top of the glass substrate connecting the angled through-glass vias, resulting in an inductor with a cross-section in the shape of a triangle or trapezoid. The inductor may have a relatively large inductance per unit area, requiring less space or allowing for a larger inductance.
    Type: Application
    Filed: September 13, 2022
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Brandon Christian Marin, Suddhasattwa Nad, Srinivas V. Pietambaram, Jeremy D. Ecton, Mohammad Rahman, Gang Duan
  • Publication number: 20240086291
    Abstract: An apparatus comprising first circuitry to process a request generated by a first device, the request specifying a memory address range of a second device to monitor for errors; and second circuitry to, based on a determination that a read request targets the memory address range of the second device, compare first data read from the second device with second data read from a memory to determine whether an error has occurred.
    Type: Application
    Filed: September 9, 2022
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Amruta Misra
  • Publication number: 20240088017
    Abstract: Described herein are full wafer devices that include passive devices formed in one or more interconnect layers. Interconnect layers are formed over a front side of the full wafer device. A passive device is formed using an additive process that results in a seam running through the passive device. The seam may be, for example, an air gap, a change in material structure, or a region with a different chemical makeup from the surrounding passive device. In some embodiments, the passive devices are formed in global interconnect layers coupling multiple does of the full wafer device.
    Type: Application
    Filed: September 9, 2022
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Tahir Ghani, Wilfred Gomes, Anand S. Murthy, Pushkar Sharad Ranade, Sagar Suthram
  • Publication number: 20240088134
    Abstract: An integrated circuit structure includes laterally adjacent first and second devices. The first device has (i) a first diffusion region, (ii) a first body including semiconductor material extending laterally from the first diffusion region, and (iii) a first gate structure on the first body. The first diffusion region has a first lower section that extends below a lower surface of the first gate structure, the first lower section having a first height. The second device has (i) a second diffusion region, (ii) a second body including semiconductor material extending laterally from the second diffusion region, and (iii) a second gate structure on the second body. The second diffusion region has a second lower section that extends below a lower surface of the second gate structure, the second lower section having a second height. In an example, the first height is at least 2 nanometers greater than the second height.
    Type: Application
    Filed: September 13, 2022
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Nicholas A. Thomson, Ayan Kar, Kalyan C. Kolluru, Mauro J. Kobrinsky
  • Publication number: 20240088887
    Abstract: An apparatus comprises a first supply node to provide a first voltage and a second supply node to provide a second voltage lower than the first voltage. First and second transistors, of a first conductivity type, are coupled in series at a first common node, wherein the first transistor is coupled to the first supply node, and the second transistor is coupled to an output node. Third and fourth transistors, of a second conductivity type, coupled in series at a second common node, wherein the fourth transistor is coupled to a third node that is to provide a third voltage, and the third transistor is coupled to the output node. First impedance circuitry is coupled to a gate terminal of the second transistor, the second supply node, and to a gate terminal of the first transistor.
    Type: Application
    Filed: November 23, 2022
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Dharmaray Nedalgi, Lavanya Manohar Nirikhi
  • Publication number: 20240088217
    Abstract: Techniques are provided herein to form semiconductor devices that include a layer across an upper surface of a dielectric fill between devices and configured to prevent or otherwise reduce recessing of the dielectric fill. In this manner, the layer may be referred to as a barrier layer or recess-inhibiting layer. The semiconductor regions of the devices extend above a subfin region that may be native to the substrate. These subfin regions are separated from one another using a dielectric fill that acts as a shallow trench isolation (STI) structure to electrically isolate devices from one another. A barrier layer is formed over the dielectric fill early in the fabrication process to prevent or otherwise reduce the dielectric fill from recessing during subsequent processing. The layer may include oxygen and a metal, such as aluminum.
    Type: Application
    Filed: September 8, 2022
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Tao Chu, Minwoo Jang, Chia-Ching Lin, Yanbin Luo, Ting-Hsiang Hung, Feng Zhang, Guowei Xu
  • Publication number: 20240088131
    Abstract: An integrated circuit structure includes a sub-fin having at least a portion that is doped with a first type of dopant, and a diffusion region doped with a second type of dopant. The diffusion region is in contact with the sub-fin and extends upward from the sub-fin. The first type of dopant is one of a p-type or an n-type dopant, and the second type of dopant is the other of the p-type or the n-type dopant. In an example, a first conductive contact is above and on the diffusion region, and a second conductive contact is in contact with the portion of the sub-fin. In an example, the diffusion region is at least a part of one of an anode or a cathode of a diode, and the portion of the sub-fin is at least a part of the other of the anode or the cathode of the diode.
    Type: Application
    Filed: September 13, 2022
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Nicholas A. Thomson, Kalyan C. Kolluru, Ayan Kar, Mauro J. Kobrinsky
  • Publication number: 20240088265
    Abstract: Techniques are provided herein to form semiconductor devices having epitaxial growth laterally extending between inner spacer structures to mitigate issues caused by the inner spacer structures either being too thick or too thin. A directional etch is performed along the side of a multilayer fin to create a relatively narrow opening for a source or drain region to increase the usable fin space for forming the inner spacer structures. After the inner spacer structures are formed around ends of the semiconductor layers within the fin, the exposed ends of the semiconductor layers are laterally recessed inwards from the outermost sidewalls of the inner spacer structures. Accordingly, the epitaxial source or drain region is grown from the recessed semiconductor ends and thus fills in the recessed regions between the spacer structures.
    Type: Application
    Filed: September 8, 2022
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Tao Chu, Guowei Xu, Feng Zhang, Ting-Hsiang Hung, Chia-Ching Lin
  • Publication number: 20240088136
    Abstract: An integrated circuit structure includes a sub-fin, a source region in contact with a first portion of the sub-fin, and a drain region in contact with a second portion of the sub-fin. A body including semiconductor material is above the sub-fin, where the body extends laterally between the source region and the drain region. A gate structure is on the body and includes (i) a gate electrode, and (ii) a gate dielectric between the gate electrode and the body. In an example, a first distance between the drain region and the gate electrode is at least two times a second distance between the source region and the gate electrode, where the first and second distances are measured in a same horizontal plane that runs in a direction parallel to the body. In an example, the body is a nanoribbon, a nanosheet, a nanowire, or a fin.
    Type: Application
    Filed: September 13, 2022
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Ayan Kar, Nicholas A. Thomson, Kalyan C. Kolluru, Benjamin Orr
  • Publication number: 20240088218
    Abstract: Techniques are provided herein to form an integrated circuit having a grating pattern of gate cut structures such that a gate cut structure extends between the gate layers of adjacent semiconductor devices and between the source or drain regions (e.g., epitaxial regions) of the adjacent semiconductor devices. In an example, neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate structure extending over the semiconductor regions of the neighboring semiconductor devices. In some such examples, a gate cut structure is present between each pair of neighboring semiconductor devices thus interrupting the gate structure and isolating the gate electrode of one semiconductor device from the gate electrode of the other semiconductor device. The gate cut structure further extends to separate the source or drain regions of the neighboring semiconductor devices.
    Type: Application
    Filed: September 13, 2022
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Shao-Ming Koh, Leonard P. Guler, Gurpreet Singh, Manish Chandhok, Matthew J. Prince
  • Publication number: 20240088132
    Abstract: An integrated circuit structure includes a sub-fin having (i) a first portion including a p-type dopant and (ii) a second portion including an n-type dopant. A first body of semiconductor material is above the first portion of the sub-fin, and a second body of semiconductor material is above the second portion of the sub-fin. In an example, the first portion of the sub-fin and the second portion of the sub-fin are in contact with each other, to form a PN junction of a diode. For example, the first portion of the sub-fin is part of an anode of the diode, and wherein the second portion of the sub-fin is part of a cathode of the diode.
    Type: Application
    Filed: September 13, 2022
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Nicholas A. Thomson, Kalyan C. Kolluru, Ayan Kar, Chu-Hsin Liang, Benjamin Orr, Biswajeet Guha, Brian Greene, Chung-Hsun Lin, Sabih U. Omar, Sameer Jayanta Joglekar
  • Patent number: 11929212
    Abstract: Embodiments disclosed herein include an electronic package and methods of forming an electronic package. In an embodiment, the electronic package comprises a package substrate, an organic layer over the package substrate, and a capacitor embedded in the organic layer. In an embodiment, the capacitor comprises, a first electrode, where the first electrode comprises a seam between a first conductive layer and a second conductive layer, a dielectric layer over the first electrode, and a second electrode over the dielectric layer.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Sameer Paital, Gang Duan, Srinivas Pietambaram, Kristof Darmawikarta
  • Patent number: 11928787
    Abstract: Systems, apparatuses and methods may provide for technology that estimates poses of a plurality of input images, reconstructs a proxy three-dimensional (3D) geometry based on the estimated poses and the plurality of input images, detects a user selection of a virtual viewpoint, encodes, via a first neural network, the plurality of input images with feature maps, warps the feature maps of the encoded plurality of input images based on the virtual viewpoint and the proxy 3D geometry, and blends, via a second neural network, the warped feature maps into a single image, wherein the first neural network is deep convolutional network and the second neural network is a recurrent convolutional network.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Gernot Riegler, Vladlen Koltun
  • Patent number: 11928860
    Abstract: Techniques related to object detection using an adaptive convolutional neural network (CNN) are discussed. Such techniques include applying one of multiple configurations of the CNN to input image data in response to an available computational resources for processing the input image data.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Konstantin Vladimirovich Rodyushkin, Alexander Vladimirovich Bovyrin
  • Patent number: 11928215
    Abstract: An apparatus to verify firmware in a computing system, comprising a non-volatile memory, including firmware memory to store agent firmware associated with each of a plurality of interconnect protocol (IP) agents and version memory to store security version numbers (SVNs) included in the agent firmware, a security controller comprising verifier logic to verify an integrity of the version memory by applying a hash algorithm to contents of the version memory to generate a SVN hash, and a trusted platform module (TPM) to store the SVN hash.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Prashant Dewan, Chao Zhang, Nivedita Aggarwal, Aditya Katragada, Mohamed Haniffa, Kenji Chen
  • Patent number: 11929320
    Abstract: A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Ryan Keech, Cory Bomberger, Cheng-Ying Huang, Ashish Agrawal, Willy Rachmady, Anand Murthy
  • Patent number: 11927982
    Abstract: An integrated clock gate (ICG) includes an OR-AND-INVERT gate to receive a first enable and a second enable; a first inverter coupled to the output of the OR-AND-INVERT; a first NAND gate coupled to the output of the first inverter; a second NAND gate coupled to the output of the OR-AND-INVERT; and a second inverter to provide a clock which is gated based on logic values of the first enable and/or the second enable, wherein an output of the second inverter is received as input by the OR-AND-INVERT-gate. The ICG circuit reduces capacitance of input clk pin, which translates to lower switching power when clock is gated and reduction in dynamic power of clock network, since buffers in clock tree driving the ICG cells can be downsized. The ICG cell has the smallest transistor count (and area) when compared to existing ICG cell topologies.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: March 12, 2024
    Assignee: INTEL CORPORATION
    Inventors: Gururaj K. Shamanna, Naveen Kumar M, Harishankar Sahu, Abhishek Chouksey, Madhusudan Rao
  • Patent number: 11928472
    Abstract: Methods and apparatus relating to branch prefetch mechanisms for mitigating front-end branch resteers are described. In an embodiment, predecodes an entry in a cache to generate a predecoded branch operation. The entry is associated with a cold branch operation, where the cold branch operation corresponds to an operation that is detected for a first time after storage in an instruction cache and wherein the cold branch operation remains undecoded since it is stored at a location in a cache line prior to a subsequent location of a branch operation in the cache line. The predecoded branch operation is stored in a Branch Prefetch Buffer (BPB) in response to a cache line fill operation of the cold branch operation in an instruction cache. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: September 26, 2020
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Gilles Pokam, Jared Warner Stark, IV, Niranjan Kumar Soundararajan, Oleg Ladin
  • Patent number: 11928753
    Abstract: Techniques related to automatically segmenting video frames into per pixel fidelity object of interest and background regions are discussed. Such techniques include applying tessellation to a video frame to generate feature frames corresponding to the video frame and applying a segmentation network implementing context aware skip connections to an input volume including the feature frames and a context feature volume corresponding to the video frame to generate a segmentation for the video frame.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Anthony Rhodes, Manan Goel
  • Patent number: 11929295
    Abstract: A semiconductor package is disclosed, which comprises a substrate, one or more dies on a first side of the substrate, and a plurality of interconnect structures having a first pitch and coupled to a second side of the substrate. The interconnect structures may attach the substrate to a board. The substrate may include a first interconnect layer having a second pitch. The first interconnect layer may be coupled to the one or more dies through second one or more interconnect layers. Third one or more interconnect layers between the first interconnect layer and the interconnect structures may translate the first pitch to the second pitch. The substrate may include a recess on a section of the second side of the substrate. The semiconductor package may further include one or more components within the recess and attached to the second side of the substrate.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Eng Huat Goh, Jiun Hann Sir, Min Suet Lim, Richard C. Stamey, Chu Aun Lim, Jimin Yao
  • Patent number: 11929339
    Abstract: An integrated circuit includes a package substrate that includes first and second electrical traces. The integrated circuit includes first, second, third, and fourth configurable dies, which are mounted on the package substrate. The first and second configurable dies are arranged in a first row. The third and fourth configurable dies are arranged in a second row, which is approximately parallel to the first row. The first and third configurable dies are arranged in a first column. The second and fourth configurable dies are arranged in a second column, which is approximately parallel to the first column. The first electrical trace couples the first and third configurable dies, and the second electrical trace couples the second and third configurable dies. The second electrical trace is oblique with respect to the first electrical trace. The oblique trace improves the latency of signals transmitted between dies and thereby increases the circuit operating speed.
    Type: Grant
    Filed: April 13, 2023
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Md Altaf Hossain, Ankireddy Nalamalpu, Dheeraj Subbareddy
  • Patent number: 11928042
    Abstract: A method and apparatus to detect, initialize and isolate a non-operating memory module in a system without physically removing the memory module from the system is provided. The memory module includes a power management integrated circuit to provide power to a memory integrated circuit on the memory module. During initialization of the memory module, if an error log stored in a non-volatile memory in the memory module indicates a fatal error condition from a prior power cycle, the memory module is electrically isolated.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Dat T. Le, George Vergis
  • Patent number: 11930479
    Abstract: Systems and methods for transmission of PDSCH and HARQ-ACK feedback in 5G networks are described. The TDRA of PDSCH repetitions are indicated in a DCI by a SLIV sequence configuration that contains multiple SLIV sequences. Each SLIV sequence for a slot is associated with an independent repetition factor and may also be associated with a partition factor to indicate a partition within the slot. One or more TRPs may be used to transmit each PDSCH repetition. The TCI states are mapped to the PDSCH repetitions in a round-robin fashion using an offset in terms of number of PDSCH repetitions from where TCI state switching starts and a number of consecutive PDSCH repetitions per TCI state. The HARQ-ACK bits in response to the PDSCH from the TRPs are concatenated in order of increasing control resource set higher layer signaling index.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Bishwarup Mondal, Gang Xiong, Alexei Davydov, Avik Sengupta, Sergey Panteleev, Debdeep Chatterjee
  • Patent number: 11928443
    Abstract: A circuit system includes a memory block and first and second processing circuits. The first and second processing circuits store a matrix in the memory block by concurrently writing elements in first and second rows or columns of the matrix to first and second regions of storage in the memory block, respectively. The first and second processing circuits transpose the matrix to generate a transposed matrix by concurrently reading elements in first and second rows or columns of the transposed matrix from third and fourth regions of storage in the memory block, respectively.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventor: Hong Shan Neoh
  • Patent number: 11930620
    Abstract: There is disclosed in one example a heat dissipator for an electronic apparatus, including: a planar vapor chamber having a substantially rectangular form factor, wherein a second dimension d2 of the rectangular form factor is at least approximately twice a first dimension d1 of the rectangular form factor; a first fan and second fan; and a first heat pipe and second heat pipe discrete from the planar vapor chamber and disposed along first and second d1 edges of the planar vapor chamber, further disposed to conduct heat from the first and second d1 edges to the first and second fan respectively.
    Type: Grant
    Filed: June 27, 2020
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Jeff Ku, Cora Nien, Gavin Sung, Tim Liu, Lance Lin, Wan Yu Liu, Gerry Juan, Jason Y. Jiang, Justin M. Huttula, Evan Piotr Kuklinski, Juha Tapani Paavola, Arnab Sen, Hari Shanker Thakur, Prakash Kurma Raju
  • Patent number: 11929888
    Abstract: Technologies for managing Function-as-a-Service function requests based on thermal and power awareness include an edge entity device having a circuitry to receive, from an edge device, a request to execute a function in an edge network environment having a plurality of edge entities. The circuitry is also to evaluate thermal and power criteria associated with the request and determine, as a function of a predicted thermal output over a specified time period relative to thermal and power criteria, whether to execute the function. In response to a determination by the circuitry to not execute the function, the circuitry is to select an edge entity of a plurality of edge entities that is able to satisfy the thermal and power criteria. The circuitry is further to forward the request to the selected edge entity.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: March 12, 2024
    Assignee: INTEL CORPORATION
    Inventor: Francesc Guim Bernat
  • Patent number: 11929927
    Abstract: A network interface controller can be programmed to direct write received data to a memory buffer via either a host-to-device fabric or an accelerator fabric. For packets received that are to be written to a memory buffer associated with an accelerator device, the network interface controller can determine an address translation of a destination memory address of the received packet and determine whether to use a secondary head. If a translated address is available and a secondary head is to be used, a direct memory access (DMA) engine is used to copy a portion of the received packet via the accelerator fabric to a destination memory buffer associated with the address translation. Accordingly, copying a portion of the received packet through the host-to-device fabric and to a destination memory can be avoided and utilization of the host-to-device fabric can be reduced for accelerator bound traffic.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Pratik M. Marolia, Rajesh M. Sankaran, Ashok Raj, Nrupal Jani, Parthasarathy Sarangam, Robert O. Sharp
  • Patent number: 11929396
    Abstract: A transistor structure includes a base and a body over the base. The body comprises a semiconductor material and has a first end portion and a second end portion. A gate structure is wrapped around the body between the first end portion and the second end portion, where the gate structure includes a gate electrode and a dielectric between the gate electrode and the body. A source is in contact with the first end portion and a drain is in contact with the second end portion. A first spacer material is on opposite sides of the gate electrode and above the first end portion. A second spacer material is adjacent the gate structure and under the first end portion of the nanowire body. The second spacer material is below and in contact with a bottom surface of the source and the drain.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: William Hsu, Biswajeet Guha, Leonard Guler, Souvik Chakrabarty, Jun Sung Kang, Bruce Beattie, Tahir Ghani
  • Patent number: 11930365
    Abstract: Systems, apparatus, methods, and techniques for reporting an attack or intrusion into an in-vehicle network are provided. The attack can be broadcast to connected vehicles over a vehicle-to-vehicle network. The broadcast can include an indication of a sub-system involved in the attack and can include a request for assistance in recovering from the attack. Connected vehicles can broadcast responses over the vehicle-to-vehicle network. The responses can include indications of data related to the compromised sub-system. The vehicle can receive the responses and can use the responses to recover from the attack, such as, estimate data.
    Type: Grant
    Filed: May 12, 2022
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Liuyang Yang, Xiruo Liu, Manoj Sastry, Marcio Juliato, Shabbir Ahmed, Christopher Gutierrez
  • Patent number: 11929330
    Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Kristof Darmawikarta, Hiroki Tanaka, Robert May, Sameer Paital, Bai Nie, Jesse Jones, Chung Kwang Christopher Tan
  • Patent number: 11929415
    Abstract: A device is disclosed. The device includes a source contact and a drain contact, a first dielectric between the source contact and the drain contact, a channel under the source contact and the drain contact, and a gate electrode below the channel, the gate electrode in an area under the first dielectric that does not laterally extend under the source contact or the drain contact. A second dielectric is above the gate electrode and underneath the channel.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Chieh-Jen Ku, Pei-Hua Wang, Bernhard Sell, Travis W. Lajoie
  • Patent number: 11929435
    Abstract: Techniques are disclosed for an integrated circuit including a ferroelectric gate stack including a ferroelectric layer, an interfacial oxide layer, and a gate electrode. The ferroelectric layer can be voltage activated to switch between two ferroelectric states. Employing such a ferroelectric layer provides a reduction in leakage current in an off-state and provides an increase in charge in an on-state. The interfacial oxide layer can be formed between the ferroelectric layer and the gate electrode. Alternatively, the ferroelectric layer can be formed between the interfacial oxide layer and the gate electrode.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Willy Rachmady, Jack T. Kavalieros, Cheng-Ying Huang, Matthew V. Metz, Sean T. Ma, Harold Kennel, Tahir Ghani
  • Patent number: 11928845
    Abstract: An apparatus to facilitate real-time playback of point cloud sequence data is disclosed. The apparatus comprises one or more processors to receive point cloud data of a captured scene, decompose the point cloud data into a plurality of point cloud patches, wherein each point cloud patch is associated with an object in the scene and includes contextual information regarding the point cloud patch, encode each of the point cloud patches via a deep-learning based algorithm to generate encoded point cloud patches, receive a viewpoint selection from a client, assign a priority to data chunks within each encoded point cloud patch based on the viewpoint selection and the contextual information and transmit the data chunks to the client based on the assigned priority.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Fai Yeung, Wayne Cochran, Pratibha Pandhare