Abstract: This disclosure describes systems, methods, and devices related to an unlicensed national information infrastructure 4 (UNII4) discovery. A device may identify a UNII4 discovery request received from a station device (STA) by a first AP of the AP MLD. The device may send the UNII4 discovery request from the first AP to a second AP of the AP MLD, wherein the second AP is capable of operating on a UNII4 frequency band. The device may send a discovery response to the discovery request from the second AP to the STA. The device may establish a first link in a multi-link operation between the second AP and the STA.

Abstract: For example, a first wireless communication device may be configured to determine a negotiated bootstrapping mechanism based on a first message-exchange including Peer-to-Peer (P2P) messages exchanged with a second wireless communication device; to pair the first wireless communication device with the second wireless communication device according to the negotiated bootstrapping mechanism; to derive a Pairwise Master Key Security Association (PMKSA) based on a second message-exchange with the second wireless communication device, e.g., after pairing with the second wireless communication device; and to determine an encryption key according to a third message exchange with the second wireless communication device based on the PMKSA. For example, the encryption key may be configured to encrypt a P2P communication with the second wireless communication device.

Abstract: An apparatus of a New Radio (NR) User Equipment (UE), includes the processing circuitry to: detect a synchronization signal block (SSB) from a NR Node B (gNB); determine a number of multiple physical random access channel (PRACH) transmissions, wherein respective PRACH transmissions of the multiple PRACH transmissions correspond to repetitions of each other and to a preamble; determine a set of valid PRACH occasions associated with the SSB, wherein respective ones of the valid PRACH occasions of the set: are in sequential respective time instances; and use same frequency resources as any immediately prior PRACH occasion of the set; and send the multiple PRACH transmissions in the set for transmission to the gNB.

Abstract: Graphics processors and graphics processing units having dot product accumulate instructions for a hybrid floating point format are disclosed. In one embodiment, a graphics multiprocessor comprises an instruction unit to dispatch instructions and a processing resource coupled to the instruction unit. The processing resource is configured to receive a dot product accumulate instruction from the instruction unit and to process the dot product accumulate instruction using a bfloat16 number (BF16) format.

Abstract: A student model may be trained in two stages by using two teacher models, respectively. The first teacher model has been trained with a pretraining dataset. The second teacher model has been trained with a training dataset that is specific to a task to be performed by the student model. In the first stage, the student model may be generated based on a structure of the first teacher model. Internal parameters of the student model are adjusted through a pretraining process based on the first teacher model and the pretraining dataset. Weights of the student model may be pruned during the pretraining process. In the second stage, a sparsity mask is generated for the student model to lock the sparsity pattern generated from the first stage. Further, some of the internal parameters of the student model are modified based on the second teacher model and the training dataset.

Abstract: For example, a first wireless communication device may be configured to determine a negotiated bootstrapping mechanism based on a first message-exchange including Peer-to-Peer (P2P) messages exchanged with a second wireless communication device; to pair the first wireless communication device with the second wireless communication device according to the negotiated bootstrapping mechanism; to derive a Pairwise Master Key Security Association (PMKSA) based on a second message-exchange with the second wireless communication device, e.g., after pairing with the second wireless communication device; and to determine an encryption key according to a third message exchange with the second wireless communication device based on the PMKSA. For example, the encryption key may be configured to encrypt a P2P communication with the second wireless communication device.

Abstract: An integrated circuit having a transistor architecture includes a first semiconductor body and a second semiconductor body. The first and second semiconductor bodies are arranged vertically (e.g., stacked configuration) or horizontally (e.g., forksheet configuration) with respect to each other, and separated from one another by insulator material, and each can be configured for planar or non-planar transistor topology. A first gate structure is on the first semiconductor body, and includes a first gate electrode and a first high-k gate dielectric. A second gate structure is on the second semiconductor body, and includes a second gate electrode and a second high-k gate dielectric. In an example, the first gate electrode includes a layer comprising a compound of silicon and one or more metals; the second gate structure may include a silicide workfunction layer, or not. In one example, the first gate electrode is n-type, and the second gate electrode is p-type.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.

Abstract: A computation system for deep learning applications includes a memory and a processor. The memory is configured to store numerical data at a given stored datatype. The processor includes a processing vector unit and a reduction module. The processing vector unit has a given vector width. The reduction module is configured to reduce a dimension of an input tensor by (i) defining a sequence of elements of the input tensor, which follows a path through the input tensor that is derived from a datatype size of the elements of the input tensor, the given size of the processing vector unit, and the stored datatype, and (ii) forming an output vector by traversing the elements of the input tensor according to the path.

Abstract: Methods, systems, mediums, and devices use video processing with low latency bitstream distribution.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to align network traffic to improve power consumption. Example instructions cause one or more processors to classify a workload based on network packets obtained via a wireless communication; determine heuristics of platform activities corresponding to the workload; and schedule network interrupts based on hardware-based wake interrupts from a sleep mode using the heuristics.

Abstract: Embodiments detailed herein relate to matrix (tile) operations. For example, decode circuitry to decode an instruction having fields for an opcode and a memory address; and execution circuitry to execute the decoded instruction to set a tile configuration for the processor to utilize tiles in matrix operations based on a description retrieved from the memory address, wherein a tile a set of 2-dimensional registers are discussed.

Abstract: Embodiments herein relate to a machine learning (ML) management system of a cellular network. The ML management system may be configure to emulate, or facilitate emulation of, a trained ML model in an emulation environment. ML emulation may refer to performing inference using the ML model in an emulation environment that is different than an inference environment of the cellular network. Other embodiments may be described and/or claimed.

Abstract: Bonding interfaces between a die and a carrier wafer are described herein. Using a bonding layer between wafers that includes metal, a doped dielectric material, and/or a semiconductor material may reduce damage from processes such as dicing. In one example, dopants are introduced into a dielectric material before bonding. In another example, the bonding layer includes a semiconductor material. In one example, a conductive material including a metal is used as a bonding interface between wafers. In some examples, the metallic bonding material may be patterned. In some examples, a conductive material including metal may replace a dielectric material as a bonding material. In other examples, the bonding interface may include a layer of conductive material and a layer of a dielectric material or a semiconductor material.

Abstract: An electronic system includes a substrate and a top surface active component die. The substrate includes a glass core layer having a glass core layer active component die disposed in a cavity and a discrete passive component disposed in another cavity; a mold layer including a mold layer active component die disposed in the mold layer; and a buildup layer contacting a top surface of the glass core layer and a bottom surface of the mold layer. The buildup layer includes electrically conductive interconnect connecting the glass core layer active component die, the discrete passive component, and the mold layer active component die. The top surface of the component die is electrically connected to the mold layer active component die.

Abstract: A data-free model compression method includes uploading a pre-trained model to a processor. A trainable model is defined. Random data samples are inputted to the pretrained model and a loss function including a loss term is iteratively minimized to obtain a training data set, the loss term quantifying differences in batch normalization statistics (BNS) between activation statistics of the pretrained model and intermediate batch normalization statistics of the pretrained model. Using the training data set, the trainable model is compressed by minimizing a total loss between the trained trainable model and the pretrained model, to obtain a compressed topology of the trained model.

Abstract: A digital-to-analog converter (DAC) and a method for correcting amplitude and/or skew error in a DAC. The DAC includes a main DAC, cell error determination circuit, a correction DAC, and a combiner. The main DAC includes a plurality of DAC cells. The cell error determination circuit is configured to determine an amplitude error and/or a skew error of each of the plurality of DAC cells and generate error data of the DAC based on the input data to the DAC cells. The correction DAC is configured to generate an error signal based on the error data. The combiner is configured to combine the error signal with an output of the main DAC.

Abstract: An apparatus to facilitate protecting assets of mutually distrustful entities during federated learning training on a remote device is disclosed. The apparatus includes a processor to a processor to: receive, at a trusted execution environment (TEE) hosted by a client platform, an encrypted machine learning (ML) model and a cryptographic message authentication code (MAC) from a model owner platform, wherein the encrypted ML model is encrypted by the model owner platform using homomorphic encryption (HE); verify integrity of the encrypted ML model using the cryptographic MAC and a TEE key established by the processor during remote attestation of the TEE with the model owner platform; perform, in the TEE, training of the encrypted ML model using HE computation on sensor data; and send, to the model owner platform, output of the training comprising updated model parameters of the encrypted ML model, where the output is homomorphically encrypted.

Abstract: Embodiments described herein provide a system of concurrent compute queues that enable the scheduling of a large number of compute contexts simultaneously on graphics processor hardware. One embodiment provides an apparatus comprising a system interface and a general-purpose graphics processor coupled with the system interface. The general-purpose graphics processor comprises a plurality of graphics processor hardware resources configured to be partitioned into a plurality of isolated partitions, each of the plurality of isolated partitions including a first command streamer, a second command streamer, and circuitry configured to schedule general-purpose graphics compute workloads submitted to a first plurality of command queues associated with the first command streamer and a second plurality of command queues associated with the second command streamer.

Abstract: This disclosure describes systems, methods, and devices related to real-time multi-person three-dimensional pose tracking using a single camera.

Abstract: Various approaches for monitoring and responding to orchestration or service failures with the use of infrastructure processing units (IPUs) and similar networked processing units are disclosed. A method performed by a computing device for deploying remedial actions in failure scenarios of an orchestrated edge computing environment may include: identifying an orchestration configuration of a controller entity (responsible for orchestration) and a worker entity (subject to the orchestration to provide at least one service); determining a failure scenario of the orchestration of the worker entity, such as at a networked processing unit implemented at a network interface located between the controller entity and the worker entity; and causing a remedial action to resolve the failure scenario and modify the orchestration configuration, such as replacing functionality of the controller entity or the worker entity with functionality at a replacement entity.

Abstract: This disclosure describes electrostatic wafer chuck designs for holding and heating semiconductor wafers. An electrostatic wafer chuck may include a metal base; a temperature sensor; and a multi-layer ceramic plate including: a bonding layer; a heater; a first dielectric positioned between the heater and the bonding layer; an electrode to electrostatically hold a semiconductor wafer; a second dielectric positioned between the heater and the electrode; a heat spreader to uniformly distribute heat from the heater to the semiconductor wafer; and a third dielectric positioned between the electrode and the semiconductor wafer; and a temperature sensor may extend through the metal base and at least partially through the multi-layer ceramic plate.

Abstract: Examples include techniques associated with data movement to a cache in a disaggregated die system. Examples include circuitry at a first die receiving and granting requests to move data to a first cache resident on the first die or to a second cache resident on a second die that also includes a core of a processor. The granting of the request based, at least in part, on a traffic source type associated with a source of the request.

Abstract: An offload analyzer analyzes a program for porting to a heterogeneous computing system by identifying code objects for offloading to an accelerator. Runtime metrics generated by executing the program on a host processor unit are provided to an accelerator model that models the performance of the accelerator and generates estimated accelerator metrics for the program. A code object offload selector selects code objects for offloading based on whether estimated accelerated times of the code objects, which comprise estimated accelerator times and offload overhead times, are better than their host processor unit execution times. The code object offload selector selects additional code objects for offloading using a dynamic-programming-like performance estimation approach that performs a bottom-up traversal of a call tree. A heterogeneous version of the program can be generated for execution on the heterogeneous computing system.

Abstract: Disclosed herein is a radio frequency (RF) circuit for a transmit/receive switch that includes an antenna coupled to a receive path through a first coupled transmission line. The antenna is also coupled to a transmit path through a second coupled transmission line. The RF circuit includes a receiver switch configured to selectively present to the receive path a high impedance or a low impedance to ground and a transmitter switch configured to selectively present to the transmit path a high impedance or a low impedance to ground. The receiver switch and/or transmitter switch may be independently supplied with a bias voltage that depends on whether the circuit is operating in a transmit mode or receive mode. The RF circuit may have improved insertion loss, bandwidth, and linearity, while also providing robustness to electrostatic discharge (ESD).

Abstract: Various embodiments herein are directed to beamforming associated with multiple-input multiple-output (MIMO) modes in open radio access network (O-RAN) systems. In one embodiment, an apparatus comprises: memory to store beamforming configuration information associated with a plurality MIMO modes; and processing circuitry, coupled with the memory to: retrieve the beamforming configuration information from the memory; request, based on the beamforming configuration information, measurements associated with the plurality of MIMO modes; receive the measurements associated with the plurality of MIMO modes; and based on the received measurements, train an artificial intelligence/machine learning (AI/ML) model that is to predict relative beamforming performance between the plurality of MIMO modes.

Abstract: A physical layer (PHY) device of a switch system of a computing network, a switch system including the PHY device, a tangible non-transitory machine-readable medium to perform operations at the PHY device, and a method to be performed at the PHY device. The PHY device includes a first physical input/output (I/O), and a second physical (I/O), and PHY circuitry coupled between the first I/O and the second I/O. The PHY circuitry includes one of a retimer circuitry or a switch circuitry, and is to: implement a plurality of ports at the first I/O, and a data link at the second I/O; access a plurality of data flows from the plurality of ports at the first I/O; determine a multiplexed data stream from the plurality of data flows by implementing a multiplexing algorithm; and send the multiplexed data stream for transmission from the data link at the second I/O.

Abstract: Techniques are provided herein to form semiconductor devices having different gate oxide thicknesses. A first semiconductor device includes a first gate structure around a first plurality of semiconductor nanoribbons and a second semiconductor device includes a second gate structure around a second plurality of semiconductor nanoribbons. The first gate structure includes at least a first gate oxide layer and a first gate electrode, and the second gate structure includes at least a second gate oxide layer and a second gate electrode. The first gate oxide layer is thicker than the second gate oxide layer. A high-k dielectric layer may be formed over the first and second gate oxide layers or may be formed over the second gate oxide layer, but not over the first gate oxide layer.

Abstract: Glass layers having partially embedded conductive layers for power delivery in semiconductor packages and related methods are disclosed. An example semiconductor package includes a core layer having a thickness between a first surface opposite a second surface. The core layer includes a trench provided in the first surface. The trench partially extending between the first surface and the second surface. An electrically conductive material is positioned in the trench. A trace is provided on the conductive material. The trace is offset in a direction away from the first surface and away from the second surface of the core layer.

Abstract: Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a plurality of conductive lines along a same direction, one of the conductive lines having a break therein. An inter-layer dielectric (ILD) structure has portions between adjacent ones of the plurality of conductive lines and has a dielectric plug portion in a location of the break in the one of the conductive lines. The dielectric plug portion of the ILD structure is continuous with one or more of the portions of the ILD structure between adjacent ones of the plurality of conductive lines. The dielectric plug portion of the ILD structure has an inwardly tapering profile from top to bottom.

Abstract: The present disclosure is directed to a thermocompression bonding tool having a bond head with a surface for compression and heating and a sensor, a stage for compression and heating, and a controller, and a method for its use for chip gap height and alignment control. For chip gap height and alignment control, the controller is provided with a recipe displacement and temperature profile and measured offsets.

Abstract: A laser transmitter component including a photonic integrated circuit substrate including a plurality of laser transmitters coupled to at least one optical output, and configured to emit a light beam from one of the laser transmitters of the plurality of laser transmitters through the at least one optical output one laser transmitter at a time; a feedback circuit configured to determine at least one characteristic of the light beam emitted from the optical output and to provide the determined characteristic to a controller; and the controller configured to control at least one of a temperature and an input electrical current of the laser transmitter emitting the light beam and to control at least one of a temperature and an input electrical current of at least one further laser transmitter of the laser transmitter component based on the determined characteristic.

Abstract: A user equipment (UE) configured for operation in a fifth-generation new radio (5G NR) network may decode resource configuration information received from a generation Node B (gNB) for Non-Overlapping Sub-Band Full Duplex (NOSB-FD) communication. The resource configuration information may indicate downlink symbols within a carrier bandwidth for downlink communication, uplink symbols within the carrier bandwidth for uplink communication, and NOSB-FD symbols within the carrier bandwidth. Each NOSB-FD symbol may be configurable for both uplink and downlink communication. For any one of the NOSB-FD symbols, one or more uplink subbands within the carrier bandwidth may be configurable to be allocated for uplink communication and one or more downlink subbands of the carrier bandwidth may be configurable to be allocated for downlink communication. The resource configuration information may be determined from a mapping of physical resource blocks (PRBs) to a common resource block (CRB) grid.

Abstract: Examples described herein relate to an Ethernet physical layer transceiver (PHY) circuitry to generate a training signal for transmission for a lane based on a pseudorandom bit sequence (PRBS) polynomial and seed.

Abstract: Structures having vertical shared gate high-drive thin film transistors are described. In an example, an integrated circuit structure includes a stack of alternating dielectric layers and metal layers. A trench is through the stack of alternating dielectric layers and metal layers. A semiconductor channel layer is along sides of the trench. A gate dielectric layer is along sides the semiconductor channel layer in the trench. A gate electrode is within sides of the gate dielectric layer.

Abstract: A user equipment (UE) may determine one or more nominal time-domain windows (TDWs) for demodulation reference signals (DMRS) bundling for physical uplink control channel (PUCCH) transmissions of a PUCCH repetition. A start of a new actual TDW for the DMRS bunding is determined in response to an event which causes power consistency and phase continuity not to be maintained across the PUCCH transmissions of the PUCCH repetition. The UE may maintain power consistency and phase continuity within the new actual TDW across two PUCCH transmissions of the PUCCH repetition. The event may comprise a use of different power control parameters for the two of the PUCCH transmissions of the PUCCH repetition within one of the nominal TDWs.

Abstract: Methods and apparatus relating to techniques for extending I3C capability across multiple platforms and devices over a Universal Serial Bus (USB) type C (USB-C) connection are described. In one embodiment, a first device is coupled to a second device via a first interface and a second interface. The first interface is to communicate low-speed messages and data between the first device and the second device and the second interface is to communicate high-speed data between the first device and the second device. The first device comprises an extension controller to communicatively couple one or more target devices of the first device to one or more target devices of the second device via the first interface. Other embodiments are also claimed and disclosed.

Abstract: According to examples, a memory module with module rows of conductive contacts can enable multiple memory channels to be connected to the same memory module. In one example, a memory module includes a printed circuit board (PCB) having a first face, a second face, and an edge to be received by a connector. The memory module includes a plurality of memory chips on at least one of the first and second faces of the PCB. The memory module includes two or more rows of conductive contacts on each of the first and second faces of the PCB, the two rows including a first row of conductive contacts proximate to the edge of the PCB to be received by the connector, and a second row of conductive contacts between the first row and a second edge of the PCB opposite to the first edge.

Abstract: An integrated circuit structure includes a source or drain region, and a contact for the source or drain region. The contact has (i) an upper portion outside the source or drain region and (ii) a lower portion extending within the source or drain region. For example, the source or drain region wraps around the lower portion of the contact, such that an entire perimeter of the lower portion of the contact is adjacent to the source or drain region.

Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to generate optical flow maps based on foreground and background image segmentation are disclosed. Example apparatus disclosed herein are to generate a reference optical flow map based on a stereo pair of background images corresponding to a first camera field-of-view and a second camera field-of-view, and generate a first optical flow map based on a stereo pair of input images corresponding to the first camera field-of-view and the second camera field-of-view. Disclosed example apparatus are also to combine the reference optical flow map and the first optical flow map based on an alpha matte to generate a second optical flow map associated with the stereo pair of input images, the alpha matte representative of segmentation of at least one of the stereo pair of input images into foreground and background regions.

Abstract: This disclosure describes systems, methods, and devices for signaling multiple modulation and coding schemes for a single user. A device may generate a common field of an ultra-high reliability signal (UHR-SIG) content channel field, the common field including signaling for station devices; generate a number of spatial streams (NSS) subfield of a user specific field of the UHR-SIG content channel field, the user specific field addressed to a first station device of the multiple station devices; generate a 6-bit modulation and coding scheme (MCS) subfield of the user specific field, wherein the 6-bit MCS subfield maps, based on a number of spatial streams signaled by the NSS subfield, to one or more MCSs assigned to the first station device; generate a frame including the UHR-SIG content channel field, wherein a user field of the user specific field includes at least 22 bits including the MCS subfield; and send the frame.

Abstract: An apparatus and method for performing crest factor reduction (CFR). A peak detection circuit detects peaks from input signal samples based on a first threshold. The first threshold is higher than a second threshold that is determined based on a target peak-to-average power ratio (PAPR). A gain computation circuit determines a gain factor for at least one detected peak. A scaled cancellation pulse generation circuit generates a scaled cancellation pulse for the at least one detected peak based on the gain factor. A combiner circuit combines the scaled cancellation pulse with the input signal samples to generate an output signal. A hard clipping circuit may compress the output signal based on the second threshold. The first threshold is set slightly higher than the second threshold.

Abstract: Data integrity logic is executable by a processor to generate a data integrity code using a hardware-based secret. A container manager, executable by the processor, creates a secured container including report generation logic that determines measurements of the secured container, generates a report according to a defined report format, and sends a quote request including the report. The defined report format includes a field to include the measurements and a field to include the data integrity code, and the report format is compatible for consumption by any one of a plurality of different quote creator types.

Abstract: A device for blind spot determination of a second vehicle in a vicinity of a first vehicle includes a processor, configured to determine one or more context variables associated with the second vehicle; modify a model of the second vehicle based on one or more context variables; and determine a probability of the first vehicle being within an area of limited visibility in the modified model.

Abstract: This disclosure describes systems, methods, and devices related to optimized resource technologies. A device may create a Managed Object Instance (MOI) representing actions executed based on artificial intelligence or machine learning (AI/ML) inference function. The device may notify a management and network service (MnS) consumer about the creation of the MOI. The device may execute actions by a network or management function acting as the consumer of the inference output. The device may manage performance of the AI/ML inference function.

Abstract: An apparatus and system for aperiodic sounding reference signals (SRS) transmission are described. Downlink control information (DCI) format 2_3 indicates a Transmission Configuration Indicator (TCI) state for beam indication for transmission of an SRS triggered by the DCI. An explicit field is added to the DCI to indicate the TCI state or the TCI state of the scheduling carrier used to transmit the DCI is used for the SRS. The TCI state indicates a joint uplink/downlink TCI state or a separate uplink or downlink TCI state. The DCI indicates an available slot to use for the SRS explicitly in a DCI field or implicitly based on the component carrier used for transmission of the SRS, the slotOffset parameter, or the first available slot.

Abstract: In various aspects, a device-to-device communication system is provided including a first device and a second device. Each of the first device and the second device includes an antenna, a radio frequency frond-end circuit, and a baseband circuit. Each of the first device and the second device are at least one of a chiplet or a package. The device-to-device communication system further includes a cover structure housing the first device and the second device. Each of the first device and the second device are at least one of a chiplet or a package. The device-to-device communication system further includes a radio frequency signal interface wirelessly communicatively coupling the first device and the second device. The radio frequency signal interface includes the first antenna and the second antenna.

Abstract: Examples described herein relate to a network interface device that includes a programmable event processing architecture that includes a plurality of programmable event processors. In some examples, the plurality of programmable event processors are to perform memory accesses separate from compute operations. In some examples, the plurality of programmable event processors are to group one or more events into at least one group. In some examples, the plurality of programmable event processors are to perform parallel processing of events belonging to different groups. In some examples, the plurality of programmable event processors are programmed to perform at least one transport protocol.

Abstract: In one embodiment, a keyboard includes keys disposed in respective holes of a housing, a set of first conductive pads coupled to respective keys, and a set of second conductive pads coupled to surfaces of the housing defining respective holes. The keys are configured such that the first conductive pad of a key is not in contact with a second conductive pad of a hole corresponding to the key when the key is in a first position (e.g., not actuated), and the first conductive pad of the key is in contact with the second conductive pad of the hole corresponding to the key when the key is in a second position (e.g., actuated).

Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.