Abstract: One embodiment provides a graphics processor including a processing resource including a register file, memory, a cache memory, and load/store/cache circuitry to process load, store, and prefetch messages from the processing resource. The circuitry includes support for an immediate address offset that will be used to adjust the address supplied for a memory access to be requested by the circuitry. Including support for the immediate address offset removes the need to execute additional instructions to adjust the address to be accessed prior to execution of the memory access instruction.

Abstract: Logic may support full power operation for uplink transmissions of user equipment. Logic may identify a codebook entry with a precoding matrix for full power mode operation for an uplink communication for a set of non-coherent or partial coherent antenna ports. Logic may generate the uplink communication, generation to comprise precoding one or more data streams of the uplink communication based on the precoding matrix to associate the data streams with the set of non-coherent or partial coherent antenna ports. And logic may cause transmission of the uplink communication via the interface between processing circuitry and radio frequency circuitry.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to control transactional data. An example apparatus disclosed herein includes memory, machine readable instructions, and processor circuitry to at least one of instantiate or execute the machine readable instructions to populate encrypted input data into a first portion of a data structure, populate an encryption key into a second portion of the data structure, cause the first portion of the data structure to be signed with (a) credentials corresponding to an owner of the encrypted data and (b) credentials corresponding to a transaction host, and store the data structure in a ledger.

Abstract: Prefetch aware LRU cache replacement policy is described. An example of an apparatus includes one or more processors including a graphic processor, the graphics processor including a load store cache having multiple cache lines (CLs), each including bits for a cache line level (CL level) and one or more sectors for data storage; wherein the graphics processor is to receive one or more data elements for storage in the cache; set a CL level to track each CL receiving data, including setting CL level 1 for a CL receiving data in response to a miss in the cache and setting a CL level 2 for a CL receiving prefetched data in response to a prefetch request, and, upon determining that space is required in the cache to store data, apply a cache replacement policy, the policy being based at least in part on set CL levels for the CLs.

Abstract: Methods, apparatus, systems are disclosed for altering displayed content on a display device responsive to a user's proximity. In accord with an example, a computing system includes a display, a sensor to output a signal, machine readable instructions, and programmable circuitry to be programmed in accordance with the instructions to determine a distance between the compute system and a person based on the signal, and cause a size of at least one object to be presented on the display to be adjusted based on the distance.

Abstract: An apparatus to facilitate graphics rendering is disclosed. The apparatus comprises tiling hardware to perform tile based rendering of objects, including receiving a workload comprising a plurality of objects, performing batch formation to generate one or more batches of the plurality of objects, performing super tile fill sequencing for to determine one or more super tiles that are intersected by objects in each batch and compute tile fill intersects for each of the objects and performing a play sequencing of each of the objects, wherein each super tile comprises a plurality of tiles.

Abstract: Disclosed examples include video frame segmenter circuitry to generate segmentation data of first video frame pixel data, the segmentation data including metadata corresponding to a foreground region and a background region, the foreground region corresponding to the first video frame pixel data. The disclosed examples also include video encoder circuitry to generate a first foreground bounding region and a first background bounding region based on the segmentation data, determine a first virtual tile of the first video frame pixel data, the first virtual tile located in the first foreground bounding region, encode the first virtual tile into a video data bitstream without encoding the first background bounding region, and transmit the video data bitstream via a network.

Abstract: A virtual machine (VM) management utility tool may deploy an object model that may persist one or more virtual machine dependencies and relationships. Through a web front-end interface, for example, the VMs may be started in a specific order or re-booted, and the tool automatically determines the additional VMs that need to be re-booted in order to maintain the integrity of the environment. Through the web interface, for example, the object model may be managed and start-up orders or VM dependencies may be updated. For VMs that may not start under load, the object model may block access to the VM until the VM is fully initialized.

Abstract: Systems and methods are provided for harmonizing a foreground region with a background image during background replacement and content editing. A sensor image including a foreground region and a background region is received at an image signal processor (ISP), along with a background image having different visual characteristics. The sensor image and the background image are downscaled and processed by a harmonization neural network that predicts one or more ISP hardware block parameters. The predicted parameters are used to configure ISP hardware blocks such that the foreground region of a processed image is harmonized to match visual characteristics of the background image while preserving full sensor bit depth. The processed image is then blended with the background image to generate a harmonized output image.

Abstract: An apparatus can include radio-frequency transceiver circuitry to transmit and receive radio-frequency signals in a first communications band and in a second communications band. The apparatus can further include a diplexer coupled to the radio-frequency transceiver circuitry. The diplexer can have terminals connected to a first path that conveys the radio-frequency signals in the first communications band and a second path that conveys the radio-frequency signals in the second communications band. The diplexer terminals can also connect to a first switch interposed in the first path and a second switch interposed in the second path.

Abstract: An apparatus, system, and method for multi-frequency oscillator control are provided. A circuit can include a resonator circuit including an input and an output, the resonator circuit configured to resonate at a fundamental frequency and a different, non-fundamental frequency, a startup circuit electrically coupled to the input, the startup circuit configured to generate a signal at about the non-fundamental frequency and detect when the resonator circuit is resonating at the non-fundamental frequency, and an oscillator driver circuit electrically coupled to the output, the oscillator driver circuit configured to amplify and buffer the output of resonator circuit and drive a load.

Abstract: A station (STA) (STA-1) configured for wireless local area network (WLAN) sensing establishes a sensing measurement agreement with another STA STA-2 to perform a sensing measurement setup with the other STA. The sensing measurement setup may comprise an exchange of sensing measurement request and response frames to establish sensing measurement parameters associated with a sensing measurement instance. The Sensing Measurement Setup Request frame and the Sensing Measurement Setup Response frame may be configurable to include a variable length Measurement Sensing Parameters field and a sensing sub-elements field to include one or more of the sensing measurement parameters. The sensing measurement parameters may, for example, comprise one or more of a bandwidth (BW) field, one or more fields for a number of space-time streams (STS) and a number of long-training field (LTF) and LTF repetitions that the STA is capable of transmitting and receiving, and an immediate or delayed feedback reporting field.

Abstract: Gallium nitride (GaN) devices with through-silicon vias for integrated circuit technology are described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, the layer including gallium and nitrogen above a silicon substrate. A backside structure is below the silicon substrate and opposite the layer including gallium and nitrogen, the backside structure including conductive features and dielectric structures. The integrated circuit structure also includes a plurality of through-silicon via power bars having a staggered arrangement, individual ones of the through-silicon via power bars extending through the layer including gallium and nitrogen and through the silicon substrate to a corresponding one of the conductive features of the backside structure, and individual ones of the through-silicon via power bars having a tapered portion coupled to an essentially vertical portion.

Abstract: Systems, apparatuses, and methods include technology that identifies that a first memory cell of a plurality of memory cells stores data that is associated with a multiply-accumulate operation. The plurality of memory cells is associated with a multiply-accumulator (MAC). The technology executes a connection operation to electrically connect the first memory cell to the MAC to execute the multiply-accumulate operation. A second memory cell of the plurality of memory cells is electrically disconnected from the MAC during the multiply-accumulate operation. The technology executes, with the MAC, the multiply-accumulate operation based on the data.

Abstract: Circuit apparatus are disclosed. An example circuit apparatus includes a body including a plurality of first traces formed on the body, and a plurality of openings formed through the body and located between respective ones of the first traces. The openings provide airflow to a fan module of an electronic device through the body of the circuit apparatus.

Abstract: Embodiments are generally directed to sparse 3D convolution acceleration in a convolutional layer of an artificial neural network model. An embodiment of an apparatus includes one or more processors including a graphics processor to process data; and a memory for storage of data, including feature maps. The one or more processors are to provide for sparse 3D convolution acceleration by applying a shared 3D convolutional kernel/filter to an input feature map to produce an output feature map, including increasing sparsity of the input feature map by partitioning it into multiple disjoint input groups; generation of multiple disjoint output groups corresponding to the input groups by performing a convolution calculation represented by the shared 3D convolutional kernel/filter on all feature values associated with active/valid voxels of each input group to produce corresponding feature values within corresponding output groups; and outputting the output feature map by sequentially stacking the output groups.

Abstract: Embodiments described herein may include apparatus, systems, techniques, and/or processes that are directed to performing testing of a device while a system is operational. A device may include computing circuitry and host connectivity registers. Host connectivity registers contain configuration and memory mapping data programmed by system software upon power up of the device and computing system. The data contained in host connectivity registers should be always maintained while the computing system is operational. Scan test circuitry may be implemented, providing the ability to test the device while the system is operational. Preservation circuitry preserves or maintains the data stored in host connectivity registers allowing in-operation testing of the device, ensuring the device the ability to return to full operation at the end of in-operation testing without requiring system software to reprogram the host connectivity registers.

Abstract: An apparatus is described. The apparatus includes a semiconductor chip package assembly having a spring element to be coupled between a first mechanical element and a second mechanical element to apply a loading force that pulls the first and second mechanical elements toward each other in the assembly's nominal assembled state. The first and second elements to support a cooling mass, the assembly further comprising a dampener that is coupled to at least one of the first and second mechanical elements to reduce oscillation amplitude of the cooling mass.

Abstract: This disclosure describes systems, methods, and devices related to clock gating. A device may detect that gating of a local clock of a computer core is enabled; detect, based on the detection that the gating is enabled, that a clock gating condition for the local clock is satisfied; and set a clock gating polarity of the local clock based on the detection that the clock gating condition for the local clock is satisfied.

Abstract: Embodiments disclosed herein include package substrates and methods of forming such package substrates. In an embodiment a package substrate comprises a core with a first surface and a second surface opposite from the first surface. In an embodiment, a buildup layer is over the first surface of the core. In an embodiment, a channel is through the core, where the channel extends in a direction that is substantially parallel to the first surface.

Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component, including an organic dielectric material; a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes metal contacts and a dielectric material between adjacent ones of the metal contacts, and wherein the dielectric material includes an inorganic dielectric material; and a third microelectronic component coupled to the first microelectronic component by wire bonding or solder.

Abstract: Multi-die packages including at least one glass substrate within a space between two adjacent IC dies or surrounding an interconnect bridge die. The various IC dies may be placed within recesses formed in the glass substrate. The IC die and glass substrate, along with any conductive vias extending through the glass substrate may be planarized. The bridge die may be directly bonded or soldered to the adjacent IC dies, providing fine pitch interconnect. The opposite side of the adjacent IC dies and glass substrate may be attached to a host component or may be built up with package dielectric material. Metallization features formed on the second side of the glass substrate may electrically interconnect the IC dies to package interconnect interfaces that may be further coupled to a host with solder interconnects.

Abstract: Embodiments of a microelectronic assembly include: a first integrated circuit (IC) die having a first memory circuit and a second memory circuit; a second IC die; a third IC die; and a package substrate. The first IC die is between the second IC die and the package substrate. The first IC die comprises: a first portion comprising a first active region and a first backend region in contact with the first active region; and a second portion comprising a second active region and a second backend region in contact with the second active region. The first memory circuit is in the first portion, the second memory circuit is in the second portion, the first active region comprises transistors that are larger than transistors in the second active region, and the first backend region comprises conductive traces that have a larger pitch than conductive traces in the second backend region.

Abstract: A method and system of automatically estimating a ball carrier in team sports.

Abstract: Task priority scheduling and resource allocation of autonomous agents are described. The scheduling may utilize sensor data characteristics to facilitate scheduling decisions. Also described is the refinement of task priority scheduling utilizing fleet management information-based scene and environment information, such as by using information available to the fleet management controller.

Abstract: A semiconductor package including: a package substrate including a base die disposed on a top surface of the package substrate, the base die including a plurality of electrical components disposed on a top surface of the base die, the plurality of electrical components including a first electrical component configured adjacent to a second electrical component, wherein the first electrical component and the second electrical component have an asymmetric form-factor; and a stiffener including: a stiffener main portion, wherein the stiffener main portion is affixed to the top surface of the package substrate and configured at least partially surrounding the base die; and a stiffener extension portion configured to extend from the stiffener main portion to be disposed at least partially over the top surface of the base die adjacent to the first electrical component and the second electrical component.

Abstract: Composite IC die package including IC die on both a first and second side of an interposer. The backside of first IC die are attached, for example through a direct bond, to a first side of the interposer. Redistribution layer (RDL) metal features are then fabricated, for example with semi-additive processes (SAP), to form interconnects to the frontside of the first die that terminate at first-level interconnect (FLI) interfaces. The frontside of second IC are attached, for example through a direct bond, to a second side of the interposer. Through vias in the interposer couple the second IC die to the first IC die and/or the FLI interfaces. Through vias of the interposer may be coupled to pillars on the first side of the interposer with the first IC die positioned between the pillars, facilitating power delivery to the second IC die.

Abstract: Examples relate to an apparatus, a device, a method, and a computer program for monitoring one or more software containers being hosted by a computer system, to an apparatus, a device, a method, and a computer program for generating information on an expected behavior of software components of software containers, and to corresponding computer systems. The apparatus for monitoring the one or more software containers comprises processing circuitry configured to determine information on an expected behavior of the one or more software containers based on respective software components being executed or used within the one or more software containers. The processing circuitry is configured to determine information on a monitored behavior of the one or more software containers. The processing circuitry is configured to determine a fault condition of a software container based on a deviation between the expected behavior of the software container and the monitored behavior of the software container.

Abstract: A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

Abstract: Systems, methods, and apparatuses relating to an instruction that allows a trusted execution environment to react to an asynchronous exit are described. In one embodiment, a hardware processor includes a register comprising a field, that when set, is to enable an architecturally protected execution environment for code in an architecturally protected enclave in memory, a decoder circuit to decode a single instruction comprising an opcode into a decoded instruction, the opcode to indicate an execution circuit is to invoke a handler to handle an asynchronous exit from execution of the code in the architecturally protected enclave and then resume execution of the code in the architecturally protected enclave from where the asynchronous exit occurred, and the execution circuit to respond to the decoded instruction as specified by the opcode.

Abstract: Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to integrated circuits with self-aligned tub architectures. Other embodiments may be described or claimed.

Abstract: An apparatus and method for merging primitives and coordinating between vertex and ray transformations on a shared transformation unit. For example, one embodiment of a graphics processor comprises: a queue comprising a plurality of entries; ordering circuitry/logic to order triangles front to back within the queue; pairing circuitry/logic to identify triangles in the queue sharing an edge and to merge the triangles sharing an edge to produce merged triangle pairs; and shared transformation circuitry to alternate between performing vertex transformations on vertices of the merged triangle pairs and to performing ray transformations on ray direction/origin data.

Abstract: Systems and methods for tuning hyperparameters of a model includes: receiving a multi-criteria tuning work request for tuning hyperparameters of the model of the subscriber to the remote tuning service, wherein the multi-criteria tuning work request includes: a first objective function of the model to be optimized by the remote tuning service; a second objective function to be optimized by the remote tuning service, the second objective function being distinct from the first objective function; computing a joint tuning func-tion based on a combination of the first objective function and the second objective function; executing a tuning opera-tion of the hyperparameters for the model based on a tuning of the joint function; and identifying one or more proposed hyperparameter values based on one or more hyperparam-eter-based points along a convex Pareto optimal curve.

Abstract: Embodiments of systems, apparatuses, and methods for chained fused multiply add. In some embodiments, an apparatus includes a decoder to decode a single instruction having an opcode, a destination field representing a destination operand, a first source field representing a plurality of packed data source operands of a first type that have packed data elements of a first size, a second source field representing a plurality of packed data source operands that have packed data elements of a second size, and a field for a memory location that stores a scalar value. A register file having a plurality of packed data registers includes registers for the plurality of packed data source operands that have packed data elements of a first size, the source operands that have packed data elements of a second size, and the destination operand.

Abstract: Embodiments are generally directed to methods and apparatuses for dynamically changing data priority in a cache. An embodiment of an apparatus comprising: a priority controller to: receive a memory access request to request data; and set a priority flag for the memory access request based on an accumulated access amount of data stored in a memory block to be accessed by the memory access request to dynamically change a priority level of the requested data.

Abstract: One-time programmable (OTP) bit-cell for an integrated circuit (IC) that includes an OTP element, such as a fuse or antifuse, coupled in electrical series with a selector that comprises a Schottky junction. The selector may comprise a metal-semiconductor-metal (MSM) material stack operable as transient voltage suppression (TVS) device that experiences electrical breakdown at a voltage below a programming voltage of the OTP element. In response to a programming voltage, the MSM stack may breakdown and pass a transient current sufficient for programming the OTP element. In response to a lower (e.g., read) voltage, the MSM stack may breakdown and pass a transient current insufficient for programming, but sufficient to sense a state of the OTP element. In response to an even lower (e.g., half-read) voltage, the MSM stack may present a very high OTP bit-cell input impedance, reducing leakage and/or sneak path currents within an array of such bit-cells.

Abstract: Variations in a thermal structure for an open cavity photonic integrated circuit (OCPIC) having an MRR. The structure includes an air trench in fluid communication with an air cavity that is located under the MRR. The air trench is a gap/opening in the oxide that encircles at least a portion of the MRR and extends outward radially therefrom, with a consistent width, to a diameter D1. An oxide cladding is not removed in areas that are used for metal traces and routing. The structure is characterized by straight walls along the air trench. The structure has a lower diameter D2, measured at a bottom/floor of the air cavity. In various embodiments, D2 is substantially equal to D1.

Abstract: An access point (AP) station (STA) configured for communicating with another STA within a synchronized transmission opportunity (S-TXOP) may encode an S-TXOP trigger for transmission at a beginning of the S-TXOP. The S-TXOP trigger may be followed by a plurality of slots within the S-TXOP. The S-TXOP trigger may include a synchronization information field, a station information list field and an optional schedule information field. The STA information list field may include an AID of each STA that is scheduled to communicate during the slots and an indication of whether semi-static configuration is enabled. When the S-TXOP trigger includes the optional schedule information field, it may include resource information for each slot which may include a slot identifier and a slot type indicator. The resource allocation for each slot further includes a scheduling information element when the semi-static configuration for the corresponding slot is not enabled.

Abstract: Various embodiments herein provide techniques related to sidelink relay enhancements in a cellular network. In some embodiments, a UE may include circuitry configured to identify, from a gNodeB (gNB) of a serving cell to which the UE and one or more relay UEs belong, a medium access control (MAC) control element (CE); and identifying, based on the MAC CE, that the UE is to communicate with the gNB via multipath communication. Other embodiments may be described and/or claimed.

Abstract: Apparatuses, methods, and systems for dynamic resource allocation based on quality-of-service prediction are disclosed. In embodiments, an apparatus includes quality-of-service prediction circuitry and a resource controller. The quality-of-service prediction circuitry is to make quality-of-service predictions using a model based at least in part on at least one performance counter measurements and at least one quality-of-service measurement. The resource controller is to allocate one or more shared resources based on the quality-of-service predictions and architectural performance counter measurements.

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a package substrate, and a die on the package substrate. In an embodiment, the electronic package further comprises a voltage regulator on the package substrate adjacent to the die, and a metal printed circuit board (PCB) heat spreader. In an embodiment, a trace on the metal PCB heat spreader couples the die to the voltage regulator.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to generate binaural sounds for hearing devices. An example apparatus includes processor circuitry to at least access audio data corresponding to multiple devices, ones of the multiple devices positioned at spatial locations relative to a listener, identify a position of the listener relative to the multiple devices, adjust, based on the spatial locations and the position of the listener, the audio data associated with at least one of the multiple devices, transmit the adjusted audio data to a hearing device associated with the listener, the adjusted audio data including a binaural sound corresponding to each of the spatial locations.

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a photonic die and at least one optical fiber. Devices and methods are shown that include an optical coupler and one or more correction regions to align a beam between the photonic die and the optical fiber.

Abstract: In one embodiment, an apparatus couples to a host processor over a Compute Express Link (CXL)-based link. The apparatus includes a transaction queue to queue memory transactions to be completed in an addressable memory coupled to the apparatus, a transaction cache, conflict detection circuitry to determine whether a conflict exists between memory transactions, and transaction execution circuitry. The transaction execution circuitry may access a transaction from the transaction queue, the transaction to implement one or more memory operations in the memory, store data from the memory to be accessed by the transaction operations in the transaction cache, execute operations of the transaction, including modifying data from the memory location stored in the transaction cache, and based on completion of the transaction, cause the modified data from the transaction cache to be stored in the memory.

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a vertical stack of semiconductor channels, a source on a first side of the vertical stack of semiconductor channels, and a drain on a second side of the vertical stack of semiconductor channels, In an embodiment, a metal is below the source and in direct contact with the source, where a centerline of the metal is substantially aligned with a centerline of the source.

Abstract: A computing platform comprising a plurality of disaggregated data center resources and an infrastructure processing unit (IPU), communicatively coupled to the plurality of resources, to compose a platform of the plurality of disaggregated data center resources for allocation of microservices cluster.

Abstract: A device includes physical layer (PHY) circuitry including a physical coding sublayer, where the PHY circuitry is configured to alternatively support at least two different power control settings. The device further includes an interface to couple the PHY circuitry to a media access control (MAC) layer, where the interface comprises a set of data pins, a set of command pins, a set of status pins, one or more clock pins, and a plurality of power control pins to receive an indication of a particular one of the at least two power control settings. The PHY circuitry is to apply parameters corresponding to the particular control setting during operation based on the indication.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed. An example apparatus includes: An apparatus comprising: at least one memory; instructions; and processor circuitry to execute the instructions to: processor circuitry to execute the instructions to: identify a word in an image, the word to be converted to an audio waveform; encode the word identified in the image into an ordered list of phonemes; and synthesize the audio waveform of the word based on an output of a neural network that determines a duration that a phoneme of the ordered list of phonemes is to be expressed in the audio waveform.

Abstract: An adaptive quantization system and method for efficient storage and processing of matrix data is disclosed. The system comprises a processor with circuitry configured to divide a matrix into blocks, assign quantization formats to each block based on content, generate a super-block comprising quantized blocks and associated format information, and store the super-block in memory. The method employs an index to indicate quantization formats, typically using 3 bits per block, and can utilize shared exponents for certain formats. A metadata buffer stores compression information, allowing gradual adoption of compression. The invention optimizes matrix data storage at a fine-grained level, maintains efficient random access, adapts to varying precision requirements within a matrix, and integrates with existing memory hierarchies.

Abstract: A processing system for distributing work in a computing environment arranges nodes in a network topology. Each node comprises upstream and downstream ports for receiving and sending packets, and ingress or egress ports for accepting new entries or forwarding packets to functional units. Nodes evaluate received packets for local processing, removing them for processing or forwarding to the next node. The system implements flow control at ingress ports, arbitrates between multiple ingress ports when the upstream port is idle, and distributes work locally to connected egress ports. Packets are inspected to determine suitability for processing by connected functional units. This efficient system enables flexible work distribution strategies in homogeneous and heterogeneous networks, reducing the need for repeaters and long wires on integrated circuits.