Intel Patents

Intel Corporation designs and manufactures microprocessors and chipsets for computing and communications equipment manufacturers. Its products may be found in desktops, servers, tablets, smartphones and other devices.

Intel Patents by Type

  • Intel Patents Granted: Intel patents that have been granted by the United States Patent and Trademark Office (USPTO).
  • Intel Patent Applications: Intel patent applications that are pending before the United States Patent and Trademark Office (USPTO).
  • Publication number: 20190021165
    Abstract: An apparatus comprising includes a first pair of conductors to carry differential signals, at least one ground conductor neighboring the first pair of conductors, the ground conductor to be connected to a ground plane, and at least one particular conductor to carry sideband signals. The particular conductor is to be connected to a ground plane via a resonance mitigation circuit, and the resonance mitigation circuit comprises a resistor.
    Type: Application
    Filed: May 14, 2018
    Publication date: January 17, 2019
    Applicant: Intel Corporation
    Inventors: Timothy D. Wig, Steven K. Krooswyk, Marc Wells
  • Publication number: 20190020451
    Abstract: The present disclosure includes systems and methods for reducing intra-cell interference during uplink MU-MIMO. An uplink grant that allocates a plurality of resource blocks is obtained. A first portion of the plurality of RBs that are overlapping with a set of RBs granted to a second UE is determined. A second portion of the plurality of RBs that are non-overlapping with the set of RBs granted to the second UE is also determined. A first demodulation reference signal (DMRS) sequence is generated for the first portion of the plurality of RBs. A second DMRS sequence is generated for the second portion of the plurality of RBs, where the second DMRS sequence is different than the first DMRS sequence. An uplink transmission (e.g., PUCCH, PUSCH) is generated that includes RBs having different DMRS sequences.
    Type: Application
    Filed: March 30, 2016
    Publication date: January 17, 2019
    Applicant: INTEL CORPORATION
    Inventors: Yushu Zhang, Yuan Y. Zhu, Wenting Chang, Xiogang C. Chen, Qinghua Li
  • Publication number: 20190021100
    Abstract: Techniques disclosed for accurately predicting the occurrence of anomalous sensor readings within a sensor network and advantageously using these predictions to limit the amount of power used by relay nodes within the sensor network. Some examples analyze spatial and temporal characteristics of anomalous sensor readings to predict future occurrences. In these examples, the relay nodes operate in a reduced power mode for periods of time in which anomalous sensor readings are not predicted to occur. Also, in these examples, only relay nodes in a path between a sensor predicting an anomalous reading and a gateway of the sensor network operate in full power mode. This feature allows other relay nodes to remain in the reduced power mode even when an anomalous sensor reading is predicted elsewhere in the sensor network.
    Type: Application
    Filed: July 11, 2017
    Publication date: January 17, 2019
    Applicant: INTEL CORPORATION
    Inventors: Venkataranan Natarajan, Apoorv Vyas, Jaroslaw J. Sydir, Kumar Ranganathan
  • Publication number: 20190021105
    Abstract: Technology for a user equipment (UE) operable to process scheduled uplink (UL) transmissions is disclosed. The UE can process one or more uplink (UL) grants received from an eNodeB on a downlink (DL) subframe in a first transmission opportunity (TxOP). The UE can determine, based on the one or more UL grants, one or more UL subframes in at least one subsequent TxOP for an UL transmission from the UE. The UE can process the UL transmission for communication on the one or more UL subframes in the at least one subsequent TxOP.
    Type: Application
    Filed: October 28, 2016
    Publication date: January 17, 2019
    Applicant: Intel IP Corporation
    Inventors: Fatemeh HAMIDI-SEPEHR, Jeongho JEON, Qiaoyang YE, Abhijeet BHORKAR, Hwan-Joon KWON, Huaning NIU, Seok Chul KWON
  • Publication number: 20190015019
    Abstract: Embodiments of the disclosure are directed to systems, methods, and devices for monitoring inertial data from a player swinging a piece of sports equipment. In embodiments, a monitoring device for monitoring swing metrics. The monitoring device includes an inertial measurement unit (IMU) implemented at least partially in hardware to sense inertial data corresponding to a swing of a piece of sports equipment; a processor implemented at least partially in hardware to extrapolate, based on the inertial data, one or more swing parameters associated with the swing of the piece of sports equipment; and a transceiver implemented at least partially in hardware to transmit the one or more swing parameters to a remote device across a wireless connection.
    Type: Application
    Filed: December 22, 2015
    Publication date: January 17, 2019
    Applicant: Intel Corporation
    Inventors: James Brian Hall, Tyler Fetters, Stephanie Moyerman, Jeffrey Mitsuo Ota, Narayan Sundararajan
  • Publication number: 20190021026
    Abstract: Uplink (UL) data splits between LTE and WLAN can be go supported in cellular networks. The split can be UE controlled or network controlled. Both UE and network controlled bearer split architectures can be supported. The reporting of Uplink Buffer Status (BSR) and the subsequent data allocation can depend on what option is supported by the network. For UE controlled UL data splits, the UE determines a traffic split ratio between LTE and WLAN. The split can be based on local link conditions. For network controlled UL data splits, the network (e.g. a Link Aggregation Scheduler at the eNB) is responsible for making bearer split decisions. The decisions can be based on link qualities, available traffic and quality of service (QoS) requirements of associated users. The split can be based on a per bearer threshold, an eNB configured ratio, or an implicit inference based on a UL grant.
    Type: Application
    Filed: June 27, 2016
    Publication date: January 17, 2019
    Applicant: INTEL IP CORPORATION
    Inventors: Shadi Iskander, Nageen Himayat, Candy Yiu, Alexander Sirotkin, Jerome Parron, Ofer Hareuveni, Umesh Phuyal, Penny Efraim-Sagi
  • Publication number: 20190019793
    Abstract: One embodiment provides an apparatus. The apparatus includes a first transistor and a second transistor. The first transistor includes a first drain, a first source coupled to the first drain by a first channel, and a first gate stack comprising a plurality of layers. The second transistor includes a second drain, a second source coupled to the second drain by a second channel, and a second gate stack comprising a plurality of layers. Each gate stack includes a work function material layer to optimize a threshold voltage variation between the transistors.
    Type: Application
    Filed: April 1, 2016
    Publication date: January 17, 2019
    Applicant: INTEL CORPORATION
    Inventors: Daniel H, MORRIS, Uygar E. AVCI, Ian A. YOUNG
  • Publication number: 20190018813
    Abstract: A shared memory controller receives, from a computing node, a request associated with a memory transaction involving a particular line in a memory pool. The request includes a node address according to an address map of the computing node. An address translation structure is used to translate the first address into a corresponding second address according to a global address map for the memory pool, and the shared memory controller determines that a particular one of a plurality of shared memory controllers is associated with the second address in the global address map and causes the particular shared memory controller to handle the request.
    Type: Application
    Filed: April 9, 2018
    Publication date: January 17, 2019
    Applicant: Intel Corporation
    Inventor: Debendra Das Sharma
  • Publication number: 20190021053
    Abstract: This disclosure describes frame structures and layer one (L1) procedures suitable for Xu air interfaces. Features of the design are designed for energy-efficient operation and to meet other performance specifications and characteristics of ultra-dense user equipment deployments.
    Type: Application
    Filed: June 27, 2016
    Publication date: January 17, 2019
    Applicant: INTEL IP CORPORATION
    Inventors: Qian Li, Guangjie Li, Xiaoyun May Wu, Geng Wu
  • Publication number: 20190018806
    Abstract: Techniques and apparatus to manage access to accelerator-attached memory are described. In one embodiment, an apparatus to provide coherence bias for accessing accelerator memory may include at least one processor, a logic device communicatively coupled to the at least one processor, a logic device memory communicatively coupled to the logic device, and logic, at least a portion comprised in hardware, the logic to receive a request to access the logic device memory from the logic device, determine a bias mode associated with the request, and provide the logic device with access to the logic device memory via a device bias pathway responsive to the bias mode being a device bias mode. Other embodiments are described and claimed.
    Type: Application
    Filed: July 14, 2017
    Publication date: January 17, 2019
    Applicant: INTEL CORPORATION
    Inventors: DAVID A. KOUFATY, RAJESH M. SANKARAN, STEPHEN R. VAN DOREN
  • Publication number: 20190018802
    Abstract: In one example a Universal Serial Bus (USB) controller comprises at least one memory register to store one or more enumeration parameters for a USB connection with the USB controller and logic, at least partially including hardware logic, to detect a USB connection with a remote device via the USB connection, retrieve one or more connection enumeration parameters for the USB connection from the at least one memory register on the USB host controller, and implement a connection enumeration process using the one or more connection enumeration parameters retrieved from the memory register on the USB controller. Other examples may be described.
    Type: Application
    Filed: April 17, 2018
    Publication date: January 17, 2019
    Applicant: Intel Corporation
    Inventors: SATHEESH CHELLAPPAN, KISHORE KASICHAINULA, LAY CHENG ONG, CHEE LIM POON, HARISH G. KAMAT
  • Patent number: 10179729
    Abstract: Embodiments of the invention describe hermetic encapsulation for MEMS devices, and processes to create the hermetic encapsulation structure. Embodiments comprise a MEMS substrate stack that further includes a magnet, a first laminate organic dielectric film, a first hermetic coating disposed over the magnet, a second laminate organic dielectric film disposed on the hermetic coating, a MEMS device layer disposed over the magnet, and a plurality of metal interconnects surrounding the MEMS device layer. A hermetic plate is subsequently bonded to the MEMS substrate stack and disposed over the formed MEMS device layer to at least partially form a hermetically encapsulated cavity surrounding the MEMS device layer. In various embodiments, the hermetically encapsulated cavity is further formed from the first hermetic coating, and at least one of the set of metal interconnects, or a second hermetic coating deposited onto the set of metal interconnects.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: January 15, 2019
    Assignee: Intel Corporation
    Inventors: Sarah K. Haney, Weng Hong Teh, Feras Eid, Sasha N. Oster
  • Patent number: 10180800
    Abstract: Systems, apparatuses and methods may include technology that detects a migration request and conducts a first transfer, via a trusted execution environment (TEE), of storage context information from a first removable storage device to a secure memory region of a system in response to the data migration request. Additionally, the technology may conduct a second transfer, via the TEE, of the storage context information from the secure memory region to a second removable storage device, wherein the storage context information includes factory data, security data and boot firmware.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: January 15, 2019
    Assignee: Intel Corporation
    Inventors: Karunakara Kotary, Krishna Kumar Ganesan, Vincent J. Zimmer
  • Patent number: 10180911
    Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: January 15, 2019
    Assignee: Intel Corporation
    Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Richard Uhlig, Scott Dion Rodgers, Rajesh M. Sankaran, Camron Rust, Sebastian Schoenberg
  • Patent number: 10180710
    Abstract: Apparatuses, methods and storage media associated with a plurality of cooling devices thermally coupled to a plurality of heat-generating components of an electronic device, such as a server, a configured rack of servers, or a configured rack of server elements, are disclosed herein. Each cooling device may be associated with a unique cooling zone for the components. Logic may be coupled with the plurality of cooling devices, and the logic may be configured to cause a first cooling zone of a first cooling device to overlap a second cooling zone of a second cooling device. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: January 15, 2019
    Assignee: Intel Corporation
    Inventors: Yanbing Sun, Yongkang Wu, Jeff King, Peifeng Si
  • Patent number: 10178969
    Abstract: Embodiments of the present disclosure provide techniques and configurations for an apparatus for stress event detection. In some embodiments, the apparatus may be a wearable device and may include at least one first sensor disposed on the wearable apparatus to generate a first sensor signal indicative of a brain activity of a user, at least one second sensor disposed on the wearable apparatus to generate a second sensor signal indicative of a heart rate of the user, and at least one third sensor disposed on the wearable apparatus to generate a third sensor signal indicative of a respiration rate of the user. The apparatus may further include a controller coupled with the at least first, second, and third sensors, to detect a stress event for the user, based at least in part on the first, second, and third sensor signals. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: January 15, 2019
    Assignee: Intel Corporation
    Inventors: Naghma Anwar, Indira Negi, Vivek K. Menon, Michael R. Rosen, Donald L. Gross, Ling Wang, Shea M. Dillon, Stephen C. Fenwick, Tom L. Simmons, Robert M. Negron
  • Patent number: 10180797
    Abstract: Provided are a computer program product, system and method for determining adjustments to the spare space in a storage device unavailable to a user based on a current consumption profile of a storage device. A current write amplification is based on storage writes to a media at a storage device and host writes from a host to the storage device. An adjustment to the current write amplification is determined to produce an adjusted write amplification based on an estimated lifespan of the storage device, a maximum storage writes for the storage device, and the storage writes at the storage device since the storage device was powered-on. A determination is made to an adjustment to spare space based on the adjusted write amplification. The spare space and the free space available to the user are reconfigured to adjust the spare space by the determined adjustment to the spare space.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: January 15, 2019
    Assignee: INTEL CORPORATION
    Inventor: Knut S. Grimsrud
  • Patent number: 10180782
    Abstract: A specified object in still images or video may be detected using a sliding search window technique, applied to the original image and its downscaled versions, in order to detect objects of different sizes. At each scale and each position of the sliding window, the technique may use a boosted tree classifier to determine whether the window contains the object. It may exit earlier if some intermediate sum falls below the certain threshold. To accelerate object detection, hybrid features are used in different boosted chains. For first boosted chains, the fastest features may be applied and then, after more complex (but slower) features and for the last few chains, the most powerful feature (but most computationally expensive) is used. This strategy may improve the speed of detection because for a majority of checking windows, only first boosted chains are used and so only the fastest features are calculated in some embodiments.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: January 15, 2019
    Assignee: Intel Corporation
    Inventors: Alexander Bovyrin, Vadim Pisarevsky, Irina Kostina
  • Patent number: 10180838
    Abstract: A processor fetches a multi-register gather instruction that includes a destination operand that specifies a destination vector register, and a source operand that identifies content that indicates multiple vector registers, a first set of indexes of each of the vector registers that each identifies a source data element, and a second set of indexes of the destination vector register for each identified source element. The instruction is decoded and executed, causing, for each of the first set of indexes of each of the vector registers, the source data element that corresponds to that index of that vector register to be stored in a set of destination data elements that correspond to the second set of identified indexes of the destination vector register for that source data element.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: January 15, 2019
    Assignee: Intel Corporation
    Inventor: Ashish Jha
  • Patent number: 10181329
    Abstract: An audio processing device includes a first microphone configured to receive a first signal a second microphone configured to receive a second signal, a noise reduction gain determination circuit configured to determine a noise reduction gain based on the first signal and the second signal, a noise reduction circuit configured to attenuate the first signal based on the determined noise reduction gain, and an output circuit configured to output the attenuated signal.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: January 15, 2019
    Assignee: Intel IP Corporation
    Inventors: Ludovick Lepauloux, Fabrice Plante, Christophe Beaugeant
  • Patent number: 10180928
    Abstract: Heterogeneous hardware accelerator architectures for processing sparse matrix data having skewed non-zero distributions are described. An accelerator includes sparse tiles to access data from a first memory over a high bandwidth interface and very/hyper sparse tiles to randomly access data from a second memory over a low-latency interface. The accelerator determines that one or more computational tasks involving a matrix are to be performed, partitions the matrix into a first plurality of blocks that includes one or more sparse sections of the matrix, and a second plurality of blocks that includes sections of the matrix that are very- or hyper-sparse. The accelerator causes the sparse tile(s) to perform one or more matrix operations for the computational task(s) using the first plurality of blocks and further causes the very/hyper sparse tile(s) to perform the one or more matrix operations for the computational task(s) using the second plurality of blocks.
    Type: Grant
    Filed: December 31, 2016
    Date of Patent: January 15, 2019
    Assignee: Intel Corporation
    Inventors: Eriko Nurvitadhi, Deborah Marr
  • Patent number: 10180856
    Abstract: A method for performing dynamic port remapping during instruction scheduling in an out of order microprocessor is disclosed. The method comprises selecting and dispatching a plurality of instructions from a plurality of select ports in a scheduler module in first clock cycle. Next, it comprises determining if a first physical register file unit has capacity to support instructions dispatched in the first clock cycle. Further, it comprises supplying a response back to logic circuitry between the plurality of select ports and a plurality of execution ports, wherein the logic circuitry is operable to re-map select ports in the scheduler module to execution ports based on the response. Finally, responsive to a determination that the first physical register file unit is full, the method comprises re-mapping at least one select port connecting with an execution unit in the first physical register file unit to a second physical register file unit.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: January 15, 2019
    Assignee: INTEL CORPORATION
    Inventor: Nelson N. Chan
  • Patent number: 10181117
    Abstract: Logic to register a personal point of sale (POS) device. Logic may communicate with the registration processor to establish a secure communication channel. Logic may access a basic input output system to obtain platform information. Logic may transmit the platform information to the registration processor to identify a certification associated with the device. Logic may communicate with a payment instrument via a card reader. Logic may transmit an encrypted message from the card reader to the registration processor to bind the payment instrument to the device. Logic may receive a communication from the device comprising platform information. Logic may perform a security protocol to establish a secure communication channel with the device. Logic may determine an existence of the certification for the device in the database based upon the platform information. And logic may register the platform in response to locating the certification of the platform.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: January 15, 2019
    Assignee: INTEL CORPORATION
    Inventors: Farid Adrangi, Sanjay Bakshi, Amit S. Bodas
  • Patent number: 10181518
    Abstract: A first III-V material based buffer layer is deposited on a silicon substrate. A second III-V material based buffer layer is deposited onto the first III-V material based buffer layer. A III-V material based device channel layer is deposited on the second III-V material based buffer layer.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: January 15, 2019
    Assignee: Intel Corporation
    Inventors: Niti Goel, Gilbert Dewey, Niloy Mukherjee, Matthew V. Metz, Marko Radosavljevic, Benjamin Chu-Kung, Jack T. Kavalieros, Robert S. Chau
  • Patent number: 10181001
    Abstract: A compensating initialization module may be automatically inserted into a design to compensate for register retiming which changes the designs behavior under reset. The device configuration circuitry may provide an adjustment sequence length as well as a start signal to the initialization module to properly reset the retimed user logic implemented on the integrated circuit after initial configuration and unfreezing of the integrated circuit. The auto initialization module may control the c-cycle initialization process and indicate to the user logic when c-cycle initialization has completed. The user logic may subsequently begin a user-specified reset sequence. When the user-specified reset sequence ends, the user logic implemented on the integrated circuit may begin normal operations. Additionally, a user reset request may also trigger the auto initialization module to begin a reset process.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: January 15, 2019
    Assignee: Intel Corporation
    Inventors: Sean R. Atsatt, Mahesh A. Iyer
  • Patent number: 10181456
    Abstract: A multi-package integrated circuit assembly can include a first electronic package having a first package substrate including a first die side and a first interface side. A first die can be electrically coupled to the first die side. A second electronic package can include a second package substrate having a second die side and a second interface side. A second die can be electrically coupled to the second die side. A conductive interconnect can be electrically coupled from the interface side of the first package substrate to the interface side of the second package substrate. A collective substrate can be attached to the first electronic package. For instance, the collective substrate can be located on a face of the first electronic package opposing the first package substrate. The collective substrate is electrically coupled to the first die and the second die through the first package substrate.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: January 15, 2019
    Assignee: Intel Corporation
    Inventor: Hyoung Il Kim
  • Patent number: 10181682
    Abstract: Particular embodiments described herein provide for a connector shield that can include a main body, a shield portion to shield electromagnetic radiation from a connector, and a support portion. The main body can be removably secured to the connector. The shield portion includes lossy material and the shield portion is not grounded. The connector can include connection lines and the connection lines are at least partially inside a cavity of the shield portion.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: January 15, 2019
    Assignee: Intel Corporation
    Inventors: Jaejin Lee, Hao-Han Hsu
  • Patent number: 10180854
    Abstract: A processing system includes an execution unit, communicatively coupled to an architecturally-protected memory, the execution unit comprising a logic circuit to execute a virtual machine monitor (VMM) that supports a virtual machine (VM) comprising a guest operating system (OS) and to implement an architecturally-protected execution environment, wherein the logic circuit is to responsive to executing a blocking instruction by the guest OS directed at a first page stored in the architecturally-protected memory during a first time period identified by a value stored in a first counter, copy the value from the first counter to a second counter, responsive to executing a first tracking instruction issued by the VMM, increment the value stored in the first counter, and set a flag to indicate successful execution of the second tracking instruction.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: January 15, 2019
    Assignee: Intel Corporation
    Inventors: Rebekah M. Leslie-Hurd, Carlos V. Rozas, Dror Caspi
  • Patent number: 10181027
    Abstract: Embodiments of an invention for an interface between a device and a secure processing environment are disclosed. In one embodiment, a system includes a processor, a device, and an interface plug-in. The processor includes an instruction unit and an execution unit. The instruction unit is to receive an instruction to create a secure processing environment. The execution unit is to execute an application in the secure processing environment. The device is to execute a workload for the application. The interface plug-in is to provide an interface for the device to enter the secure processing environment to execute the workload.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: January 15, 2019
    Assignee: Intel Corporation
    Inventors: Alpa Narendra Trivedi, Siddhartha Chhabra, Xiaozhu Kang, Prashant Dewan, Uday Savagaonkar, David Durham
  • Patent number: 10180903
    Abstract: Embodiments of the invention relate a hybrid hardware and software implementation of transactional memory accesses in a computer system. A processor including a transactional cache and a regular cache is utilized in a computer system that includes a policy manager to select one of a first mode (a hardware mode) or a second mode (a software mode) to implement transactional memory accesses. In the hardware mode the transactional cache is utilized to perform read and write memory operations and in the software mode the regular cache is utilized to perform read and write memory operations.
    Type: Grant
    Filed: April 1, 2017
    Date of Patent: January 15, 2019
    Assignee: INTEL CORPORATION
    Inventors: Sanjeev Kumar, Christopher J. Hughes, Partha Kundu, Anthony Nguyen
  • Patent number: 10181432
    Abstract: Embodiments of the present disclosure provide techniques and configurations for a computing system with a thermal interface having magnetic particles. In some embodiments, the computing system may include a first part, a second part, and a thermal interface to couple the first and second parts. The thermal interface may comprise a thermal interface material having magnetic particles that are aligned in a defined direction relative to a surface of the first or second part, to provide desired thermal conductivity between the first and second parts. The defined direction of alignment of magnetic particles may comprise an alignment of the particles substantially perpendicularly to the surface of the first or second part. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: January 15, 2019
    Assignee: Intel Corporation
    Inventors: Ameya Limaye, Shubhada H. Sahasrabudhe, Nachiket R. Raravikar
  • Patent number: 10180927
    Abstract: A device to process data packets for communication across PHY layers which are of different respective communication protocols. In an embodiment, the device includes a first protocol stack and a second protocol stack which are each for a PCIe™ communication protocol. The first protocol stack and a second protocol stack may interface, respectively, with a first physical (PHY) layer and a second PHY layer of the device. The first protocol stack and the second protocol stack may exchange packets to facilitate communications via both the first PHY layer and the second PHY layer. In another embodiment, the first PHY layer is for communication according to the PCIe™ communication protocol and the second PHY layer is for communication according to another, comparatively low power communication protocol.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: January 15, 2019
    Assignee: Intel Corporation
    Inventors: Akshay G. Pethe, Mahesh Wagh, Manjari Kulkarni
  • Patent number: 10181856
    Abstract: A Digital Phase Locked Loop (DPLL), including a Time-to-Digital Converter (TDC) configured generate quantized phase values of a Voltage Controlled Oscillator (VCO) signal; and a frequency estimation circuit configured to receive the quantized phase values, determine wraparound phase of the quantized phase values, and least-squares estimate a frequency based on the quantized phase values and the wraparound phase.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: January 15, 2019
    Assignee: Intel IP Corporation
    Inventors: Elan Banin, Roy Amel, Ran Shimon, Ashoke Ravi, Nati Dinur
  • Patent number: 10181171
    Abstract: A technique to share execution resources. In one embodiment, a CPU and a GPU share resources according to workload, power considerations, or available resources by scheduling or transferring instructions and information between the CPU and GPU.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: January 15, 2019
    Assignee: Intel Corporation
    Inventors: Eric Sprangle, Matt Craighead, Chris Goodman, Belliappa Kuttanna
  • Patent number: 10181886
    Abstract: Some demonstrative embodiments include devices, systems and/or methods of wireless communication via multiple antenna assemblies. For example, a device may include a wireless communication unit to transmit and receive signals via one or more quasi-omnidirectional antenna assemblies, wherein the wireless communication unit is to transmit, via each quasi-omnidirectional antenna assembly, a plurality of first transmissions, to receive, in response to the first transmissions, a plurality of second transmissions from another device via one or more of the quasi-omnidirectional antenna assemblies, and, based on the second transmissions, to select at least one selected transmit antenna assembly for transmitting to the other device and a selected receive antenna assembly for receiving transmissions from the other device. Other embodiments are described and claimed.
    Type: Grant
    Filed: January 7, 2018
    Date of Patent: January 15, 2019
    Assignee: INTEL CORPORATION
    Inventors: Menashe Soffer, Assaf Kasher
  • Patent number: 10181052
    Abstract: Technologies for informing a remote user of a local user's availability to receive a contact on a communication device are disclosed. The availability of the local user may be determined based on the local user's context information, which may be reported to the remote user in response to a contact status request. The local user's context information provided to the remote user may inform, for example, whether the local user is available to receive a contact, the best way to contact the local user, and/or other context information of the local user. The type and/or level of specificity of the local user's context information reported to the remote user may be determined based on a privacy level, which may be determined based on the local user's context, the identity of the remote user, and/or other criteria. In some embodiments, contact status updates may be provided to the remote user.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: January 15, 2019
    Assignee: Intel Corporation
    Inventors: Hong Li, Sharad K. Garg, Mark D. Yarvis, Joshua Boelter
  • Patent number: 10182245
    Abstract: Techniques related to quality restoration filtering for video coding are described.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: January 15, 2019
    Assignee: Intel Corporation
    Inventors: Atul Puri, Daniel Socek
  • Patent number: 10181073
    Abstract: Technologies for efficient identity recognition based on skin features include a compute device. The compute device includes an image capture device and an image acquisition module to obtain, with the image capture device, an image that depicts the skin of the person. The compute device also includes a skin feature determination module to identify pixels in the obtained image that are associated with the skin of the person, and determine one or more features of the skin based on the identified pixels. Additionally, the compute device includes an identity determination module to generate a feature vector that includes the determined features of the skin, and analyze the feature vector with reference data to determine an identity of the person. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: January 15, 2019
    Assignee: Intel Corporation
    Inventors: Rita Chattopadhyay, Tina Alam
  • Patent number: 10181969
    Abstract: An apparatus is described that includes a receiver. The receive includes a data sampler, a positive error sampler and a negative error sampler each having respective inputs coupled to a same differential channel. The receiver also includes circuitry to drive the respective inputs, the circuitry to place a same calibration voltage on the differential channel to calibrate each of the data sampler, positive error sampler and negative error sampler with the same calibration voltage.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: January 15, 2019
    Assignee: Intel Corporation
    Inventors: Shenggao Li, Ji Chen
  • Patent number: 10181940
    Abstract: Described are apparatuses and methods for reducing channel physical layer (C-PHY) switching jitter. An apparatus may include a pattern dependent delay circuit to detect a switching pattern of at least three data signals on respective wires and adaptively change delays of the at least three data signals based on the switching pattern. The apparatus may further include a transmitter, coupled to the pattern dependent delay circuit, to transmit the at least three data signals.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: January 15, 2019
    Assignee: Intel Corporation
    Inventor: Jonggab Kil
  • Patent number: 10182217
    Abstract: The present disclosure provides a projection device and manufacturing method, comprising the steps of fixing the positions of a red light source, green light source and blue light source so that the light sources are immovable; providing a mirror which is configured to oscillate such that it can scan light it receives across a display screen; positioning an optical component, which is configured to deflect light, such that it can receive red, green and blue light beams outputted from the red, green and blue light sources respectively; adjusting the optical component such that the optical component compensates for variation between the light sources, in the direction in which the red, green and blue light beams are output from the red, green and blue light sources, so that each of the red, green and blue light beams are directed to the same point on the display screen.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: January 15, 2019
    Assignee: INTEL CORPORATION
    Inventors: Lucio Kilcher, Nicolas Abele
  • Patent number: 10181945
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: January 15, 2019
    Assignee: INTEL CORPORATION
    Inventors: Shay Gueron, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • Patent number: 10181996
    Abstract: Methods, computer readable media, and wireless apparatuses are disclosed for trigger frame recovery. An apparatus of a wireless device is disclosed. The apparatus comprising processing circuitry configured to: encode a trigger frame comprising a resource allocation for one or more stations, where the trigger frame comprises a network allocation vector (NAV) duration. The processing circuitry may be further configured to configure the wireless device to transmit the trigger frame to the one or more stations. The processing circuitry may be further configured to configure the wireless device to contend for the wireless medium a first time, encode a retransmission of the trigger frame, and configure the wireless device to transmit the retransmission of the trigger frame to the one or more stations, if a frame is not received from the one or more stations in response to the trigger frame before a trigger frame timeout duration.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: January 15, 2019
    Assignee: Intel IP Corporation
    Inventors: Po-Kai Huang, Yaron Alpert, Laurent Cariou, Robert J. Stacey
  • Patent number: 10182181
    Abstract: Various embodiments may be generally directed to techniques for synchronizing operation of a flash light with operation of a camera using a rolling shutter for image capture. Various embodiments provide techniques for illuminating portions of a field of view of a camera substantially synchronously with portions of the field of view of the camera undergoing image capture. Various embodiments provide techniques for illuminating sequential sections of the camera field of view, rather than the entire field of view of the camera, at substantially the same time that a sensor of the camera performs image capture operations using corresponding portions of an image sensor, such as exposing the sensors to light from the image to be captured.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: January 15, 2019
    Assignee: INTEL CORPORATION
    Inventor: Nizan Horesh
  • Patent number: 10182437
    Abstract: Some demonstrative embodiments include apparatuses, devices, systems and methods of dynamic allocation using a grant frame. For example, a wireless station may be able to generate a grant frame including a duration field and a Dynamic Allocation Info field, the Dynamic Allocation Info field including an allocation duration subfield and an access mode subfield, the access mode subfield to indicate an access mode of an allocation according to the grant frame; and to transmit the grant frame.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: January 15, 2019
    Assignee: INTEL IP CORPORATION
    Inventors: Solomon B. Trainin, Carlos Cordeiro
  • Patent number: 10181946
    Abstract: Technologies for cryptographic protection of I/O data include a computing device with one or more I/O controllers. Each I/O controller may generate a direct memory access (DMA) transaction that includes a channel identifier that is indicative of the I/O controller and that is indicative of an I/O device coupled to the I/O controller. The computing device intercepts the DMA transaction and determines whether to protect the DMA transaction as a function of the channel identifier. If so, the computing device performs a cryptographic operation using an encryption key associated with the channel identifier. The computing device may include a cryptographic engine that intercepts the DMA transaction and determines whether to protect the DMA transaction by determining whether the channel identifier matches an entry in a channel identifier table of the cryptographic engine. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: January 15, 2019
    Assignee: Intel Corporation
    Inventors: Reshma Lal, Steven B. McGowan, Siddhartha Chhabra, Gideon Gerzon, Bin Xing, Pradeep M. Pappachan, Reouven Elbaz
  • Patent number: 10182446
    Abstract: Some demonstrative embodiments include apparatuses, systems and/or methods of selecting a wireless communication channel to communicate in a wireless communication network. For example, an apparatus may include a channel selector to select at a network controller of a first wireless communication network a first wireless communication channel to communicate between the network controller and one or more wireless communication devices, to detect on the first wireless communication channel a frame from a second wireless communication network, and based on a medium access control (MAC) address of the frame, to select between remaining on the first wireless communication channel and selecting a second wireless communication channel to communicate between the network controller and the one or more wireless communication devices.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: January 15, 2019
    Assignee: INTEL IP CORPORATION
    Inventors: Izoslav Tchigevsky, Noam Ginsburg
  • Patent number: 10181975
    Abstract: An override subsystem on the host side of a serial data link between the host and a peripheral detects and diagnoses link errors by comparing the states of the port's link-layer component and physical layer. An override controller accesses a data-store containing stored policies for responding to particular errors. After selecting the appropriate policy, the override controller takes control of the physical layer, the link-layer component, or both, reconfigures them according to the policy to correct the errors, and returns control of the physical layer to the host controller and link-layer component. As well as error recovery, the override subsystem may be used by applications or drivers to asynchronously manage power consumed by the link.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: January 15, 2019
    Assignee: Intel Corporation
    Inventor: Satheesh Chellappan
  • Patent number: 10182362
    Abstract: Described are methods and devices for increasing the efficiency of Wi-Fi networks by increased spatial reuse, which refers to sharing the same wireless spectral resources over different spatial regions. A described technique for doing this is for a Wi-Fi device to increase the threshold of the clear channel assessment (CCA) so as to ignore and regard as interference the transmissions from other devices. The sensing range of the Wi-Fi device then decreases, and the spatial resource can be reused by different Wi-Fi devices in different spatial locations.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: January 15, 2019
    Assignee: Intel IP Corporation
    Inventors: Po-Kai Huang, Robert J. Stacey
  • Patent number: 10182369
    Abstract: Computer readable media, methods, and apparatuses for flow control with acknowledgment feedback. An apparatus of a wireless device comprising: memory; and processing circuitry coupled to the memory is disclosed. The processing circuity may be configured to determine based on buffer capacity parameters of a station and a receive buffer state of the station at least one of a size, a modulation and coding scheme (MCS), a bandwidth of a subchannel, or a number of spatial streams (NSS) for a frame. The processing circuitry may be further configured to encode the frame based on the size, the MCS, the bandwidth of the subchannel, and the NSS. The processing circuitry may be further configured to configure the wireless device to transmit the frame in accordance with the size, the MCS, the bandwidth of the subchannel, the NSS, and one or both of orthogonal frequency division multiple-access (OFDMA) or multi-user multiple-input multiple-output (MU-MIMO).
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: January 15, 2019
    Assignee: Intel IP Corporation
    Inventors: Laurent Cariou, Yaron Alpert, Robert J. Stacey