Abstract: Embodiments are provided for summarization and recommendation of content. In disclosed embodiments, a summarization engine scores constituent parts of content, and generates a plurality of summaries from a plurality of points of view for the content based at least in part on the scores of constituent parts. The summaries may be formed with constituent parts extracted from the contents. A recommendation engine provides recommendations to a user based on rankings of the summaries generated by the summarization engine. Other embodiments may be described and/or claimed.

Abstract: Embodiments are directed to systems and methods for reuse of FMA execution unit hardware logic to provide native support for execution of get exponent, get mantissa, and/or scale instructions within a GPU. These new instructions may be used to implement branch-free emulation algorithms for mathematical functions and analytic functions (e.g., transcendental functions) by detecting and handling various special case inputs within a pre-processing stage of the FMA execution unit, which allows the main dataflow of the FMA execution unit to be bypassed for such special cases. Since special cases are handled by the FMA execution unit, library functions emulating various functions, including, but not limited to logarithm, exponential, and division operations may be implemented with significantly fewer lines of machine-level code, thereby providing improved performance for HPC applications.

Abstract: The substrate of an integrated circuit component comprises a cutout that extends fully or partially through the substrate. An edge of a photonic integrated circuit (PIC) in the integrated circuit component is coplanar with a wall of the cutout or extends into the cutout. An optical fiber in an FAU is aligned with a waveguide within the PIC and the FAU is attached to the PIC edge and an attachment block. The attachment block provides an increased attachment surface area for the FAU. A portion of the FAU extends into the substrate cutout. A stress relief mechanism can secure the fiber optic cable attached to the FAU to the substrate to at least partially isolate the FAU-PIC attachment from external mechanical forces applied to the optical fiber cable. The integrated circuit component can be attached to a socket that comprises a socket cutout into which an FAU can extend.

Abstract: Disclosed herein are IC devices with fishbone capacitor structures. An example capacitor structure includes a first capacitor electrode, a second capacitor electrode, and a third capacitor electrode, wherein the first capacitor electrode is a first line with protrusions on a side of the first line, the second capacitor electrode is a second line with protrusions on a first side of the second line and protrusions on a second side of the second line, the third capacitor electrode is a third line with protrusions on a side of the third line, the protrusions on the side of the first line and the protrusions on the first side of the second line form a first interdigitated capacitor structure, and the protrusions on the side of the third line and the protrusions on the second side of the second line form a second interdigitated capacitor structure.

Abstract: Disclosed herein are antenna modules, electronic assemblies, and communication devices. An example antenna module includes an IC component, an antenna patch support over a face of the IC component, and a stack of antenna patches vertically arranged at least partially above one another, where a first antenna patch of the stack is an antenna patch closest to the IC component, and a second antenna patch of the stack is an antenna patch closest to the first antenna patch. The first antenna patch is on the face of the IC component while the second and further antenna patches of the stack are on or in the antenna patch support and are electrically isolated from all electrically conductive material pathways in the antenna patch support and in the IC component.

Abstract: Gesture input with multiple displays, views, and physics is described. In one example, a method includes generating a three dimensional space having a plurality of objects in different positions relative to a user and a virtual object to be manipulated by the user, presenting, on a display, a displayed area having at least a portion of the plurality of different objects, detecting an air gesture of the user against the virtual object, the virtual object being outside the displayed area, generating a trajectory of the virtual object in the three-dimensional space based on the air gesture, the trajectory including interactions with objects of the plurality of objects in the three-dimensional space, and presenting a portion of the generated trajectory on the displayed area.

Abstract: Devices, transistor structures, systems, and techniques are described herein related to coupling backside and frontside metallization layers that are on opposite sides of a device layer. A device includes a transistor having semiconductor structures extending between a source and a drain, and a gate between the source and drain, a bridge via extending between a frontside metallization over the transistor and a backside metallization below the transistor, and a thin insulative liner between the bridge via and components of the transistor.

Abstract: Methods and apparatus relating to techniques for data compression. In an example, an apparatus comprises a processor receive a data compression instruction for a memory segment; and in response to the data compression instruction, compress a sequence of identical memory values in response to a determination that the sequence of identical memory values has a length which exceeds a threshold. Other embodiments are also disclosed and claimed.

Abstract: An apparatus to facilitate acceleration of machine learning operations is disclosed. The apparatus comprises at least one processor to perform operations to implement a neural network and accelerator logic to perform communicatively coupled to the processor to perform compute operations for the neural network.

Abstract: A kinematically aligned optical connector may be implemented with a silicon PIC component and a glass substrate component. The kinematically aligned optical connector includes one or more kinematic connectors or mechanical alignment features and visual fiducials that enable true kinematic coupling (i.e., in a three-dimensional Cartesian coordinate system, full constraint in all 6 degrees of freedom, meaning, X, Y, Z planes and all 3 angles), and enables an increased thickness of the glass substrate material of the glass waveguide substrate.

Abstract: Covers for integrated circuit package sockets are disclosed herein. An example cover for a socket for an integrated circuit package includes a base including a cutout, the cutout to engage a pin associated with the socket, engagement of the cutout and the pin to maintain a position of the cover relative to the socket; and a handle to facilitate positioning of the cover to move the cutout into engagement with the pin.

Abstract: A block of a video frame can be encoded using inter-prediction, and the motion vector of the block can be encoded based on a motion vector reference of a merge candidate. Some video codecs allow a large range of temporal and spatial neighbors to be considered as potential merge candidates. It is not practical to perform motion compensation and rate-distortion optimization for all possible merge candidates. To address this concern, a hardware-efficient process can be implemented to rank and select merge candidates. A reference frame priority list is applied to select a subset of potential reference frame combinations. An efficient top-K sorting algorithm is applied to identify merge candidates for each reference frame combination and keep top merge candidates with highest weights. Motion compensation and rate-distortion optimization are performed on the top merge candidates only.

Abstract: A computer-implemented method of audio processing comprises receiving, by at least one processor, multiple audio signals from multiple microphones. The audio signals are associated with audio emitted from a same source. The method also may include determining an audio quality indicator of individual ones of the audio signals using a neural network, and selecting at least one of the audio signals depending on the audio quality indicators.

Abstract: Integrated circuit (IC) packages with pre-applied underfill in select areas, and methods of forming the same, are disclosed herein. In one example, an IC package includes a package substrate, a first IC die electrically coupled to the package substrate, a second IC die electrically coupled to the first IC die, and a thermoset adhesive that partially fills an area between the first IC die and the second IC die.

Abstract: An electrostatic discharge protection circuit, device, system, and apparatus has ultra-low-leakage.

Abstract: There is disclosed in one example an application-specific integrated circuit (ASIC), including: an artificial intelligence (AI) circuit; and circuitry to: identify a flow, the flow including traffic diverted from a core cloud service of a network to be serviced by an edge node closer to an edge of the network than to the core of the network; receive telemetry related to the flow, the telemetry including fine-grained and flow-level network monitoring data for the flow; operate the AI circuit to predict, from the telemetry, a future service-level demand for the edge node; and cause a service parameter of the edge node to be tuned according to the prediction.

Abstract: In one embodiment, an integrated circuit package includes a package substrate, a first integrated circuit die electrically coupled to the package substrate via wire bond connectors, and a second integrated circuit die coupled to the package substrate. The package further includes a heat spreader coupled to the first integrated circuit die via a thermal interface material (TIM) and a dielectric material encompassing the first integrated circuit die and the second integrated circuit die on the package substrate. A top surface of the heat spreader is aligned with a top surface of the dielectric material.

Abstract: An electrostatic discharge protection circuit, device, system, and apparatus has low-leakage for a large voltage swing of negative current.

Abstract: Embodiments are provided for summarization and recommendation of content. In disclosed embodiments, a summarization engine scores constituent parts of content, and generates a plurality of summaries from a plurality of points of view for the content based at least in part on the scores of constituent parts. The summaries may be formed with constituent parts extracted from the contents. A recommendation engine provides recommendations to a user based on rankings of the summaries generated by the summarization engine. Other embodiments may be described and/or claimed.

Abstract: This disclosure describes systems, methods, and devices for performing performance measurements for one-way uplink packet delay in wireless communications. An apparatus of a Service Based Management Architecture (SBMA) Management Service (MnS) Producer may identify performance measurements, received from a network function (NF) of a 5th Generation (5G) wireless network, indicative of uplink packet delay between a user equipment (UE) and a protocol data unit (PDU) session anchor (PSA) user plane function (UPF) of the 5G wireless network; detect whether the performance measurements indicate that the uplink packet delay includes an uplink PDCP delay occurred in the UE (D1); and generate performance metrics for the NF using the performance measurements.

Abstract: An integrated circuit (IC) package includes a via extending through a stack of antipads in a stack of layers, and the stack of antipads has an antipad with a shorter diameter between antipads with longer diameters. The via may have first and second connections and first and second pads at or over and under the antipads. The longer diameters (over and under the shorter diameter) may be equal. Intervening antipads of intermediate size may be between the smallest antipads and the largest antipads. An antipad void profile may be tapered and concave, with flatter slopes nearer the upper and lower ends of the via and steeper slopes near a via midpoint. A second via may be adjacent the first via. One or more other vias may have an aligned (rather than a tapered) profile.

Abstract: Devices and techniques for accelerated packet processing are described herein. The device can match an action to a portion of a network data packet and accelerate the packet-processing pipeline for the network data packet through the machine by processing the action.

Abstract: A circuit system includes a platform baseboard, an integrated circuit coupled to the platform baseboard, and an auxiliary control board mounted on the platform baseboard. The auxiliary control board includes an interface device that is in communication with the integrated circuit through the platform baseboard. The auxiliary control board can perform power sequencing functions for the circuit system. The auxiliary control board can also perform telemetry gathering, hardware security functions, and configuration of the integrated circuit.

Abstract: An accelerator includes a memory, a compute zone to receive an encrypted workload downloaded from a tenant application running in a virtual machine on a host computing system attached to the accelerator, and a processor subsystem to execute a cryptographic key exchange protocol with the tenant application to derive a session key for the compute zone and to program the session key into the compute zone. The compute zone is to decrypt the encrypted workload using the session key, receive an encrypted data stream from the tenant application, decrypt the encrypted data stream using the session key, and process the decrypted data stream by executing the workload to produce metadata.

Abstract: Systems, apparatuses and methods may provide for technology that detects a tensor operation in an application, wherein the tensor operation has an unspecified tensor input size, determines the input tensor size at runtime, and selects a partition configuration for the tensor operation based at least in part on the input tensor size and one or more runtime conditions. In one example, the technology searches a lookup table for the input tensor size and at least one of the runtime condition(s) to select the partition configuration.

Abstract: Disclosed embodiments include composite-bridge die-to-die interconnects that are on a die side of an integrated-circuit package substrate and that contacts two IC dice and a passive device that is in a molding material, where the molding material also contacts the two IC dice.

Abstract: An electrostatic discharge protection circuit, device, system, and apparatus has low-leakage for a large voltage swing of positive current.

Abstract: Described herein are SRAM cells in which some transistors are implemented as thin film transistors (TFTs) while other transistors are implemented as non-TFTs (e.g., as FinFETs or nanoribbon-based transistors), where the TFTs are folded over non-TFTs to realize high-density 3D SRAM. For a given SRAM cell, either N-type transistors may be implemented as TFTs and stacked above P-type transistors that are implemented as non-TFTs, or P-type transistors may be implemented as TFTs and may be stacked above N-type transistors that are implemented as non-TFTs.

Abstract: A system and method for high performance secure access to a trusted platform module on a hardware virtualization platform. Example instructions partition resources of the host system to allocate (a) first resources of the host system for a first virtual machine and (b) second resources of the host system for a second virtual machine, wherein the resources of the host system include memory resources and a trusted platform module, the first virtual machine to run a first guest operating system and the second virtual machine to run a second guest operating system, wherein the first guest operating system is to run in a first isolated environment, the second guest operating system is to run in a second isolated environment; implement a virtual trusted platform module to support encryption for the first virtual machine; and protect the first resources and the second resources from unauthorized access.

Abstract: Some demonstrative aspects include radar apparatuses, devices, systems and methods. In one example, an apparatus may include a plurality of Transmit (Tx) antennas to transmit radar Tx signals, a plurality of Receive (Rx) antennas to receive radar Rx signals based on the Tx signals, and a processor to generate radar information based on the radar Rx signals. The apparatus may be implemented, for example, as part of a radar device, for example, as part of a vehicle including the radar device. In other aspects, the apparatus may include any other additional or alternative elements and/or may be implemented as part of any other device.

Abstract: An Infrastructure Processing Unit (IPU), including: a model optimization processor configured to optimize an artificial intelligence (AI) model for an accelerator managed by the IPU, and deploy the optimized AI model to the accelerator for execution of an inference; and a local memory configured to store data related to the AI model optimization.

Abstract: For example, an apparatus may include an Electromagnetic Interference (EMI) shield, which may be configured to provide EMI shielding for electronic circuitry on a Printed Circuit Board (PCB). For example, the EMI shield may be configured to include an EMI shield lid; and an EMI shield connector to electrically couple the EMI shield lid to at least one tube on the PCB to provide a ground to the EMI shield lid via the at least one tube. For example, the EMI shield connector may be configured to maintain the EMI shield lid over the electronic circuitry on the PCB.

Abstract: An example of an apparatus may include circuitry to monitor one or more sensors, determine a debug condition based on the monitored one or more sensors, and provide an indication of the debug condition. In some examples, the apparatus includes further circuitry to adjust a debug operation based at least in part on the provided indication of the debug condition. Other examples are disclosed and claimed.

Abstract: An apparatus to facilitate efficient data sharing for graphics data processing operations is disclosed. The apparatus includes a processing resource to generate a stream of instructions, an L1 cache communicably coupled to the processing resource and comprising an on-page detector circuit to determine that a set of memory requests in the stream of instructions access a same memory page; and set a marker in a first request of the set of memory requests; and arbitration circuitry communicably coupled to the L1 cache, the arbitration circuitry to route the set of memory requests to memory comprising the memory page and to, in response to receiving the first request with the marker set, remain with the processing resource to process the set of memory requests.

Abstract: A computing platform is disclosed. The computing platform includes a first computer system comprising a first graphics processing unit (GPU), a network coupled to the first computer system and a second computer system, coupled to the first computer system via the network, comprising a second GPU, wherein the first and second computer system are configured to perform distributed processing of graphics workloads between the first GPU and the second GPU.

Abstract: A three-dimensional memory array may include a first memory array and a second memory array, stacked above the first. Some memory cells of the first array may be coupled to a first layer selector transistor, while some memory cells of the second array may be coupled to a second layer selector transistor. The first and second layer selector transistor may be coupled to one another and to a peripheral circuit that controls operation of the first and/or second memory arrays. A different layer selector transistor may be used for each row of memory cells of a given memory array and/or for each column of memory cells of a given memory array. Such designs may allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

Abstract: A server is provided. The server comprises one or more interfaces configured to communicate with a client and processing circuitry configured to control the one or more interfaces and to transmit an interrupt to the client informing the client about an operation state of the server.

Abstract: An apparatus to verify firmware in a computing system, comprising a non-volatile memory, including firmware memory to store agent firmware associated with each of a plurality of interconnect protocol (IP) agents and version memory to store security version numbers (SVNs) included in the agent firmware, a security controller comprising verifier logic to verify an integrity of the version memory by applying a hash algorithm to contents of the version memory to generate a SVN hash, and a trusted platform module (TPM) to store the SVN hash.

Abstract: An electronic device may include an organic light emitting display (OLED), a heat generating device, and a heat spreading device. The heat generating device may provide heat directly to the heat spreading device, and the heat spreading device is to dissipate the heat from the heat generating device and evenly heat the OLED and lower a driving voltage of the OLED to reduce power consumption of the OLED.

Abstract: An integrated circuit includes a region of configurable logic circuits, and a control circuit that generates a digital signature based on a private key and data using a signing engine for verifying that data stored in the region of the configurable logic circuits has been erased. A method is provided for verifying that the region of the configurable logic circuits in the integrated circuit has been erased. The method includes receiving a public key, data, and a digital signature at a control circuit comprising a signature verifier engine, and generating an output that verifies whether the region of the configurable logic circuits has been erased by performing a signature verification of the digital signature using the data and the public key with the signature verifier engine.

Abstract: Provided herein are mechanisms on response of pre-allocated resource based PUSCH transmission. The disclosure provides an apparatus including processor circuitry. The processor circuitry is to: encode data, for transmission to an access node (AN) over a pre-allocated uplink (UL) resource (PUR) based physical uplink shared channel (PUSCH); start a timer once the data is transmitted; and monitor, based on the timer, a physical downlink control channel (PDCCH) to obtain a response of the AN to the transmission of the data. Other embodiments may also be disclosed and claimed.

Abstract: This disclosure describes systems, methods, and devices related to enhanced frame exchange. A device may generate a first subset of a plurality of fields, wherein the first subset is mandatory in a probe request frame. The device may generate a second subset of the plurality of fields, wherein the second subset is optional in the probe request frame regardless of capability information of the device. The device may generate the probe request frame comprising the first subset and the second subset. The device may cause to send the probe request frame to an access point (AP) device.

Abstract: Embodiments are generally directed to methods and apparatuses for dynamically changing data priority in a cache. An embodiment of an apparatus comprising: a priority controller to: receive a memory access request to request data; and set a priority flag for the memory access request based on an accumulated access amount of data stored in a memory block to be accessed by the memory access request to dynamically change a priority level of the requested data.

Abstract: Embodiments are generally directed apparatuses, methods, techniques and so forth determine an access level of operation based on an indication received via one or more network links from a pod management controller, and enable or disable a firmware update capability for a firmware device based on the access level of operation, the firmware update capability to change firmware for the firmware device. Embodiments may also include determining one or more configuration settings of a plurality of configuration settings to enable for configuration based on the access level of operation, and enable configuration of the one or more configuration settings.

Abstract: Systems, apparatuses and methods include technology that identifies a first neural network, wherein the first neural network is associated with a first training parameter and first population data that are generated during a process to train the first neural network. The technology executes a first neural network process to serve input data with the first neural network, and estimates a first drift of the first neural network based on the first neural network process, the first training parameter and the first population data to determine whether to retrain the first neural network.

Abstract: Embodiments may relate to an electronic device that includes a modulator to modulate an in-phase portion of an input signal and a quadrature portion of the input signal. The modulator may include a III-V material on a silicon substrate. In some embodiments, the III-V material may include, for example, indium phosphide (InP). Other embodiments may be described or claimed.

Abstract: A computer platform is disclosed. The computer platform comprises a central processing unit (CPU) including at least one socket having a plurality of tiles and control circuitry to partition the socket into a plurality of sub-sockets and assign a unique identity to each of the plurality of sub-sockets for security verification, wherein each sub-socket comprises at least one of the plurality of tiles to operate as a cluster of resources.

Abstract: Backside contact structures include etch selective materials to facilitate backside contact formation. An integrated circuit structure includes a frontside contact region, a device region below the frontside contact region, and a backside contact region below the device region. The device region includes a transistor. The backside contact region includes a first dielectric material under a source or drain region of the transistor, a second dielectric material laterally adjacent to the first dielectric material and under a gate structure of the transistor. A non-conductive spacer is between the first and second dielectric materials. The first and second dielectric materials are selectively etchable with respect to one another and the spacer. The backside contact region may include an interconnect feature that, for instance, passes through the first dielectric material and contacts a bottom side of the source/drain region, and/or passes through the second dielectric material and contacts the gate structure.

Abstract: Embodiments described herein are generally directed to an end-to-end trainable degradation restoration network (DRN) that enhances the ability of a super-resolution (SR) subnetwork to deal with noisy low-resolution images. An embodiment of a method includes estimating, by a noise estimator (NE) subnetwork of the DRN, an estimated noise map for a noisy input image; and predicting, by the SR subnetwork of the DRN, a clean upscaled image based on the input image and the noise map by, for each of multiple conditional residual dense blocks (CRDBs) stacked within one or more cascade blocks representing the SR subnetwork, adjusting, by a noise control layer of the CRDB that follows a stacked set of a multiple residual dense blocks of the CRDB, feature values of an intermediate feature map associated with the input image by applying (i) a scaling factor and (ii) an offset factor derived from the noise map.

Abstract: An integrated circuit capacitor structure, includes a first electrode includes a cylindrical column, a ferroelectric layer around an exterior sidewall of the cylindrical column and a plurality of outer electrodes. The plurality of outer electrodes include a first outer electrode laterally adjacent to a first portion of an exterior of the ferroelectric layer and a second outer electrode laterally adjacent to a second portion of the exterior of the ferroelectric layer, wherein the second outer electrode is above the first outer electrode.