Intel Patent Applications
Intel patent applications that are pending before the United States Patent and Trademark Office (USPTO).
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Publication number: 20190045198Abstract: Techniques related to detection of features and modification of encoding based on such detected features for improved data utilization efficiency are discussed. Such techniques include generating a partitioning decision for a block and coding mode decisions for partitions of the individual block using the detected features or indicators thereof based on one or more of generating a luma and chroma or luma only evaluation decision for a partition, generating a merge or skip mode decision for a partition having an initial merge mode decision, generating only a portion of a transform coefficient block for a partition, and evaluating 4×4 partitions only for any partition of the partitions that are 8×8 initial coding partitions.Type: ApplicationFiled: December 28, 2017Publication date: February 7, 2019Applicant: Intel CorporationInventors: Nader MAHDI, Chekib NOUIRA, Hassen GUERMAZI, Faouzi KOSSENTINI
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Publication number: 20190043570Abstract: An embodiment of a semiconductor apparatus may include technology to convert an analog voltage level of a memory cell of a multi-level memory to a multi-bit digital value, and determine a single-bit value of the memory cell based on the multi-bit digital value. Some embodiments may also include technology to track a temporal history of accesses to the memory cell for a duration in excess of ten seconds, and determine the single-bit value of the memory cell based on the multi-bit digital value and the temporal history. Other embodiments are disclosed and claimed.Type: ApplicationFiled: March 5, 2018Publication date: February 7, 2019Applicant: Intel CorporationInventors: Bruce Querbach, Christopher Connor
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Publication number: 20190041719Abstract: Technology for improving performance of a personal display device by variably controlling the emission divergence and/or the emission direction of light from the pixels of the display as a function of the location of the pixel within a display.Type: ApplicationFiled: January 2, 2018Publication date: February 7, 2019Applicant: Intel CorporationInventors: Zhiming Zhuang, Ginni Grover, Jun Jiang, Basel Salahieh, Oscar Nestares, David W. Browning
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Publication number: 20190042747Abstract: The present disclosure is directed to systems and methods for mitigating or eliminating the effectiveness of a side channel attack, such as a Meltdown or Spectre type attack by selectively introducing a variable, but controlled, quantity of uncertainty into the externally accessible system parameters visible and useful to the attacker. The systems and methods described herein provide perturbation circuitry that includes perturbation selector circuitry and perturbation block circuitry. The perturbation selector circuitry detects a potential attack by monitoring the performance/timing data generated by the processor. Upon detecting an attack, the perturbation selector circuitry determines a variable quantity of uncertainty to introduce to the externally accessible system data. The perturbation block circuitry adds the determined uncertainty into the externally accessible system data. The added uncertainty may be based on the frequency or interval of the event occurrences indicative of an attack.Type: ApplicationFiled: June 29, 2018Publication date: February 7, 2019Applicant: Intel CorporationInventors: Vadim Sukhomlinov, Kshitij Doshi, Francesc Guim, Alex Nayshtut
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Publication number: 20190042482Abstract: Techniques are described for providing consistent memory operations and security across electronic circuitry components having disparate memory and/or security architectures when integrating such disparately architected components within a single system, such as a system on chip. A programmable logical hierarchy of isolated memory region (IMR) enforcement circuits is provided to protect such IMRs, allowing or preventing memory access requests from one of multiple distinct circuitry components based on configuration registers for the IMR enforcement circuits. Integration of multiple trust domain architectures associated with the multiple distinct circuitry components is facilitated via trust domain conversion bridge circuitry that includes translation logic for generating information in accordance with a first trust domain architecture based on information provided in accordance with a distinct second trust domain architecture.Type: ApplicationFiled: May 28, 2018Publication date: February 7, 2019Applicant: Intel CorporationInventors: Aditya Katragada, Peter Munguia, Gregg Lahti
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Publication number: 20190037639Abstract: An Internet of Things (IoT) device includes a transceiver to transmit and receive data packets. The IoT device also includes a controller to alternate between upstream and downstream relaying of data packets via the transceiver.Type: ApplicationFiled: December 30, 2017Publication date: January 31, 2019Applicant: Intel CorporationInventors: Keith Nolan, Mark Kelly, Charlie Sheridan
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Publication number: 20190033683Abstract: Flat optical elements including a multi-level metasurface stack having two or more metasurface levels. Each metasurface level includes an arrangement of nanostructures, or protrusions, of one or more optically transmissive materials. A metasurface level may further include another optically transmissive material between the nanostructures, achieving a desired index contrast. Another metasurface level including additional nanostructures may be over a planar surface of this additional transmissive material. Another optically transmissive material may be between the additional nanostructures. This architecture may be followed for any number of levels, (e.g., a bi-layer, tri-layer, etc.). Each metasurface within the multi-level metasurface structure may be tuned to a particular optical wavelength. Such a multi-level metasurface may have greater bandwidth and/or achieve higher optical efficiency for a given band than a single metasurface.Type: ApplicationFiled: December 18, 2017Publication date: January 31, 2019Applicant: Intel CorporationInventors: Khaled Ahmed, Richmond Hicks
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Publication number: 20190034427Abstract: Disclosed is a data management system configured to provide a key-value data structure architecture for use with a storage device. The key-value data structure includes a logic tree having a tree-based index and a hash table having a hash-based index. For a ‘scan’ (or range query) operation, the data management system scans the tree-based index to determine which keys exist between two search keys in the tree-based index. For a ‘get’ (e.g., a value request) operation, the data management system applies a hash function to a provided key to determine an index in the hash table by which to retrieve a value that corresponds with the provided key. Other operations (e.g., ‘put’, ‘update’, ‘delete’) may include updating both the tree-based index and the hash-based index. The logic tree stores keys and stores a zero byte-sized value with each of the keys, to limit the size of the logic tree.Type: ApplicationFiled: December 28, 2017Publication date: January 31, 2019Applicant: Intel CorporationInventors: Sanjeev N. Trika, Dongchul Park, Peng Li, Francis R. Corrado, Robert A. Dickinson
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Publication number: 20190034919Abstract: Methods and systems are provided for securing e-wallet transactions. In an example method, a transaction is created in a device hosting a first e-wallet. The transaction is signed with a first wallet key. The transaction is signed in a subsequent device with a subsequent wallet key to create a subsequent transaction.Type: ApplicationFiled: December 29, 2017Publication date: January 31, 2019Applicant: INTEL CORPORATIONInventors: Michael Nolan, Davide Carboni, Mark Kelly, Cliodhna Ni Scanaill, Keith Nolan, Ned M. Smith
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Publication number: 20190034616Abstract: An input device of a secure authentication protocol system may receive at least one user authentication factor in a pre-boot session. The input device may verify the received authentication factors and may store the verified authentication factors. During a post-boot session, the input device may communicate the verified authentication factor and a stored post-boot session credential received during a prior post-boot session to an authentication engine executing in a trusted execution environment. The authentication engine verifies the received post-boot session credential is logically associated with an immediately preceding post-boot session. Upon successful verification of the received post-boot session credential, the verified authentication factors or data indicative of a successfully verified authentication factor received during the pre-boot session are used in the current post-boot session.Type: ApplicationFiled: September 10, 2018Publication date: January 31, 2019Applicant: Intel CorporationInventors: MICHAEL RAZIEL, ABHILASHA BHARGAV-SPANTZEL, HORMUZD M. KHOSRAVI
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Publication number: 20190036704Abstract: A system for verifying the secure erase of a storage device is provided. A storage device controller for the storage device logs the execution of a secure erase command. A storage device controller for the storage device receives an erase verify command from a host. The storage device controller retrieves one or more secure erase log entries from access-limited memory locations in non-volatile memory of the storage device. The storage device controller copies the one or more secure erase log entries to storage device buffer circuitry. The storage device controller secures the one or more secure erase log entries with one or more cryptographic keys to generate an encrypted and/or signed erase verification message. The storage device controller transmits the encrypted and/or signed erase verification message to the host, in response to receipt of the erase verify command.Type: ApplicationFiled: December 27, 2017Publication date: January 31, 2019Applicant: Intel CorporationInventors: DOUG DeVETTER, JAMES CHU, ADRIAN PEARSON, GAMIL CAIN, SRIKANTH VARADARAJAN
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Publication number: 20190035051Abstract: One embodiment provides for a general-purpose graphics processing unit comprising multiple processing elements having a single instruction, multiple thread architecture, the multiple processing elements enabled to perform hardware multithreading, wherein execution context for threads to be executed is maintained on-chip during execution, a scheduler to schedule a warp to the multiple processing elements, wherein the warp is a group of parallel threads, the warp includes multiple sub-warps, and threads within the warp diverge at sub-warp granularity, and a logic unit including hardware or firmware logic, the logic unit to group active threads from the warp for execution on the multiple processing elements.Type: ApplicationFiled: October 2, 2018Publication date: January 31, 2019Applicant: Intel CorporationInventors: Balaji Vembu, Altug Koker, Joydeep Ray
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Publication number: 20190036987Abstract: Techniques for augmented social networking may include receiving an image. After receiving an image, in real time, an identity of a person in the image may be determined. Association information for the person based on the identity and one or more defined parameters may be determined. The defined parameters may represent electronic communication. Location information of the person may be determined. The association information may be presented proximate to the person in an augmented reality view using the location information. Other embodiments are described and claimed.Type: ApplicationFiled: February 12, 2018Publication date: January 31, 2019Applicant: INTEL CORPORATIONInventors: JOSHUA J. RATCLIFF, KENTON M. LYONS
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Publication number: 20190036574Abstract: Briefly, in accordance with one or more embodiments, an apparatus of a user equipment (UE) comprises one or more baseband processors to decode one or more channel state information reference signals (CSI-RS) received from an evolved Node B (eNB) using open loop full-dimension multiple input, multiple output (FD-MIMO), and to generate feedback to the eNB responsive to the one or more CSI-RS signals, and a memory to store a Class A codebook from which the feedback is generated, wherein the feedback includes an i1 codebook index of the Class A codebook and a channel quality indicator (CQI) determined based at least in part on i2 codebook index cycling across one or more physical resource blocks (PRBs). In some embodiments, Class B feedback using a Class B codebook by be utilized.Type: ApplicationFiled: February 8, 2017Publication date: January 31, 2019Applicant: Intel IP CorporationInventors: Yuan Zhu, Yushu Zhang, Wenting Chang, Alexei Davydov, Qinghua Li
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Publication number: 20190036552Abstract: The present disclosure includes systems and methods for supporting polar codewords with variable polar codeword lengths. Variable codeword length codewords are communicated using an n-bit encoder/n-bit decoder having n inputs and n corresponding outputs. Each input and each corresponding output is associated with a bit index. A set of bit indices to be shortened are selected. The encoder encodes n input bits to obtain n output bits. Each output bit that is associated with a bit index from the set of bit indices to be shortened is ignored. A codeword is generated from all of the remaining output bits.Type: ApplicationFiled: June 13, 2016Publication date: January 31, 2019Applicant: INTEL CORPORATIONInventors: Eren Sasoglu, Wook Bong Lee
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Publication number: 20190033910Abstract: One embodiment provides a master device in a bus system. The master device includes bus interface circuitry to exchange commands and data with a slave device in communication with the master device; and test sequence generation logic to generate at least one test sequence, each test sequence having a corresponding unique clock signal having a unique clock frequency; the test sequence generation logic also to transmit the at least one test sequence and the corresponding unique clock signal to the slave device; the test signal generation logic also to determine, based on feedback from the slave device, if the slave device is capable of communicating with the master device using the unique clock frequency.Type: ApplicationFiled: December 27, 2017Publication date: January 31, 2019Applicant: Intel CorporationInventors: PATRIK EDER, ROLF KUEHNIS, ENRICO CARRIERI
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Publication number: 20190034376Abstract: Aspects of the embodiments are directed to systems and methods for performing link training using stored and retrieved equalization parameters obtained from a previous equalization procedure. As part of a link training sequence, links interconnecting an upstream port with a downstream port and with any intervening retimers, can undergo an equalization procedure. The equalization parameter values from each system component, including the upstream port, downstream port, and retimer(s) can be stored in a nonvolatile memory. During a subsequent link training process, the equalization parameter values stored in the nonvolatile memory can be written to registers associated with the upstream port, downstream port, and retimer(s) to be used to operate the interconnecting links. The equalization parameter values can be used instead of performing a new equalization procedure or can be used as a starting point to reduce latency associated with equalization procedures.Type: ApplicationFiled: November 14, 2017Publication date: January 31, 2019Applicant: Intel CorporationInventor: Debendra Das Sharma
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Publication number: 20190035362Abstract: Various embodiments are generally directed to techniques to partition a display interface such that pixel data associated with display data having indications of an image to be displayed may be transmitted to multiple timing controller and driver (TCON-DR) sets over the display interface without necessitating each TCON-DR set receive all the pixel data. In some examples, the display interface may be partitioned such that each TCON-DR set receives only the pixel data for which the respective TCON-DR set corresponds to.Type: ApplicationFiled: September 28, 2018Publication date: January 31, 2019Applicant: INTEL CORPORATIONInventor: Seh W. KWA
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Publication number: 20190034936Abstract: Methods and systems are provided for approving transactions for an electronic wallet (e-wallet). An example method includes combining a transaction with an M of N threshold authorization policy to create an approval request in an originating e-wallet share hosted in a first device. The approval request is signed in the originating e-wallet share to create an initial approval request. The initial approval request is provided to an anonymizing router to be transferred to another device hosting another e-wallet share for signing.Type: ApplicationFiled: December 29, 2017Publication date: January 31, 2019Applicant: INTEL CORPORATIONInventors: Michael Nolan, Davide Carboni, Ned M. Smith
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Publication number: 20190034101Abstract: Various embodiments are directed to providing integrity protection for a system management mode. During initialization, a hash value of a system management mode control routine may be determined. Subsequently, during operation, the hash value may be compared to a hash value of a system management mode control routine to be executed. The system management mode control routine to be executed may be determined to be authentic if the hash values are the same.Type: ApplicationFiled: September 28, 2018Publication date: January 31, 2019Applicant: INTEL CORPORATIONInventors: Jorge E. GONZALEZ DIAZ, Juan Manuel CRUZ ALCARAZ
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Publication number: 20190036586Abstract: Control information may be multiplexed, by User Equipment (UE), with non-control uplink data (e.g., user data) and transmitted in the PUSCH. In one implementation, in combining the control information and the user data, the control information and the user data may be interleaved in a manner in which the control information is mapped in a time-first direction and the user data is mapped in a frequency-first direction. Additionally, the control information may include beam information (BI).Type: ApplicationFiled: June 23, 2016Publication date: January 31, 2019Applicant: Intel IP CorporationInventors: Glenn Bradford, Gang Xiong, Ajit Nimbalker, Joonyoung Cho
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Publication number: 20190035889Abstract: Transistor devices having an indium-containing ternary or greater III-V compound active channels, and processes for the fabrication of the same, may be formed that enables improved carrier mobility when fabricating fin shaped active channels, such as those used in tri-gate or gate all around (GAA) devices. In one embodiment, an indium-containing ternary or greater III-V compound may be deposited in narrow trenches on a reconstructed upper surface of a sub-structure, which may result in a fin that has indium rich side surfaces and an indium rich bottom surface. These indium rich surfaces will abut a gate oxide of a transistor and may result in high electron mobility and an improved switching speed relative to conventional homogeneous compositions of indium-containing ternary or greater III-V compound active channels.Type: ApplicationFiled: February 22, 2016Publication date: January 31, 2019Applicant: Intel CorporationInventors: Chandra S. Mohapatra, Anand S. Murthy, Glenn A. Glass, Matthew V. Metz, Willy Rachmady, Gilbert Dewey, Tahir Ghani, Jack T. Kavalieros
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Publication number: 20190034829Abstract: Technology for a data filter device operable to filter training data is described. The data filter device can receive training data from a data provider. The training data can be provided with corresponding metadata that indicates a model stored in a data store that is associated with the training data. The data filter device can identify a filter that is associated with the model stored in the data store. The data filter device can apply the filter to the training data received from the data provider to obtain filtered training data. The data filter device can provide the filtered training data to the model stored in the data store, wherein the filtered training data is used to train the model.Type: ApplicationFiled: December 28, 2017Publication date: January 31, 2019Applicant: Intel CorporationInventors: FRANCESC GUIM BERNAT, MARK A. SCHMISSEUR, KARTHIK KUMAR, THOMAS WILLHALM
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Publication number: 20190035749Abstract: Wireless modules having a semiconductor package attached to an antenna package is disclosed. The semiconductor package may house one or more electronic components as a single die package and/or a system in a package (SiP) implementation. The antenna package may be communicatively coupled to the semiconductor package using by one or more coupling pads. The antenna package may further have one or more radiating elements for transmitting and or receiving wireless signals. The antenna package and the semiconductor package may have dissimilar number of interconnect layers and/or dissimilar materials of construct.Type: ApplicationFiled: April 1, 2016Publication date: January 31, 2019Applicant: INTEL CORPORATIONInventors: Sidharth DALMIA, Ana M. YEPES, Pouya TALEBBEYDOKHTI, Miroslav BARYAKH, Omer ASAF
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Publication number: 20190036836Abstract: Techniques are provided for adaptive distribution of video analysis workload over a network of video processor nodes. The nodes may include, for example, internet protocol (IP) cameras, video recorders and/or data centers. The network may also include a management system configured to assign video analysis tasks to the nodes based on the node resources and predictive modelling of the node workload. The management system may re-distribute the tasks based on performance monitoring. Some assigned tasks may be bound to the node while other tasks may be transferrable, by the node, to other nodes. The nodes may be configured to determine which of the transferrable tasks will be locally executed or transferred based on a check of resource usage against a usage policy that specifies thresholds for the determinations. The nodes may be configured to transmit video analysis packets, including image data, analysis completion status and analysis results, to other nodes.Type: ApplicationFiled: March 30, 2016Publication date: January 31, 2019Applicant: INTEL CORPORATIONInventors: HUIFENG LE, WENJIAN SHAO, YU ZHANG, SHAO-WEN YANG, HENG JUEN HAN, XIAOWEN ZHANG
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Publication number: 20190037689Abstract: A system for a three-dimensional (“3D”) printed circuit board (“PCB”) to printed circuit board interface is provided. A first PCB includes first landing pads disposed on one or more edges of the first PCB. The first landing pads electrically couple to conductive pins or second landing pads disposed on a second PCB. The second landing pads may be disposed in a slot in the second PCB. The interface between the first landing pads and the second landing pads may provide various advantages over traditional PCB to PCB interfaces, such as, improved signal integrity, improved power integrity, increased contact density, decreased clock jitter, etc.Type: ApplicationFiled: December 20, 2017Publication date: January 31, 2019Applicant: Intel CorporationInventors: DAQIAO DU, ZHEN ZHOU, JUN LIAO, JAMES A. MCCALL, XIANG LI, KAI XIAO, ZHICHAO ZHANG
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Publication number: 20190035133Abstract: In response to movement of an underlying structure, motion of complex objects connected to that structure may be simulated relatively quickly and without requiring extensive processing capabilities. A skeleton extraction method is used to simplify the complex object. Tracking is used to track the motion of the underlying structure, such as the user's head in a case where motion of hair is being simulated. Thus, the simulated motion is driven in response to the extent and direction of head or facial movement. A mass-spring model may be used to accelerate the simulation in some embodiments.Type: ApplicationFiled: March 17, 2016Publication date: January 31, 2019Applicant: Intel CorporationInventors: Shaohui JIAO, Qiang LI, Wenlong LI
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Publication number: 20190037259Abstract: Systems, apparatuses, and methods may provide for technology to conduct contemporaneous crowd-sourced voting via interaction between a client and a client interface.Type: ApplicationFiled: July 26, 2017Publication date: January 31, 2019Applicant: Intel CorporationInventors: John Gaffrey, Glen J. Anderson, Meng Shi, Therese E. Dugan
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Publication number: 20190036841Abstract: An IoT device Internet of Things (IoT) device including storage to store instructions and a processor to execute the stored instructions to prioritize data blocks of a data payload by dynamically assigning priority levels of the data blocks, and to transmit one or more of the data blocks based on the prioritizing.Type: ApplicationFiled: December 30, 2017Publication date: January 31, 2019Applicant: INTEL CORPORATIONInventors: Keith Nolan, John Brady, Mark Kelly, Charlie Sheridan
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Publication number: 20190034454Abstract: Disclosed is a file system that may support data management for a distributed data storage and computing system, such as Apache™ Hadoop®. The file system may include an expandable tree-based indexing framework that enables convenient expansion of the file system. As a non-limiting example, the file system disclosed herein may enable indexing, storage, and management of a billion or more files, which is 1,000 times the capacity of currently available file systems. The file system includes a root index system and a number of leaf index systems that are organized in a tree data structure. The leaf index systems provide heartbeat information to the root index system to enable the root index system to maintain a lightweight and searchable index of file references and leaf index references. Each of the leaf indexes maintains an index or mapping of file references to file block addresses within data storage devices that store files.Type: ApplicationFiled: December 19, 2017Publication date: January 31, 2019Applicant: Intel CorporationInventors: Uma Maheswara Rao Gangumalla, Malini Bhandaru, Rakesh Radhakrishnan Potty, Devarajulu Kavali, Niraj Rai
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Publication number: 20190034716Abstract: In one embodiment, an apparatus comprises a top-view sensing device to capture sensor data associated with an environment below the top-view sensing device. The apparatus further comprises a processor to: obtain the sensor data captured by the top-view sensing device; generate, based on the sensor data, a visual representation of the environment below the top-view sensing device; determine that the visual representation comprises a representation of a person; identify one or more features associated with the representation of the person; and identify demographic information associated with the person based on the one or more features.Type: ApplicationFiled: December 29, 2017Publication date: January 31, 2019Applicant: Intel CorporationInventors: Siti Khairuni Amalina Kamarol, Addicam V. Sanjay, Shao-Wen Yang, Siew Wen Chin
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Publication number: 20190037432Abstract: An apparatus may include a radio frequency (RF) transceiver to receive a first message over a first carrier in a first band in a downlink sub-frame of a first radio frame in a communications link, where the communications link comprises interband carriers aggregated over primary and secondary cells. The apparatus may also include a processor and a reply message assignment module operable on the processor to determine a downlink sub-frame in which the downlink transmission is received and to adjust timing of a reply/acknowledge message to be sent by the RF transceiver in response to the first message so as to coincide with a predetermined uplink sub-frame of a radio frame. Other embodiments are described and claimed.Type: ApplicationFiled: October 17, 2016Publication date: January 31, 2019Applicant: INTEL CORPORATIONInventors: PING WANG, JONG-KAE FWU, KAMRAN ETEMAD
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Publication number: 20190037708Abstract: The systems and methods described herein are directed to using a plurality of interface elements (e.g., sockets) and/or stud-bump elements embedded into board substrates (e.g., a motherboard) to enable the interchange of variable configuration components (e.g., electronic components, chips, and the like) that are mounted on package substrates having ball grid arrays (BGAs). In some aspects, this interchange can be accomplished while leaving the pre-existing board substrate design and various peripheral system components of the board substrate unchanged.Type: ApplicationFiled: April 1, 2016Publication date: January 31, 2019Applicant: INTEL CORPORATIONInventors: Sandeep SANE, Timothy SWETTLEN
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Publication number: 20190037598Abstract: Described is an apparatus of a User Equipment (UE). The apparatus may comprise a first circuitry and a second circuitry. The first circuitry may be operable to encode a Non-scheduled Physical Uplink Control Channel (N-PUCCH) in an Uplink (UL) burst transmission, and to encode a Physical Uplink Shared Channel (PUSCH) in the UL burst transmission. The second circuitry may be operable to initiate the UL burst transmission subject to a Listen-Before-Talk (LBT) protocol on a channel of the wireless network. The UL burst transmission may be initiated without a UL grant received from the eNB.Type: ApplicationFiled: September 2, 2016Publication date: January 31, 2019Applicant: Intel IP CorporationInventors: Fatemeh Hamidi-Sepehr, Abhijeet Bhorkar, Qiaoyang Ye, Huaning Niu, Hwan-Joon Kwon
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Publication number: 20190035705Abstract: Semiconductor packages with electromagnetic interference supported stacked die and a method of manufacture therefor is disclosed. The semiconductor packages may house a stack of dies in a system in a package (SiP) implementation, where one or more of the dies may be wire bonded to a semiconductor package substrate. The dies may be stacked in a partially overlapping, and staggered manner, such that portions of some dies may protrude out over an edge of a die that is below it. This dies stacking may define a cavity, and in some cases, wire bonds may be made to the protruding portions of the die. Underfill material may be provided in the cavity and cured to form an underfill support. Wire bonding of the bond pads overlying the cavity formed by the staggered stacking of the dies may be performed after the formation of the underfill support.Type: ApplicationFiled: April 2, 2016Publication date: January 31, 2019Applicant: INTEL CORPORATIONInventor: Guo MAO
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Publication number: 20190036803Abstract: An apparatus is provided which comprises: a first network interface (NI) to receive data from a source; a second NI coupled to a target; and a circuitry to generate a sequence of source timestamps and a sequence of target timestamps, wherein the first NI is to receive the sequence of source timestamps, and associate a first source timestamp of the sequence of source timestamps with the data, and wherein the second NI is to receive: the data with the first source timestamp from the first NI and the sequence of target timestamps from the circuitry, the second NI to generate a timestamp for the data, based at least in part on the first source timestamp and a first target timestamp of the sequence of target timestamps.Type: ApplicationFiled: December 7, 2017Publication date: January 31, 2019Applicant: Intel IP CorporationInventors: Pradeep Kumar, Amit Badole, Arumugam Vijayaraman, Helmut Reinig, Patrik Eder, Vladimir Todorov, Abhiram Anantharamu
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Publication number: 20190035018Abstract: Methods and systems are provided for securing distributed shares of an electronic wallet. An example method includes provisioning a plurality of devices each hosting an e-wallet share with enhanced privacy identification (EPID) private keys for the e-wallet share. A signature is posted for the e-wallet share to a blockchain. A determination is made as to whether the e-wallet share is compromised, and, if so, posting a revocation list comprising the signature for the e-wallet share to a blockchain.Type: ApplicationFiled: December 29, 2017Publication date: January 31, 2019Applicant: Intel CorporationInventors: Michael Nolan, Davide Carboni, Ned M. Smith
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Publication number: 20190036873Abstract: An apparatus for addressing a plurality of Internet of Things (IoT) devices includes storage to store instructions and a processor. The processor is to execute the stored instructions to initialize an IoT device alias addressing space, to assign an alias address to each of a plurality of the IoT devices, where the alias addresses are time-limited, and to handle packet transactions using the assigned alias addresses.Type: ApplicationFiled: December 30, 2017Publication date: January 31, 2019Applicant: INTEL CORPORATIONInventors: Keith Nolan, Mark Kelly, John Brady, Charlie Sheridan
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Publication number: 20190035720Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing a stress distribution interposer for mitigating substrate cracking. For instance, in accordance with one embodiment, there is an apparatus having therein: a substrate having electrical traces therein; a functional semiconductor die electrically interfaced to the electrical traces of the substrate; an interposer bonded at a bottom surface to the substrate and bonded at a top surface to the functional semiconductor die; and in which the interposer includes edges with a coefficient of thermal expansion and modulus which is between a coefficient of thermal expansion and modulus of the substrate and a coefficient of thermal expansion and modulus of the functional semiconductor die. Other related embodiments are disclosed.Type: ApplicationFiled: April 1, 2016Publication date: January 31, 2019Applicant: Intel CorporationInventors: Min-Tih LAI, Yuhong CAI
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Publication number: 20190035926Abstract: A replacement fin layer is deposited on a sub-fin layer in trenches isolated by an insulating layer on a substrate. The replacement fin layer has first component rich side portions and a second component rich core portion. The second component rich core portion is etched to generate a double fin structure comprising the first component rich fins.Type: ApplicationFiled: March 30, 2016Publication date: January 31, 2019Applicant: Intel CorporationInventors: Chandra S. MOHAPATRA, Glenn A. GLASS, Anand S. MURTHY, Karthik JAMBUNATHAN
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Publication number: 20190034763Abstract: Technology for a memory controller is described. The memory controller can receive a request to store training data. The request can include a model identifier (ID) that identifies a model that is associated with the training data. The memory controller can send a write request to store the training data associated with the model ID in a memory region in a pooled memory that is allocated for the model ID. The training data that is stored in the memory region in the pooled memory can be addressable based on the model ID.Type: ApplicationFiled: December 27, 2017Publication date: January 31, 2019Applicant: Intel CorporationInventors: FRANCESC GUIM BERNAT, KARTHIK KUMAR, MARK A. SCHMISSEUR, THOMAS WILLHALM
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Publication number: 20190035381Abstract: A mechanism is described for facilitating context-based cancellation and amplification of acoustical signals in acoustical environments according to one embodiment. An apparatus of embodiments, as described herein, includes detection and recognition logic to detect an acoustical signal being emitted by an acoustical signal source; evaluation, estimation, and footprint logic to classify the acoustical signal as an emergency acoustical signal or a non-emergency acoustical signal, wherein the classification is based on a footprint or a footprint identification (ID) associated with the acoustical signal; acoustical signal cancellation logic to cancel the acoustical signal if the acoustical signal is regarded as the non-emergency acoustical signal based on the footprint or the footprint ID; and acoustical signal amplification logic to amplify the acoustical signal if the acoustical signal is classified as the emergency acoustical signal based on the footprint or the footprint ID.Type: ApplicationFiled: December 27, 2017Publication date: January 31, 2019Applicant: Intel CorporationInventors: Przemyslaw Maziewski, Da-Ming Chiang, Shmuel Markovich Golan, Swarnendu Kar, Victoria Moore
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Publication number: 20190034917Abstract: Methods and systems are provided for tracking an electronic wallet (e-wallet) using radio frequency identification (RFID). An example apparatus includes a CPU package hosting an RFID device and a trusted platform module (TPM). The RFID device is configured to provide RFID values to an RFID reader from a device hosting an e-wallet share, wherein the RFID device comprises a flash memory to store an attestation key. The trusted platform module (TPM) is configured to provide the attestation key for signing the RFID values, e-wallet transactions, or location communications, or any combinations thereof, and create a trusted execute environment (TEE) for operation of a wallet app.Type: ApplicationFiled: December 29, 2017Publication date: January 31, 2019Applicant: INTEL CORPORATIONInventors: Michael Nolan, Davide Carboni, Ned M. Smith
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Publication number: 20190035437Abstract: Devices, systems, and methods having increased efficiency selective writing to memory are disclosed and described. A memory controller, upon receiving a dirty data segment, performs a read-modify-write to retrieve a corresponding data line from memory, saves a copy of the data line, merges the dirty data segment into the appropriate location in the data line to create a modified data line, and generates a write mask from the modified data line and the copy of the data line.Type: ApplicationFiled: December 28, 2017Publication date: January 31, 2019Applicant: Intel CorporationInventors: DAVID J. ZIMMERMAN, ROBERT M. ELLIS, RAJESH SUNDARAM
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Publication number: 20190037227Abstract: An apparatus of video encoding is described herein. The apparatus includes an encoder and a hardware bit packing unit. The encoder includes a fixed function hierarchical motion estimation search unit, fixed function integer motion estimation search units, and a fixed function check and refinement unit. The check and refinement unit is to generate residuals using nested loops based on at least one spatial domain prediction and at least one frequency domain prediction and perform a final mode decision based on rate distortion optimization (RDO) costs associated with the generated residuals. The hardware bit packing unit is to pack bits as coded according to the final mode decision into a data format.Type: ApplicationFiled: July 28, 2017Publication date: January 31, 2019Applicant: Intel CorporationInventors: James M. Holland, Srinivasan Embar Raghukrishnan, Lidong Xu, Fangwen Fu, Dmitry E. Ryzhov, Satya N. Yedidi
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Publication number: 20190036371Abstract: In one example an electronic device comprises at least one electronic component, a least one power storage device, and a chassis comprising a body formed from a rigid material and comprising a first pad coupled to the body by a first hinge, wherein the first pad is rotatable about the first hinge between a first position in which the first pad is closed and a second position in which the first pad is open, wherein the first pad comprises a first wireless power transmitting device. Other examples may be described.Type: ApplicationFiled: April 2, 2016Publication date: January 31, 2019Applicant: INTEL CORPORATIONInventors: Jeff KU, Gavin SUNG, Ivan WANG, Tim LIU, Jason Y. JIANG
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Publication number: 20190034920Abstract: Methods and systems are provided for a contextual authentication of an electronic wallet (e-wallet). An example apparatus includes a wallet application configured to confirm a context for use of an e-wallet, wherein the context is defined by a multifactor authentication (MFA) policy. A multifactor authentication application is configured to access a context sensor to provide input to the wallet application for the MFA policy.Type: ApplicationFiled: December 29, 2017Publication date: January 31, 2019Applicant: INTEL CORPORATIONInventors: Michael Nolan, Davide Carboni, Ned M. Smith
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Publication number: 20190035729Abstract: Semiconductor packages with programmable routing pathways are disclosed. The semiconductor package may have a source trace that may be electrically coupled to two or more different electrical pathways, where any of the electrical pathways may be activated to provide an electrical connection between the source trace and one or more destination nodes. Each of the electrical pathways may have a corresponding metal well with a correspond airgap overlying the metal well, as well as corresponding heating elements. If a particular heating element is energized, the heating element may melt metal in a corresponding metal well and the molten metal may migrate by capillary action into the overlying airgap to complete an electrical connection between the source trace and a destination node.Type: ApplicationFiled: March 31, 2016Publication date: January 31, 2019Applicant: INTEL CORPORATIONInventors: Russell S. AOKI, Dimitrios ZIAKAS
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Publication number: 20190028398Abstract: Described is a low latency re-timer for systems supporting spread spectrum clocking. The re-timer comprises: a first clock frequency estimator to estimate a frequency of a receive clock (RX CLK) and to provide a first timestamp associated with a first clock that underwent spread spectrum; a second clock frequency estimator to estimate a frequency of a transmit clock (TX CLK) and to provide a second timestamp associated with a second clock that underwent spread spectrum; and a comparator to compare the first timestamp with the second timestamp.Type: ApplicationFiled: September 24, 2018Publication date: January 24, 2019Applicant: Intel CorporationInventors: Ehud Udi SHOOR, Ari SHARON
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Publication number: 20190026709Abstract: In one embodiment, a trusted cloud service such as an “electronic vault” may store records of a consumer's electronic data file history. These documents may come from disparate providers and include financial statements and the like. The trusted vault cloud may act as an online notary to certify documents are legitimate and may be trusted. For example, a retailer may dispute whether the consumer paid a debt. To resolve the issue the retailer may access the cloud vault to retrieve a bank statement for the consumer, whereby the bank statement is electronically notarized by the vault cloud and is thus credible to the retailer. The retailer may then see proof the consumer had indeed paid a past debt to the retailer. Other embodiments are described herein.Type: ApplicationFiled: February 5, 2018Publication date: January 24, 2019Applicant: INTEL CORPORATIONInventor: Charles Baron