Abstract: A Land Grid Array (LGA) interface assembly used to physically interface or connect a semiconductor package (e.g., a semiconductor, a microprocessor, etc.) and a PCB, motherboard, etc. The LGA interface assembly including an LGA socket including a plurality of socket pins arranged and configured to contact a plurality of contact pads on the semiconductor package to enable data transfer. The socket pins including a multi-bend and/or zig-zag configuration arranged and configured to minimize lateral displacement of the socket pin relative to the contact pad during insertion of the semiconductor package into the LGA socket. Other embodiments are described and claimed.

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a at least one processor to perform operations to implement a neural network and compute logic to accelerate neural network computations.

Abstract: Techniques for forming a semiconductor device (such as a metal-semiconductor-metal device) within the interconnect region over a device layer (such as plurality of field effect transistor (FET) devices). An interconnect layer within a stack of interconnect layers includes a metal-semiconductor-metal (MSM) structure having a first metal layer, a semiconductor layer on the first metal layer, and a second metal layer on the semiconductor layer. The first metal layer may be directly on a first conductive layer of a lower interconnect layer (such as on a via or line of the lower interconnect layer). One or more other conductive layers may also be disposed between the first metal layer and the underlying first conductive layer. A second conductive layer may contact the top surface of the second metal layer.

Abstract: Described herein are inductor devices formed using wafer processing techniques. The inductor devices are singulated and can be mounted into different packages or computing systems. The magnetic material included in the inductor devices have higher aspect ratios (e.g., relatively tall and thin magnetic regions), which may be achieved using electroplating. The electroplated magnetic material is highly concentrated, which enables a higher inductance density.

Abstract: Techniques related to distributing the video encoding processing of an input video across hardware and software systems. Such techniques include evaluating the content of the video and determine whether or the encoding operation is best to be done on the hardware system only, software system only or a hybrid hardware and software system.

Abstract: Embodiments of apparatuses, methods, and systems for scalable multi-key memory encryption are disclosed. In an embodiment, an apparatus includes a core, an encryption unit, and key identification hardware. The core is to write data to and read data from memory regions, each to be identified by a corresponding address. The encryption unit to encrypt data to be written and decrypt data to be read. The key identification hardware is to use a portion of the corresponding address to look up a corresponding key identifier in a key information data structure. The corresponding key identifier is one multiple key identifiers. The corresponding key identifier is to identify which one of multiple encryption keys is to be used to encrypt and decrypt the data.

Abstract: Embodiments of apparatuses, methods, and systems for highly scalable accelerators are described. In an embodiment, an apparatus includes an interface to receive a plurality of work requests from a plurality of clients and a plurality of engines to perform the plurality of work requests. The work requests are to be dispatched to the plurality of engines from a plurality of work queues. The work queues are to store a work descriptor per work request. Each work descriptor is to include all information needed to perform a corresponding work request.

Abstract: One embodiment provides an apparatus comprising an interconnect fabric comprising a processing cluster including an array of multiprocessors coupled to an interconnect fabric, scheduling circuitry to distribute a plurality of thread groups across the array of multiprocessors, each thread group comprising a plurality of threads. A first multiprocessor of the array of multiprocessors can be assigned to process a first thread group comprising a first plurality of threads including a first thread sub-group and a second thread sub-group. The second thread sub-group has a data dependency on the first thread sub-group and the first multiprocessor includes circuitry to cause threads of the second thread sub-group to sleep until the threads of the first thread sub-group have satisfied the data dependency.

Abstract: A mechanism is described for facilitating slimming of neural networks in machine learning environments. A method of embodiments, as described herein, includes learning a first neural network associated with machine learning processes to be performed by a processor of a computing device, where learning includes analyzing a plurality of channels associated with one or more layers of the first neural network. The method may further include computing a plurality of scaling factors to be associated with the plurality of channels such that each channel is assigned a scaling factor, wherein each scaling factor to indicate relevance of a corresponding channel within the first neural network. The method may further include pruning the first neural network into a second neural network by removing one or more channels of the plurality of channels having low relevance as indicated by one or more scaling factors of the plurality of scaling factors assigned to the one or more channels.

Abstract: Metal oxide resist layers including bismuth and phosphorus, and related methods are disclosed herein. An example method of fabricating a semiconductor device, the method including depositing a metal oxide resist layer on a base material by applying a precursor including bismuth, the metal oxide resist layer including a bismuth phosphate compound and patterning the metal oxide resist layer.

Abstract: An example of an apparatus may include a processor to process request transactions and completion transactions for one or more respective communication protocols, memory coupled to the processor to store error-related transaction information, and circuitry coupled to the memory to save the error-related transaction information in the memory for both the request transactions and the completion transactions for the one or more respective communication protocols. Other examples are disclosed and claimed.

Abstract: Systems and methods for providing a high-resolution gaming experience on typical computer systems, including computer systems without high-end d-GPUs. In particular, systems and methods are provided for optimizing deep learning-based super-sampling methods. A hardware-aware optimization technique for super-sampling machine learning networks uses a subset of intermediate outputs of the machine learning model for the previous game frame for convolution operations on the current frame, thereby reducing compute usage and latency without sacrificing quality of the output. The inputs are concatenated and passed through a convolutional neural network (CNN), such as a U-net-based CNN. The output of the CNN is a high-resolution image frame that can be post-processed to generate a final output. The hardware optimization technique can be implemented in a neural network framework that divides the machine learning inference across available compute resources on the computer platform.

Abstract: This disclosure describes systems, methods, and devices related to enhanced ranging. A device may initiate a ranging sequence by transmitting an NDPA frame followed by an I2R NDP frame. The device may receive a corresponding R2I NDP frame and an R2I LMR from a responding station. The device may repeat the ranging sequence for two or more iterations to collect multiple data sets. The device may process the R2I NDP frame and the R2I LMR to generate continuous ToA and ToD measurements for each iteration.

Abstract: Techniques related to quantization parameter estimation for coding intra and scene change frames are discussed. Such techniques include generating features based on an intra or scene change frame including a proportion of smooth blocks and one or both of a measure of block variance and a prediction distortion, and applying a machine learning model to generate an estimated quantization parameter for encoding the intra or scene change frame.

Abstract: Techniques and mechanisms for an integrated circuit (IC) die to support in-field testing and/or repair of a lane in a three-dimensional (3D) IC which is formed with multiple IC dies. In an embodiment, the 3D IC comprises test units which each correspond to a different partition comprising respective circuit resources. During in-field operation of the 3D IC, a given test unit is operable to detect both a first condition wherein two partitions are each in an idle state, and a second condition wherein a first link between the two partitions fails to satisfy a performance criteria. The idle states are indicated by a power management controller (PMC) agent during runtime operation of the 3D IC. In another embodiment, one or more test units configure an operational mode, based on the detected conditions, to substitute communication via the first lane with communication via a repair lane.

Abstract: Methods and apparatus to mitigate cracking in glass cores are disclosed. An example apparatus comprises a glass core having an opening extending between opposing surfaces of the glass core, and a metal within the opening. a gap between an interface of the metal and a sidewall of the opening.

Abstract: An example apparatus to perform a convolution on an input tensor includes a parameters generator to: generate a horizontal hardware execution parameter for a horizontal dimension of the input tensor based on a kernel parameter and a layer parameter; and generate a vertical hardware execution parameter for a vertical dimension of the input tensor based on the kernel parameter and the layer parameter; an accelerator interface to configure a hardware accelerator circuitry based on the horizontal and vertical hardware execution parameters; a horizontal Iterator controller to determine when the hardware accelerator circuitry completes the first horizontal iteration of the convolution; and a vertical Iterator controller to determine when the hardware accelerator circuitry completes the first vertical iteration of the convolution.

Abstract: Techniques related to compressing a pre-trained dense deep neural network to a sparsely connected deep neural network for efficient implementation are discussed. Such techniques may include iteratively pruning and splicing available connections between adjacent layers of the deep neural network and updating weights corresponding to both currently disconnected and currently connected connections between the adjacent layers.

Abstract: This disclosure describes systems, methods, and devices related to enhanced capability advertising. A device may send a Beacon frame or a Probe Response frame on a legacy band, including an enhanced Security Element containing one or more fields of an original robust security network element (RSNE). The device may override at least one of the one or more fields from the enhanced Security Element over corresponding fields in the original RSNE during a connection establishment process with a peer device.

Abstract: Embodiments are generally directed to multi-tile graphics processor rendering. An embodiment of an apparatus includes a memory for storage of data; and one or more processors including a graphics processing unit (GPU) to process data, wherein the GPU includes a plurality of GPU tiles, wherein, upon geometric data being assigned to each of a plurality of screen tiles, the apparatus is to transfer the geometric data to the plurality of GPU tiles.

Abstract: Apparatus, systems, methods, and articles of manufacture are disclosed for acoustic signal processing adaptive to microphone distances. An example system includes a microphone to convert an acoustic signal to an electrical signal and one or more processors to: estimate a distance between a source of the acoustic signal and the microphone; select a signal processing mode based on the distance; and process the electrical signal in accordance with the selected processing mode.

Abstract: A system, method and computer readable medium for dynamic noise reduction in a voice call. The system includes an encoder having a short-time Fourier transform module to determine a magnitude spectrum and a phase spectrum of an input audio signal. The input audio signal includes speech and dynamic noise. A separator is coupled to the encoder. The separator comprises a temporal convolution network (TCN) used to develop a separation mask using the magnitude spectrum as input. The TCN is trained using a frequency SNR function used to calculate loss during training. A mixer is coupled to the separator to multiply the separation mask with the magnitude spectrum to separate the speech from the dynamic noise to obtain a denoise magnitude spectrum. The system also includes a decoder coupled to the mixer and the encoder. The decoder includes an inverse short-time Fourier transform module to reconstruct the input audio signal without the dynamic noise using the denoise magnitude spectrum and the phase spectrum.

Abstract: Techniques related to adaptive quality boosting for low latency video coding are discussed. Such techniques include segmenting each of a number of temporally adjacent video frames into unique high encode quality regions and encoding each of the video frames by applying a coding quality boost to the high encode quality regions relative to other regions of the video frames.

Abstract: In an illustrative embodiment, mechanical adhesive and a separate index-matching material are used as underfill between a photonic integrated circuit (PIC) die and an optical interposer. The index-matching material reduces coupling loss between waveguides of the PIC die and waveguides of the optical interposer, while the mechanical adhesive secures the optical interposer in place. The mechanical adhesive can be thermally cured, have a low coefficient of thermal expansion (CTE), have high viscosity, and have a relatively high optical transmission loss. The index-matching material can have low optical transmission loss, be UV cured, have a relatively high CTE, and have low viscosity. The combination of mechanical adhesive and index-matching material can improve ease of manufacture and yield. Additional features are disclosed, such as V-groove arrays in the optical interposer and the PIC die that have low stress and trenches and walls to control flow of the mechanical adhesive and/or index-matching material.

Abstract: This disclosure describes systems, methods, and devices related to sensing authorization. A device may transmit a request for sensing services to a network, the request including one or more parameters related to sensing. The device may receive an authorization response from the network based on a UE's subscription status and privacy settings. The device may execute sensing functions locally on the UE upon receiving authorization from the network. The device may transmit sensing data to the network for exposure to authorized clients. The device may update a UE's privacy profile related to sensing data via a communication with a network function.

Abstract: A tunable edge-coupled interface for photonic integrated circuits (PICs). The architecture can be identified by (1) an edge interface for optical coupling that exhibits a gap between an oxide cladding layer and the silicon substrate of the PIC die, (2) a perforated beam region above the gap in the oxide layer, wherein waveguide beams in the beam region provide a respective optical path for waveguides of the PIC, (3) actuator beams flanking the waveguide beams, the actuator beams include a heating element and are operated to tune the edge interface by inducing deflection of the edge interface, and (4) an application-specific target pitch of waveguides on the edge interface.

Abstract: Integrated photonic devices, packages, and systems are disclosed. An example photonic device includes a laser device with a laser cavity having three sections. The three sections include, respectively, an active region, a waveguide, and a grating arranged along a longitudinal axis of the cavity. Materials of these three sections of the laser device are selected so that a TOC of the grating is between a TOC of the active region and a TOC of the waveguide.

Abstract: This disclosure describes systems, methods, and devices related to enhanced video coding. A device may receive encoded bitstream data of a frame with multiple tiles. The device may divide each tile into multiple coding tree units (CTUs). The device may decode Luma and Chroma pixels of each CTU using either a single-tree mode or a dual-tree mode. The device may execute a cross-component linear model (CCLM) prediction to predict Chroma pixels based on decoded Luma pixels. The device may store the decoded Luma pixels and the predicted Chroma pixels in a storage.

Abstract: Described herein is a graphics processor comprising a memory interface and a graphics processing cluster coupled with the memory interface. The graphics processing cluster includes a plurality of processing resources. A processing resource of the plurality of processing resources includes a source crossbar communicatively coupled with a register file, the source crossbar to reorder data elements of a source operand and a format conversion pipeline to convert a plurality of input data elements specified by the source operand from a first format of a plurality of datatype formats to a second format of the plurality of datatype formats, the plurality of datatype formats including integer and floating-point formats.

Abstract: This disclosure describes systems, methods, and devices for remotely controlling device settings for collaboration sessions. A device may identify an alphanumeric handle based on a location identifier of a first location associated with the device and a collaboration session identifier for a collaboration session of a collaboration application executed by the device; generate a Bluetooth Low Energy (BLE) advertising packet including a header and a payload, the header including the alphanumeric handle and a hardware identifier that identifies the device; transmit the BLE advertising packet; identify an authentication request received from a second device in the collaboration session, the authentication request including the alphanumeric handle; authenticate the second device based on the alphanumeric handle; and transmit a BLE notification packet including an indication of a volume at which the second device is to set a speaker for the collaboration session.

Abstract: This disclosure describes systems, methods, and devices related to enhanced wireless frame security. A device may utilize a Galois Message Authentication Code with a 256-bit key (GMAC-256) as an integrity protocol for block acknowledgment (BA) and block acknowledgment request (BAR). The device may generate a packet number (PN) and Message Integrity Code (MIC) using GMAC-256 for integrity design in the BA and BAR. The device may include a key identification (ID) indication in a BA control or BAR control field for the BA and BAR.

Abstract: Disclosed herein are embodiments of a broadband wavemeter system comprising: a laser source to generate an optical signal having one or more wavelengths; a tap to separate a portion of the optical signal from the laser source; a splitter to split an incoming optical signal from the tap into a plurality of outgoing optical signals; a plurality of wavemeters, each one in the plurality to receive one of the outgoing optical signals from the splitter, in which each wavemeter in the plurality of wavemeters comprises a Mach-Zehnder Interferometer (MZI), and each wavemeter has at least one of free spectral range (FSR) detuning and center wavelength detuning, and a control circuit to collate outputs from individual ones of the plurality of wavemeters to monitor, detect and control the laser source.

Abstract: Disclosed herein are embodiments of a waveguide structure, comprising: a deep rib waveguide on a slab and a plurality of shallow rib waveguides on the slab. The deep rib waveguide has a first etch-depth, the plurality of shallow rib waveguides has a second etch-depth, and the first etch-depth is greater than the second etch-depth.

Abstract: Described herein is a graphics processor comprising a memory interface and a graphics processing cluster coupled with the memory interface. The graphics processing cluster includes a multi-lane parallel floating-point unit and a multi-lane parallel integer unit. The multi-lane parallel integer unit includes an integer pipeline including a plurality of parallel integer logic units configured to perform integer compute operations on a plurality of input data elements and a format conversion pipeline including a plurality of parallel format conversion units configured to convert a plurality of input data elements from a first one of a plurality of datatype formats to a second one of the plurality of datatype formats, the plurality of datatype formats including integer and floating-point formats.

Abstract: A compute system that includes an Internet of things (IoT) device is provided. The IoT device includes a common services interface (CSI) to create a self-managing network of devices with other nodes comprising the CSI.

Abstract: An apparatus to facilitate thread scheduling is disclosed. The apparatus includes logic to store barrier usage data based on a magnitude of barrier messages in an application kernel and a scheduler to schedule execution of threads across a plurality of multiprocessors based on the barrier usage data.

Abstract: Embodiments are generally directed to compression for compression for sparse data structures utilizing mode search approximation. An embodiment of an apparatus includes one or more processors including a graphics processor to process data; and a memory for storage of data, including compressed data. The one or more processors are to provide for compression of a data structure, including identification of a mode in the data structure, the data structure including a plurality of values and the mode being a most repeated value in a data structure, wherein identification of the mode includes application of a mode approximation operation, and encoding of an output vector to include the identified mode, a significance map to indicate locations at which the mode is present in the data structure, and remaining uncompressed data from the data structure.

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed to evict tokens from a key value cache. An example apparatus includes interface circuitry, machine readable instructions, and programmable circuitry to at least one of instantiate or execute the machine readable instructions to: determine score history values for tokens based on attention scores associated with the tokens, wherein a token is a numerical representation of text, after a number of tokens present in the key value cache exceeds a threshold number of tokens, compute group importance scores for groups of tokens based on score history values of the tokens in the groups of tokens, identify low-ranked groups of tokens having lowest group importance scores, the low-ranked groups of tokens associated with an eviction range in the key value cache, and remove an identified low-ranked group of tokens from the eviction range of the key value cache.

Abstract: A system, article, device, apparatus, and method of audio processing comprises receiving, by processor circuitry, audible audio signal data of intermodulation distortion products (IDPs) based on ultrasonic audio signals received by at least one microphone of an audio device. The method also compares the audible audio signal data to ultrasonic audio signal data of the ultrasonic audio signals. Thereafter, the method determines a plurality of susceptibility values each of a different ultrasonic frequency based on the comparing, wherein the plurality of susceptibility values represent an ultrasonic attack susceptibility of the audio device.

Abstract: An apparatus is disclosed that includes a network interface device comprising processors to implement network interface device functionality and communication protocol engine circuitry, wherein the network interface device is to: receive a request to write data to a memory node communicably coupled to the network interface device; identify network information corresponding to the request, wherein the network information includes at least one of quality of service (QoS), physical function (PF), virtual function (VF), name space identifier (NSID), flow ID, service level objectives (SLOs), or process address space ID (PASID); identify characteristics of the memory node, wherein the characteristics include at least page size of the memory node; and cause the data to be coalesced with other data on the memory node based on the network information and the characteristics.

Abstract: Embodiments of the present disclosure are directed toward techniques and configurations enhancing the performance of hardware (HW) accelerators. Disclosed embodiments include static MAC scaling arrangement, which includes architectures and techniques for scaling the performance per unit of power and performance per area of HW accelerators. Disclosed embodiments also include dynamic MAC scaling arrangement, which includes architectures and techniques for dynamically scaling the number of active multiply-and-accumulate (MAC) within an HW accelerator based on activation and weight sparsity. Other embodiments may be described and/or claimed.

Abstract: Described herein is a graphics processor comprising an instruction cache and a plurality of processing elements coupled with the instruction cache. The plurality of processing elements include functional units configured to provide an integer pipeline to execute instructions to perform operations on integer data elements. The integer pipeline including a first multiplier and a second multiplier, the first multiplier and the second multiplier configured to execute operations for a single instruction.

Abstract: Systems, apparatuses and methods may provide for technology that selects an anti-aliasing mode for a vertex of a primitive based on a parameter associated with the vertex and generates a coverage mask based on the selected anti-aliasing mode. Additionally, one or more pixels corresponding to the vertex may be shaded based at least partly on the coverage mask, wherein the selected anti-aliasing mode varies across a plurality of vertices in the primitive.

Abstract: In an example, an apparatus comprises a plurality of compute engines; and logic, at least partially including hardware logic, to detect a cache line conflict in a last-level cache (LLC) communicatively coupled to the plurality of compute engines; and implement context-based eviction policy to determine a cache way in the cache to evict in order to resolve the cache line conflict. Other embodiments are also disclosed and claimed.

Abstract: An integrated circuit includes protected container access control logic to perform a set of access control checks and to determine whether to allow a device protected container module (DPCM) and an input and/or output (I/O) device to communicate securely through one of direct memory access (DMA) and memory-mapped input/output (MMIO). The DPCM and the I/O device are allowed to communicate securely if it is determined that at least the DPCM and the I/O device are mapped to one another, an access address associated with the communication resolves into a protected container memory, and a page of the protected container memory into which the access address resolves allows for the aforementioned one of DMA and MMIO. In some cases, a Security Attributes of Initiator (SAI) or security identifier may be used to obtain a DPCM identifier or attest that access is from a DPCM mapped to the I/O device.

Abstract: Embodiments of the present disclosure are directed toward techniques and configurations enhancing the performance of hardware (HW) accelerators. The present disclosure provides a schedule-aware, dynamically reconfigurable, tree-based partial sum accumulator architecture for HW accelerators, wherein the depth of an adder tree in the HW accelerator is dynamically based on a dataflow schedule generated by a compiler. The adder tree depth is adjusted on a per-layer basis at runtime. Configuration registers, programmed via software, dynamically alter the adder tree depth for partial sum accumulation based on the dataflow schedule. By facilitating a variable depth adder tree during runtime, the compiler can choose a compute optimal dataflow schedule that minimizes the number of compute cycles needed to accumulate partial sums across multiple processing elements (PEs) within a PE array of a HW accelerator. Other embodiments may be described and/or claimed.

Abstract: Monolithic two-dimensional (2D) arrays of double-sided DRAM cells including a frontside bit cell over a backside bit cell. Each double-sided cell includes a stacked transistor structure having at least a first transistor over a second transistor. Each double-sided cell further includes a first capacitor on a frontside of the stacked transistor structure and electrically coupled to a source/drain of the first transistor. Each double-sided cell further includes a second capacitor on a backside of the stacked transistor structure and electrically coupled to a source/drain of the second transistor. Frontside cell addressing interconnects are electrically coupled to other terminals of at least the first transistor while one or more backside addressing interconnects are electrically coupled to at least one terminal of the second transistor or second capacitor.

Abstract: Systems and methods for super sampling and viewport shifting of non-real time 3D applications are disclosed. In one embodiment, a graphics processing unit includes a processing resource to execute graphics commands to provide graphics for an application, a capture tool to capture the graphics commands, and a data generator to generate a dataset including at least one frame based on the captured graphics commands and to modify viewport settings for each frame of interest to generate a conditioned dataset.

Abstract: Methods for fabricating an IC structure, e.g., for fabricating a metallization stack portion of an IC structure, as well as related semiconductor devices, are disclosed. An example fabrication method includes splitting metal lines that are supposed to be included at a tight pitch in a single metallization layer into two vertically-stacked layers (hence the term “vertical metal splitting”) by using helmets and wrap-around dielectric spacers. Metal lines split into two such layers may be arranged at a looser pitch in each layer, compared to the pitch at which metal lines of the same size would have to be arranged if there were included in a single layer. Increasing the pitch of metal lines may advantageously allow decreasing the parasitic metal-to-metal capacitance associated with the metallization stack.

Abstract: Embodiments described herein include software, firmware, and hardware that provides techniques to enable deterministic scheduling across multiple general-purpose graphics processing units. One embodiment provides a multi-GPU architecture with uniform latency. One embodiment provides techniques to distribute memory output based on memory chip thermals. One embodiment provides techniques to enable thermally aware workload scheduling. One embodiment provides techniques to enable end to end contracts for workload scheduling on multiple GPUs.