Intel Patents
Intel Corporation designs and manufactures microprocessors and chipsets for computing and communications equipment manufacturers. Its products may be found in desktops, servers, tablets, smartphones and other devices.
Intel Patents by Type- Intel Patents Granted: Intel patents that have been granted by the United States Patent and Trademark Office (USPTO).
- Intel Patent Applications: Intel patent applications that are pending before the United States Patent and Trademark Office (USPTO).
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Patent number: 7019550Abstract: A method includes providing a device under test (DUT) which has an input port and an output port. The DUT also has a squelch detector which is coupled to receive a signal from the input port. The DUT also has a receiver amplifier coupled to receive a signal from the input port. In addition, the DUT also has a transmitter to transmit data signals from the output port. The method further includes providing a loopback connection from the output port to the differential input port. The method also includes controlling the transmitter to transmit a test signal from the output port to the input port. The method includes monitoring at least one of respective outputs of the receiver amplifier and the squelch detector to determine whether a leakage condition exists in the DUT. Other embodiments are described and claimed.Type: GrantFiled: June 29, 2004Date of Patent: March 28, 2006Assignee: Intel CorporationInventors: Eric R. Wehage, Anne Meixner, Kersi H. Vakil
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Patent number: 7020747Abstract: Briefly, embodiments of the invention provide an architecture including two or more stack memories defined on separate memory banks. An apparatus in accordance with embodiments of the invention may include, for example, a processor associated with two stack memories defined on separate single-access memory banks. Embodiments of the invention further provide a method of compilation including, for example, allocating a first variable to a first memory bank and allocating a second variable to a stack memory defined on a second memory bank.Type: GrantFiled: March 31, 2003Date of Patent: March 28, 2006Assignee: Intel CorporationInventor: Omry Paiss
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Patent number: 7020223Abstract: In a Viterbi decoder, 2n-way add-compare-select (ACS) operations are performed by sequential and/or parallel two-way ACS operations. In one embodiment, first two-way ACS operations generate an interim path metric for each of a plurality of interim states. Second two-way ACS operations generate a path metric for each of a plurality of next states. This process may be repeating for subsequent groups of bits to generate branch transitions through a trellis. A path having a lowest path metric may be selected and a decoded bit sequence determined based on the selected path. In generating the decoded bit sequence, the interim states of the selected path do not have to be used for code rates k/n when k is two or greater. The interim states may be used for code rates k/n when k=1.Type: GrantFiled: April 16, 2002Date of Patent: March 28, 2006Assignee: Intel CorporationInventor: Maximino Vasquez
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Patent number: 7019326Abstract: Various methods for forming a layer of strained silicon in a channel region of a device and devices constructed according to the disclosed methods. In one embodiment, a strain-inducing layer is formed, a relaxed layer is formed on the strain-inducing layer, a portion of the strain-inducing layer is removed, which allows the strain-inducing layer to relax and strain the relaxed layer.Type: GrantFiled: November 14, 2003Date of Patent: March 28, 2006Assignee: Intel CorporationInventors: Stephen M. Cea, Ravindra Soman, Ramune Nagisetty, Sunit Tyagi, Sanjay Natarajan
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Patent number: 7020818Abstract: Embodiments include an on die termination circuit. The on die termination circuit may be programmable. The on die termination circuit may be programmed to compensate for environmental conditions and the physical characteristics of the device. The programmed on die termination circuit allows for faster transfer rates over communication lines by reducing the time needed to recover from signal reflection and similar issues.Type: GrantFiled: March 8, 2004Date of Patent: March 28, 2006Assignee: Intel CorporationInventors: Navneet Dour, Roger K. Cheng
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Patent number: 7019928Abstract: The present disclosure relates to mass storage devices and, more particularly, to transferring data between mass storage devices.Type: GrantFiled: July 6, 2001Date of Patent: March 28, 2006Assignee: Intel CorporationInventor: Pedro E. Fajardo
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Patent number: 7020893Abstract: A broadcast method and system for continuously and opportunistically driving an optimal broadcast schedule based on most recent client demand feedback from a distributed set of broadcast clients. The broadcast system includes an operation center that broadcasts meta-data to a plurality of client systems. The meta-data describes a plurality of pieces of content that are in consideration for upcoming broadcasts by the server. Each client receives the broadcasted meta-data from and sends back a set of client demand feedback data to the operations center, wherein the user feedback data reflects a client's interest level in at least a portion of the pieces of content. The feedback data, which typically may include ratings and/or relative rankings, may be user-generated, automatically-generated, or a combination of the two. The system then determines a most opportunistic piece of content to be broadcast based on an aggregation of the client demand feedback data.Type: GrantFiled: June 15, 2001Date of Patent: March 28, 2006Assignee: Intel CorporationInventor: Jay H. Connelly
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Patent number: 7018920Abstract: A composite sacrificial material is deposited in a void or opening in a dielectric layer on a semiconductor substrate. The composite sacrificial material includes a polymeric or oligomeric matrix with filler material mixed therein. The filler material may be particulate matter that may be used to modify one or more properties of the composite sacrificial material during semiconductor processing.Type: GrantFiled: November 10, 2004Date of Patent: March 28, 2006Assignee: Intel CorporationInventors: Robert P. Meagley, Michael D. Goodner
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Patent number: 7020603Abstract: A system and method of encoding an audio stream includes generation of a distortion threshold templates database that is accessible by a perceptual audio encoder. The audio encoder utilizes the threshold templates to operate a compression algorithm, obviating the need to implement a psycho-acoustic model to generate a distortion threshold for each compression operation. A similar templates database may be used in a transcoding operation, again bypassing a psycho-acoustic modeling operation and promoting system efficiency.Type: GrantFiled: February 7, 2002Date of Patent: March 28, 2006Assignee: Intel CorporationInventor: Alex A Lopez-Estrada
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Patent number: 7020177Abstract: Briefly, in accordance with an embodiment of the invention, a method and apparatus to transfer information is provided, wherein the method includes transferring information between at least two wireless devices using a waveform that includes a first sinusoidal signal and a second sinusoidal signal, wherein the second sinusoidal signal has more zero-crossings than the first signal and wherein a duration of the first sinusoidal signal is less than a duration of the second sinusoidal signal.Type: GrantFiled: October 1, 2002Date of Patent: March 28, 2006Assignee: Intel CorporationInventors: David G. Leeper, David G. England
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Patent number: 7019884Abstract: A spatial light modulator is adapted to receive bidirectional drive signals.Type: GrantFiled: March 31, 2003Date of Patent: March 28, 2006Assignee: Intel CorporationInventors: Steven J. Kirch, Kenneth E. Salsman, Thomas E. Willis, Oleg Rashkovskiy
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Patent number: 7020873Abstract: An apparatus and method for vectorization of detected saturation and clipping operations in serial code loops of a source program are described. In one embodiment, the method includes the analysis of source program code to identify source code utilizing conditional constructs to perform saturation/clipping operations. Once analysis is complete, identified source code is vectorized to implement identified saturation/clipping operations utilizing single instruction, multiple data (SIMD) saturation/clipping instructions. Accordingly, utilizing embodiments of the present invention, conditional statements utilized to implement saturation arithmetic, as well as clipping of data values, such as pixel values within graphics applications, are replaced with SIMD saturation arithmetic instructions, as well as clipping instructions.Type: GrantFiled: June 21, 2002Date of Patent: March 28, 2006Assignee: Intel CorporationInventors: Aart J. C. Bik, Milind Girkar
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Patent number: 7018549Abstract: A method is described for fabricating multiple nanowires of uniform length from a single precursor nucleation particle. The method includes growing a first nanowire segment from a nanoparticle and growing a second nanowire segment between the first nanowire segment and the nanoparticle. The first nanowire segment and the second nanowire segment have a different solubility.Type: GrantFiled: December 29, 2003Date of Patent: March 28, 2006Assignee: Intel CorporationInventors: Matthew V. Metz, Scott A. Hareland, Robert S. Chau
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Patent number: 7020738Abstract: One embodiment of the invention is method for resolving address space conflicts between a virtual machine monitor and a guest operating system. The method includes allocating an address space for the operating system and an address space for the monitor. The method also includes mapping a portion of the monitor into the address space allocated for the operating system and the address space allocated for the monitor, and locating another portion of the monitor in the address space allocated for the monitor. The method also includes detecting that the operating system attempts to access a region occupied by the portion of the monitor within the address space allocated for the operating system, and relocating that portion of the monitor within that address space to allow the operating system to access the region previously occupied by that portion of the monitor.Type: GrantFiled: September 30, 2003Date of Patent: March 28, 2006Assignee: Intel CorporationInventors: Gilbert Neiger, Stephen Chou, Erik Cota-Robles, Stalinselvaraj Jevasingh, Alain Kagi, Michael Kozuch, Richard Uhlig, Sebastian Schoenberg
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Patent number: 7019907Abstract: An integrated multi-channel transmitter for fiber optic applications is disclosed. The transmitter includes a laser array coupled to a modulator chip by way of an isolator sandwiched between two lenslet arrays. The modulator chip includes an array of modulators, with each one receiving the output of one of the lasers. The chip also includes a coupler that receives the outputs from the modulators and combines them into a single, combined output signal which, in turn, may be coupled an output fiber.Type: GrantFiled: November 25, 2003Date of Patent: March 28, 2006Assignee: Intel CorporationInventor: Jean-Marc Verdiell
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Patent number: 7020246Abstract: An apparatus and technique for determining whether a telephone loop is capable of carrying a Digital Subscriber Line (DSL) signal. Time domain reflected (TDR) signals that are echoes of transmit impulse signals are processed using time domain echo averaging and echo enhancement using second-order statistics. Each technique allows clearer visualization of the TDR echo signal by reducing the noise and distortion present in the TDR signals. These statistical signal processing techniques allow determination of telephone loop characteristics such as loop length once the TDR echo signal amplitude and time index are calculated.Type: GrantFiled: June 30, 2003Date of Patent: March 28, 2006Assignee: Intel CorporationInventors: Xiao M. Gao, Wesley H. Smith, Veda Krishnan, Kanna Krishnan
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Patent number: 7020724Abstract: A streaming direct memory access (DMA) engine is disclosed. The streaming DMA engine includes several power reduction capabilities. A controller throttles the DMA engine according to the system throughput requirement and the system processor operation state. The DMA engine holds off a new read request to the memory if the data present in the DMA engine requires re-transmission. The DMA engine holds off a new write request to the memory if the data present in the DMA engine is corrupted, until the corrupted data is discarded.Type: GrantFiled: September 28, 2001Date of Patent: March 28, 2006Assignee: Intel CorporationInventors: David Emerson, Seh Kwa
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Patent number: 7019971Abstract: Apparatus and methods for providing self-contained, closed-loop microchannel cooling systems that can be integrated into a micro-component package, such as a microelectronic package, are described herein.Type: GrantFiled: September 30, 2003Date of Patent: March 28, 2006Assignee: Intel CorporationInventors: Sabina Houle, James C. Matayabas, Jr.
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Patent number: 7020041Abstract: An apparatus and method are provided for limiting a drop of a supply voltage in an SRAM device to retain the state of the memory during an IDLE state. The apparatus may include a memory array, a sleep device, and a clamping circuit. The clamping circuit may be configured to activate the sleep device when a voltage drop across the memory array falls below a preset voltage and the memory array is in an IDLE state.Type: GrantFiled: December 18, 2003Date of Patent: March 28, 2006Assignee: Intel CorporationInventors: Dinesh Somasekhar, Muhammad M. Khellah, Yibin Ye, Vivek K. De, James W. Tschanz, Stephen H. Tang
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Patent number: 7020792Abstract: A method and apparatus is described that may be utilized to equalize modal velocity changes on a data bus. Modal velocity changes may be equalized by use of variable delays that may be used to equalize modal velocity changes.Type: GrantFiled: April 30, 2002Date of Patent: March 28, 2006Assignee: Intel CorporationInventor: Stephen H. Hall
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Patent number: 7019346Abstract: A structure and method including an anodic metal oxide substrate used to form a capacitor are described herein.Type: GrantFiled: December 23, 2003Date of Patent: March 28, 2006Assignee: Intel CorporationInventor: Larry E. Mosley
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Patent number: 7018853Abstract: The present invention relates to a ferroelectric polymer storage device including at least two stacked ferroelectric polymer memory structures that are arrayed next to at least two respective stacked topologies that are a pre-fabricated silicon substrate cavity that includes interlayer dielectric layers and via structures.Type: GrantFiled: August 29, 2003Date of Patent: March 28, 2006Assignee: Intel CorporationInventors: Jian Li, Xiao-Chun Mu
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Patent number: 7020705Abstract: In a protocol providing for authentication to a first security realm, but failing to provide for a logout operation to de-authenticate from the first security realm, a logout operation is effected by providing a logout button, hyperlink, or other linking construct that causes a user to be transparently authenticated to a second security realm. For example, with respect to HTTP basic authentication, authentication with the second security realm removes, or logs out, the user from the first security realm.Type: GrantFiled: April 26, 2001Date of Patent: March 28, 2006Assignee: Intel CorporationInventors: Bing Wang, Jessica Zhang
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Patent number: 7020363Abstract: A first optical probe is used to test a planar lightwave circuit. In one embodiment, a second probe is used in combination with the first probe to test the planar lightwave circuit by sending and receiving a light beam through the planar lightwave circuit.Type: GrantFiled: December 28, 2001Date of Patent: March 28, 2006Assignee: Intel CorporationInventor: Kjetil Johannessen
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Patent number: 7020891Abstract: A device is provided that includes a first processor connected to a communications channel device. The communications device is capable of receiving and transmitting information to a video-on-demand (VOD) service provider. A VOD content decoder is provided that is conencted to the first processor. A video and audio formatting processor is provided that is connected to the first processor and the content decoder. An index memory is provided that is connected to the first processor. The index memory stores a plurality of VOD program segment representations of either whole VOD program content or partial VOD program content. Also provided is a method that includes selecting a start and stop time for recording a representation of a segment of at least one VOD program. The method also includes converting a VOD program identifier of at least one VOD program to a text representation.Type: GrantFiled: September 28, 2000Date of Patent: March 28, 2006Assignee: Intel CorporationInventor: Louis A. Lippincott
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Patent number: 7018095Abstract: A circuit for sensing on-die temperature at multiple locations using a minimum number of pins is described. Thermal diodes coupled to pins are placed on a die to measure the temperature at various die locations. Voltage is applied to the pins to determine the temperature at each given diode location. The polarity of the voltage applied across the pins determines what diodes are selected for measurement.Type: GrantFiled: June 27, 2002Date of Patent: March 28, 2006Assignee: Intel CorporationInventors: Dean J. Grannes, Harjinder Singh, Jason A. Gayman
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Patent number: 7020709Abstract: A system is described comprising: a primary root splitter to split a data stream transmitted from an upstream server into a plurality of leaf splitter streams; a plurality of leaf splitters to split each of the leaf splitter streams into a plurality of end user streams, wherein one or more of the plurality of leaf splitters is a backup root splitter; and root splitter reassignment logic for reassigning one of the backup root splitters as a new primary root splitter responsive to detecting a problem with the primary root splitter. Also described is a method comprising: monitoring a primary root splitter to ensure that the primary root splitter is operating within predefined parameters, the primary root splitter to split a single data stream into multiple data streams transmitted to multiple leaf splitters; and reassigning one of the leaf splitters as a new primary root splitter responsive to detecting that the primary root splitter is not operating within the predefined parameters.Type: GrantFiled: June 30, 2000Date of Patent: March 28, 2006Assignee: Intel CorporationInventor: Reed J. Sloss
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Patent number: 7018058Abstract: A reflector, light source, phase retarder, and linear polarizer configured to increase a single-polarization output beam by converting wrong-polarization light into correct-polarization light. The linear polarizer reflects the wrong-polarization light and transmits the correct-polarization light. The phase retarder converts the wrong-polarization light into correct-polarization light, which is then transmitted by the linear polarizer.Type: GrantFiled: July 22, 2005Date of Patent: March 28, 2006Assignee: Intel CorporationInventors: Michael O'Connor, Clark A. Pentico
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Patent number: 7020093Abstract: A method for evaluating an end-user's subjective assessment of streaming media quality includes obtaining reference data characterizing the media stream, and obtaining altered data characterizing the media stream after the media stream has traversed a channel that includes a network. An objective measure of the QOS of the media stream is then determined by comparing the reference data and the altered data.Type: GrantFiled: May 30, 2001Date of Patent: March 28, 2006Assignee: Intel CorporationInventors: Sudheer Sirivara, Jeffrey Mcveigh, Robert J. Reese, Gianni G. Ferrise, Phillip G. Austin, Ram R. Rao, Shobhana Subramanian
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Patent number: 7020810Abstract: System and methods for propagating error status over an error checking and correcting (ECC) protected channel. A first device receives data and an error status associated with the data. The first device generates check bits for the data based on a first ECC code and combines the check bits with the data to form one or more code words. The first device sends the code words across the channel where the first device inserts a triple error into a nibble of at least one codeword sent if the error status indicated an uncorrectable error. A second device connected to the channel receives the code words sent across the channel. The second device detects triple errors within a nibble of any code word and any other single error in the code word using a second ECC code, where the second ECC code is the first ECC code with columns for check bits inserted.Type: GrantFiled: July 10, 2003Date of Patent: March 28, 2006Assignee: Intel CorporationInventor: Thomas J. Holman
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Patent number: 7020789Abstract: In some embodiments of the present invention, one or more elements of a processor core may receive a signal indicating that operands of a micro-instruction are narrow, for example less than or equal to 32 bits. In response to this signal, one or more components of a processor core element that are able to handle more than 32 bits of data (e.g. operands or results) may function as though they handle only 32 bits of data.Type: GrantFiled: December 31, 2002Date of Patent: March 28, 2006Assignee: Intel CorporationInventors: Zeev Sperber, Ittai Anati, Yuval Bustan, Sagi Lahav
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Patent number: 7018918Abstract: An inter-layer dielectric structure and method of making such structure are disclosed. A composite dielectric layer, initially comprising a porous matrix and a porogen, is formed. Subsequent to other processing treatments, the porogen is decomposed and removed from at least a portion of the porous matrix, leaving voids defined by the porous matrix in areas previously occupied by the porogen. The resultant structure has a desirably low k value as a result of the porosity and materials comprising the porous matrix and porogen. The composite dielectric layer may be used in concert with other dielectric layers of varying porosity, dimensions, and material properties to provide varied mechanical and electrical performance profiles.Type: GrantFiled: November 3, 2003Date of Patent: March 28, 2006Assignee: Intel CorporationInventors: Grant M. Kloster, Kevin P. O'brien, Michael D. Goodner, Jihperng Leu, David H. Gracias, Lee D. Rockford, Peter K. Moon, Chris E. Barns
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Patent number: 7020766Abstract: A conjugate processor includes an instruction set architecture (ISA) visible portion having a main pipeline, and an h-flow portion having an h-flow pipeline. The binary executed on the conjugate processor includes an essential portion that is executed on the main pipeline and a non-essential portion that is executed on the h-flow pipeline. The non-essential portion includes hint calculus that is used to provide hints to the main pipeline. The conjugate processor also includes a conjugate mapping table that maps triggers to h-flow targets. Triggers can be instruction attributes, data attributes, state attributes or event attributes. When a trigger is satisfied, the h-flow code specified by the target is executed in the h-flow pipeline.Type: GrantFiled: May 30, 2000Date of Patent: March 28, 2006Assignee: Intel CorporationInventors: Hong Wang, Ralph Kling, Yong-Fong Lee, David A. Berson, Michael A. Kozuch, Konrad Lai
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Patent number: 7019828Abstract: Briefly, in accordance with one embodiment of the invention, the intensity of the signals from surface enhanced Raman spectroscopy may be increased by using lithium chloride as an enhancer to activate a metallic structure used for surface enhanced Raman spectroscopy. The increased signal intensity may allow surface enhanced Raman spectroscopy to be utilized to detect individual analytes such as nucleotides, for example in DNA sequencing without requiring a dye or radioactive label.Type: GrantFiled: March 12, 2003Date of Patent: March 28, 2006Assignee: Intel CorporationInventors: Xing Su, Lei Sun, Tae-Woong Koo, Selena Chan
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Patent number: 7020836Abstract: Received data is provided to a pipelined network in which a one's complement checksum is computed. The computed checksum is stored in a register. In further embodiments, at least one intermediate result in the pipelined network is stored in at least one corresponding register. Other embodiments include determining whether the digital data to be included in the checksum is odd or even based on a number of valid bytes, and selectively swapping bytes in the pipelined checksum network based on whether the digital data is determined to be odd or even. In some embodiments, the received digital data is masked to selectively choose received digital data to be included in the checksum.Type: GrantFiled: July 30, 2002Date of Patent: March 28, 2006Assignee: Intel CorporationInventor: Harlan T. Beverly
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Patent number: 7020206Abstract: A computer system includes a memory and a processor. The memory stores a program to cause the processor to provide error data that indicate motion in an image. The processor represent each error signal as a collection of ordered bits, and the processor codes the bits of each order to indicate zerotree roots that are associated with the order.Type: GrantFiled: November 27, 2000Date of Patent: March 28, 2006Assignees: Intel Corporation, Indian Institute of TechnologyInventors: Tinku Acharya, Prabir K. Biswas, Niloy J. Mitra
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Patent number: 7020762Abstract: A system and method for a processor to determine a memory page management implementation used by a memory controller without necessarily having direct access to the circuits or registers of the memory controller is disclosed. In one embodiment, a matrix of counters correspond to potential page management implementations and numbers of pages per block. The counters may be incremented or decremented depending upon whether the corresponding page management implementations and numbers of pages predict a page boundary whenever a long access latency is observed. The counter with the largest value after a period of time may correspond to the actual page management implementation and number of pages per block.Type: GrantFiled: December 24, 2002Date of Patent: March 28, 2006Assignee: Intel CorporationInventors: Eric A. Sprangle, Anwar Q. Rohillah
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Patent number: 7020675Abstract: A multiplier includes an input stage to receive input signals to provide currents at a plurality of source nodes. An output stage includes a plurality of transistors groups, each of the transistor groups has a plurality of binary weighted transistor pairs. A select unit selects the binary weighted transistor pairs based on binary code signals so that each transistor pair passes a current from one of the source nodes to either a reference node or a summing node.Type: GrantFiled: March 26, 2002Date of Patent: March 28, 2006Assignee: Intel CorporationInventors: David J. Comer, Aaron K. Martin, James E. Jaussi
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Patent number: 7020871Abstract: A method of debugging code that executes in a multithreaded processor having a microengines includes receiving a program instruction and an identification representing a selected one of the microengines from a remote user interface connected to the processor pausing program execution in the threads executing in the selected microengine, inserting a breakpoint after a program instruction in the selected microengine that matches the program instruction received from the remote user interface, resuming program execution in the selected microengine, executing a breakpoint routine if program execution in the selected microengine encounters the breakpoint and resuming program execution in the microengine.Type: GrantFiled: December 21, 2000Date of Patent: March 28, 2006Assignee: Intel CorporationInventors: Debra Bernstein, Serge Kornfeld, Desmond R. Johnson, Donald F. Hooper, James D. Guilford, Richard D. Muratori
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Patent number: 7019592Abstract: An amplifier includes multiple gain ranges. The gain range can be set by electrically adding or removing load devices.Type: GrantFiled: November 12, 2004Date of Patent: March 28, 2006Assignee: Intel CorporationInventor: James E. Jaussi
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Patent number: 7020590Abstract: A mechanism is disclosed for determining a voltage at a device in a power delivery network. The mechanism includes determining an impulse response for the power delivery network, and tracking the current consumed by the device as it operates over a sequence of clock cycles. The activity profile is filtered using a representation of the impulse response to provide a profile of the voltages at the device.Type: GrantFiled: December 28, 2001Date of Patent: March 28, 2006Assignee: Intel CorporationInventors: Edward T. Grochowski, David J. Ayers, Vivek Tiwari
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Patent number: 7017638Abstract: An embodiment of the present invention includes a pusher and a horizontal puncher. The pusher is located underneath a strip of flexible tape attached to a first unit and a sub-assembly, respectively. The pusher pushes the first unit upward vertically. The horizontal puncher punches the first unit horizontally so that the first unit is folded on top of the sub-assembly.Type: GrantFiled: July 8, 2002Date of Patent: March 28, 2006Assignee: Intel CorporationInventor: Ernesto S. dela Cruz
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Patent number: 7019394Abstract: A circuit package includes a base portion and a first metal pattern disposed on a substrate surface. Second and third metal patterns are disposed on another substrate surface, and electrically coupled to first and second vias. The third metal pattern forms a gap to electrically isolate it from the second metal pattern. A circuit package includes a substrate having an opening and a single heat sink positioned in the opening to expose top and bottom surfaces through top and bottom surfaces of the substrate. Selective plating includes applying first and second metal patterns to a substrate surface, creating a potential voltage difference between the first metal pattern and a metal source, and plating the first metal pattern by attracting a first metal type to the voltage potential of the first metal pattern. The voltage potential of the first metal pattern is less than the voltage potential of the metal source.Type: GrantFiled: September 30, 2003Date of Patent: March 28, 2006Assignee: Intel CorporationInventors: Xiaowei Yao, Tam Nguyen, Marc Finot, Rickie C. Lake, Jeffrey A. Bennett, Robert Kohler
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Patent number: 7018938Abstract: Radiant energy may be applied to a photochemically susceptible etching or conditioning solution to enable precise control of the removal of material or alteration of the top surface of a wafer during the fabrication of semiconductor integrated circuits. A particular condition may be detected during the course of photoactivated generation of free radicals or molecular activation to control the further generation of said species by controlling the radiant energy exposure of a wafer.Type: GrantFiled: November 14, 2002Date of Patent: March 28, 2006Assignee: Intel CorporationInventors: Subramanyam A. Iyer, Justin K. Brask, Vijayakumar S. Ramachandrarao
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Patent number: 7019977Abstract: Securing a heat sink to an electronic device, such as an integrated circuit package, includes applying an adhesive layer to only a periphery of a surface on a thermal interface material. The thermal interface material is applied to the heat sink and/or integrated circuit package using the adhesive layer. The heat sink is in thermal contact with the integrated circuit package to extract heat during operation.Type: GrantFiled: December 17, 2003Date of Patent: March 28, 2006Assignee: Intel CorporationInventors: Seri Lee, Seung M. You, Jae W. Chang
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Patent number: 7018867Abstract: Fluidic self-assembly may be utilized to form a stack of two integrated circuits. The integrated circuits may include surface mount electrical connections and surface features that control the alignment between the integrated circuits. In particular, the contacts may be provided on one side of each integrated circuit and surface features may cause the integrated circuits to align with one another in an immersion fluid. The aligned circuits may join to form physical and electrical connections. The resulting structure may be a stack of two integrated circuits electrically coupled to one another.Type: GrantFiled: February 6, 2003Date of Patent: March 28, 2006Assignee: Intel CorporationInventor: David Gracias
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Patent number: 7017258Abstract: A system for mounting heatsinks, in particular, high-mass heatsinks, on printed circuit boards, such as motherboards. The mounting system includes a backplate, disposed beneath the motherboard, with pins protruding up through the motherboard, and a linkage assembly, which is fixably attached to a base portion of a heatsink assembly. The linkage assembly includes scoops, for grasping the pins during engagement, and a ratcheting system, for compressing the heatsink and thermal interface material onto the package. The mounting system is designed to effectively distribute the heatsink weight, as well as the forces caused by chronic and dynamic stresses, through, rather than upon the motherboard, such as to a chassis. The mounting system thus alleviates stress cracks, component pullout, solderball stress, and other damaging conditions to the motherboard. The mounting system may be engaged and disengaged without the use of tools.Type: GrantFiled: January 26, 2004Date of Patent: March 28, 2006Assignee: Intel CorporationInventors: Michael Z. Eckblad, Mark W. Anderson
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Patent number: 7020729Abstract: Transmitting data across a scalable, flexible speed, serial bus in a communication protocol independent manner.Type: GrantFiled: May 16, 2002Date of Patent: March 28, 2006Assignee: Intel CorporationInventors: Richard Taborek, Sr., Donald W. Alderrou, Steve Dreyer, Gary Rara
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Publication number: 20060063495Abstract: A system design may include electromagnetic sensors and/or placement of components to address problems of near-field electromagnetic interference caused by a processor within the system, and may further include measures to mitigate interference when detected.Type: ApplicationFiled: September 21, 2004Publication date: March 23, 2006Applicant: Intel CorporationInventor: Tony Hamilton
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Patent number: 7017040Abstract: A system includes a processor, a memory including a basic input/output system (BIOS) in flash memory that includes digital signature verification, and a BIOS update installation process, and a medium containing a BIOS update file. The BIOS update file includes a signed data portion having a volume header, signed data and executable update code to configure the signed data with data in an unsigned data portion, and a digital signature.Type: GrantFiled: December 4, 2003Date of Patent: March 21, 2006Assignee: Intel CorporationInventors: Matthew D. Singer, Robert J. Johnson, Nicholas J. Adams