Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a first die having a first surface and an opposing second surface embedded in a first dielectric layer, where the first surface of the first die is coupled to the second surface of the package substrate by first interconnects; a second die having a first surface and an opposing second surface embedded in a second dielectric layer, where the first surface of the second die is coupled to the second surface of the first die by second interconnects; and a third die having a first surface and an opposing second surface embedded in a third dielectric layer, where the first surface of the third die is coupled to the second surface of the second die by third interconnects.

Abstract: This disclosure describes systems, methods, and devices related to performance measurements. A device may decode a management service (MnS) service request received from an MnS consumer for the 5G system (5GS), wherein the service request is associated with a performance measurement collection service to be delivered by the service producer to the consumer related to a location management function (LMF). The device may detect performance measurements data received from the LMF. The device may decode from the performance measurements data a measurement label associated with the performance measurements data based on the MnS service. The device may encode a service response based on the performance measurements data received from the PCF.

Abstract: Technologies for memory on package with reduced package thickness are disclosed. In the illustrative embodiment, a die assembly includes a substrate with a processor die mounted on the top surface and a memory die mounted on the bottom surface. The die assembly is mounted on another substrate, such as a mainboard. A cavity is defined in the mainboard, and the memory die mounted on the bottom surface of the die assembly is positioned in the cavity. Positioning the memory die on the bottom surface of the die assembly can reduce the overall thickness of the die assembly and, therefore, can reduce the overall thickness of a device that incorporates the die assembly.

Abstract: This disclosure describes systems, methods, and devices related to shifting layouts of electronic circuit vias during optical proximity corrections (OPC). A method may include identifying a first metal line, of an electronic circuit, drawn at a first position; identifying a second metal line, of the electronic circuit, drawn at a second position; identifying a via drawn at a third position extending between the first metal line and the second metal line; determining a fourth position to which the first metal line is to move from the first position; determining a fifth position to which the second metal line is to move from the second position; determining, based on the fourth position, the fifth position, a sixth position to which the via is to move from third position; and generating a layout for generating a photomask for the via at the sixth position.

Abstract: Disclosed herein are microelectronic assemblies with direct bonding using nanotwinned copper (NTC). An example microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding (DB) region, wherein the DB region includes a DB contact comprising a first portion and a second portion having different microstructures. The first portion is between the first microelectronic component and the second portion. The second portion is between the first portion and the second microelectronic component. In some implementations, the first portion has non-columnar microstructure, and the second portion has columnar microstructure. In some implementations, less than about 40% of grains of the first portion have ac <111> orientation, and at least about 50% of grains of the second portion have the <111> orientation.

Abstract: An integrated circuit (IC) package comprising a die having a front side and a back side. A solder thermal interface material (STIM) comprising a first metal is over the backside. The TIM has a thermal conductivity of not less than 40 W/mK; and a die backside material (DBM) comprising a second metal over the STIM, wherein the DBM has a CTE of not less than 18×10?6 m/mK, wherein an interface between the STIM and the DBM comprises at least one intermetallic compound (IMC) of the first metal and the second metal.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a photonic integrated circuit (PIC) having a first surface having a channel and a first magnetic material; a fiber connector including a second surface with a second magnetic material; and a fiber physically coupled to the second surface of the fiber connector by an adhesive material; wherein the first surface of the PIC is coupled to the second surface of the fiber connector by the first and second magnetic materials with the fiber positioned in the channel.

Abstract: A low-leakage oxide dielectric material with high elastic modulus is deposited directly upon an oxidizable feature with a polycyclic PE-ALD process that limits the formation of an oxide on the feature. A precursor of one or more constituents, such as silicon, may be deposited upon a workpiece during a deposition phase, and the absorbed precursor(s) may be oxidized during a first oxidation phase under more conservative conditions until a first film thickness is achieved. Subsequently, absorbed precursor(s) may be oxidized during a second oxidation phase under more aggressive conditions to arrive at a total film thickness. Transistor contact metal, which may provide local interconnection between source or drain terminals of multiple transistors, may maintain high electrical conductivity after being electrically insulated with such a low-leakage film.

Abstract: An array of quantum dot qubits (e.g., an array of spin qubits) relies on a gradient magnetic field to ensure that the qubits are separated in frequency in order to be individually addressable. Furthermore, a strong magnetic field gradient is required to electrically drive the electric dipole spin resonance (EDSR) of the qubits. Quantum dot devices disclosed herein use microcoil arrangements for providing a gradient magnetic field, the microcoil arrangements integrated on the same chip (e.g., on the same die or wafer) as quantum dot qubits themselves. Unlike previous approaches to quantum dot formation and manipulation, various embodiments of the quantum dot devices disclosed herein may enable improved control over magnetic fields and their gradients to realize better frequency targeting of individual qubits, help minimize adverse effects of charge noise on qubit decoherence and provide good scalability in the number of quantum dots included in the device.

Abstract: Technologies for optical coupling to photonic integrated circuit (PIC) dies are disclosed. In one illustrative embodiment, a PIC die has one or more waveguides. A lens array is positioned adjacent the PIC die. Light from waveguides of the PIC die reflects off of a reflective surface of the lens array. The reflective surface directs the light from the PIC die towards lenses in the lens array. The lenses collimate the light, facilitating coupling of light to and from other components. The reflective surface on the lens array may be oriented at any suitable angle, resulting in a collimated beam of light that is oriented at any suitable angle.

Abstract: Substrates with a glass core and glass buildup layers, and methods of forming the same, are described herein. In one example, a substrate includes a glass core, glass layers above and below the glass core, conductive traces in the glass core and at least some of the glass layers, and conductive contacts on a surface of the substrate.

Abstract: Devices, transistor structures, systems, and techniques are described herein related to backside contacts for field effect transistors formed using a backside contact etch prior to cavity spacer formation. A transistor includes semiconductor structures such as nanoribbons extending between a source and a drain. A spacer material is between a gate and the source/drain as cavity spacer fill. The spacer material is also between a portion of a backside contact and a portion of the source/drain, to eliminate a short between the backside contact and the gate.

Abstract: An integrated circuit device comprising a plurality of first field effect transistors (FETs) formed on a substrate, wherein a first FET comprises a first channel material comprising a portion of the substrate; and a plurality of second FETs formed on the substrate, wherein a second FET comprises a second channel material that is different from the first channel material, wherein the second channel material comprises a thin film transistor (TFT) channel material.

Abstract: One or more transistors may have gate structures with differing sidewall slopes. The gate structures may be over stacks of channel regions in nanosheets (or nanoribbons or nanowires), and the differing gate profiles may correspond to differing electrical characteristics. Transistors with metal gate structures may be tuned by strategically etching the gate structures, for example, using lower etch powers, higher etch temperatures, and/or longer etch durations, to achieve substantially vertical gate profiles.

Abstract: In a technique of hardware thread isolation, a processor comprises a first core including a first hardware thread register. The core is to select a first key identifier stored in the first hardware thread register in response to receiving a first memory access request associated with a first hardware thread of a process. Memory controller circuitry coupled to the first core is to obtain a first encryption key associated with the first key identifier. The first key identifier may be selected from the first hardware thread register based, at least in part, on a first portion of a pointer of the first memory access request. The first key identifier selected from the first hardware thread register is to be appended to a physical address translated from a linear address at least partially included in the pointer.

Abstract: Embodiments described herein provide a technique to decompose 64-bit per-lane virtual addresses to access a plurality of data elements on behalf of a multi-lane parallel processing execution resource of a graphics or compute accelerator. The 64-bit per-lane addresses are decomposed into a base address and a plurality of per-lane offsets for transmission to memory access circuitry. The memory access circuitry then combines the base address and the per-lane offsets to reconstruct the per-lane addresses.

Abstract: Technologies for device management in metaverse interactions are disclosed. In an illustrative embodiment, a compute device is connected to remote compute devices in a metaverse. The compute device may detect local devices, such as by seeing a device in images captured by a camera of the compute device. The local device may be, e.g., a cell phone or smartwatch. The local devices may be registered by the compute device and reproduced in the metaverse. The local user of the compute device may interface with the local devices in the metaverse. The local user may allow remote users to interface or control the local device as well.

Abstract: An apparatus includes circuitry to receive a memory access request based on a memory address in a memory allocation of a program. The memory allocation is assigned to a slot of memory apportioned into a plurality of slots. The circuitry is to calculate an index based, at least in part, on whether a size of the slot exceeds a slot threshold size, and determine whether a buffer communicatively coupled to the circuitry includes a buffer entry corresponding to the index and containing a set of metadata associated with the memory allocation. Based on the slot size, the circuitry is to calculate the index by either determining a metadata virtual address or by determining a virtual address of a midpoint of the slot. The indexed data may include bounds and tag information for the circuitry to determine if a memory access is within the bounds and matches the tag value.

Abstract: Multi-die packages including both photonic and electric integrated circuit (IC) die interconnected to each other through a routing structure built-up on a glass substrate. A glass preform comprising an optical waveguide may also be attached to the routing structure. A plurality of electrical IC (EIC) die may be arrayed over the routing structure along with a plurality of photonic IC (PIC). Each PIC may be coupled to an optical waveguide within the glass preform. Conductive vias may extend through the glass substrate and be further coupled with a host substrate. The host substrate may comprise glass and an optical waveguide embedded within the glass. A vertical coupler may be attached to the host substrate to optically couple the host substrate to the optical waveguide within the glass preform of the multi-die package. Many of the multi-die packages may be arrayed over a routing structure on the host substrate.

Abstract: Thermal dissipation and grounding of integrated circuit (IC) devices with backside power delivery networks are discussed. An IC device layer between frontside and backside interconnect sections, composed mostly of an insulating material, is coupled to a crystalline heat spreader or a metal thermal ground layer by an array of thermal pillars extending through the insulating material. The crystalline heat spreader layer may include one or more thermal sensors, such as thermal sensing diodes, also coupled to the IC device layer by one or more thermal pillars. The IC device layer and crystalline layers are coupled by a hybrid bond, which forms the thermal pillars through a continuous section of the insulating material.

Abstract: An electronic substrate may be fabricated by forming a base substrate and forming an inductor extending through the base substrate, wherein the inductor includes a magnetic material layer and a barrier layer, such that the barrier layer prevents the magnetic material layer from leaching into plating solutions during the fabrication of the electronic substrate. In one embodiment, the barrier material may comprise titanium. In another embodiment, the barrier layer may comprise a polymeric material. In still another embodiment, the barrier layer may comprise a nitride material layer. The inductor may further include a plating seed layer on the barrier layer and a conductive fill material abutting the plating seed layer.

Abstract: In one embodiment, an interconnect bridge circuitry includes a first set of bridge-to-die electrical connectors in a first region of the circuitry, a second set of bridge-to-die electrical connectors in a second region of the circuitry, and an interconnection between a bridge-to-die connector of the first set and a bridge-to-die connector of the second set. The interconnection is in a third region of the circuitry between the first region and the second region, and includes a first trace connected to the bridge-to-die electrical connector of the first set, a second trace connected to the bridge-to-die electrical connector of the second set, the second trace parallel with the first trace, and a third trace connected between the first trace and the second trace.

Abstract: Techniques for snapshotting of performance monitoring are described. In an embodiment, an apparatus includes a plurality of performance monitoring hardware resources, hardware to capture a record of state data related to state of the apparatus in connection with an occurrence of an event, and storage to store a first indicator corresponding to at least a first performance monitoring hardware resource of the plurality of performance monitoring hardware resources and to enable the hardware to include, in the record, performance data from the first performance monitoring hardware resource.

Abstract: Transistor structures comprising a gate electrode, or “gate,” that is self-aligned to underlying channel material. A mask material employed for patterning the channel material is further employed to define a cap of mask material having a larger width that protects a portion of gate material during a gate etch. The cap is therefore self-aligned to the channel material so that an amount by which a gate material extends laterally beyond the channel material is ensured to be symmetrical about a centerline of the channel material.

Abstract: Techniques for region-aware memory bandwidth allocation control are described. In an embodiment, an apparatus includes a processing core and control circuitry. The processing core is to execute a plurality of threads. The control circuitry is to control use of memory bandwidth per memory region and per thread.

Abstract: Microelectronic integrated circuit package structures include a die having a dielectric die edge sidewall and a bulk silicon die edge sidewall, where the bulk silicon die edge sidewall is in substantial alignment with the dielectric die edge sidewall. The bulk silicon die edge sidewall has a plurality of scallop structures along a vertical distance of the bulk silicon die edge sidewall.

Abstract: Embodiments described herein are generally directed to detecting security issues in a hardware design using IFT. In an example, dataflows are tracked within a hardware design represented in an HDL without instrumenting the HDL. Dataflow primitives are received specifying taint sources from which the dataflows are to be tracked. A baseline simulation trace log is obtained for a baseline RTL simulation of the hardware design by causing a simulator to perform the baseline RTL simulation during which none of the taint sources are altered. Injection simulation trace logs are obtained for injection RTL simulations by causing the simulator to perform an injection RTL simulation, for each taint source, during which the taint source is altered. The dataflows are then identified based on comparisons between the baseline and the injection simulation trace logs. A potential security issue is detected within the hardware design by applying a policy to the dataflows.

Abstract: Described herein is a network and renderer aware split rendering technique that enables a cloud gaming service to split execution of cloud gaming workloads between a graphics processor of a cloud gaming server and a graphics processor of a client of the cloud gaming service. The split rendering technique enables portions of a frame that most vulnerable to quality degradation at low bitrates to be rendered on the client, which results in an improvement of the quality of the final frame that is presented at the client device.

Abstract: This disclosure describes systems, methods, and devices related to non-trigger based (non-TB) sensing. A device may initiate sensing measurements by sending a sensing null data packet announcement (NDPA) frame to an access point (AP) responder. The device may send one or more first null data packet (NDP) packets to the AP responder. The device may identify one or more second NDP packets received from the AP responder.

Abstract: In one embodiment, an integrated circuit package includes an integrated heat spreader (IHS) that incorporates a Peltier element. The IHS may include one or more Peltier elements, which may be in a top portion of the IHS. The Peltier element(s) may be electrically connected to the package substrate through a trace on a sidewall of the IHS.

Abstract: Technologies for a unified debug and test architecture in chiplets is disclosed. In an illustrative embodiment, several chiplets are integrated on an integrated circuit package. The chiplets are connected by a package interconnect, such as a universal chiplet interconnect express (UCIe) interconnect. Each chiplet includes several debug nodes, which are connected by an on-chiplet network. One of the chiplets, referred to as a package debug endpoint, acts as a link endpoint for an off-package link, such as a peripheral component interconnect express (PCIe) link. In use, debug messages can be sent to the package debug endpoint over a PCIe link. The debug messages can be routed within the chiplets and between chiplets, allowing for the debug functionality at each debug node to be probed using a common protocol. In this manner, chiplets from different vendors can be integrated into the same package and tested using common software.

Abstract: This disclosure describes systems, methods, and devices for placing bits in an isochronous data stream from a first data port to a second data port. A device may inject, using a first port, based on a periodicity less than a defined frame rate of a data stream comprising multiple frames, a status or control bit in place of one or more low-order bits, reserved bits, or unused bits of a frame of the data stream, wherein the frame includes one or more data words; receive, using a second port synchronized to the periodicity, the data stream from the first port; extract, using the second port, based on the periodicity, the status or control bit; and extract, using the second port, a remainder of the frame.

Abstract: An integrated circuit device comprising a varactor comprising a first conductive contact; a second conductive contact; and a thin film transistor (TFT) channel material coupled between the first conductive contact and the second conductive contact.

Abstract: A data scaling module for USB4 that embodies display driver (DD) and connection manager (CM) operations. Periodic and aperiodic transfer requests are monitored. The periodic BW activity on periodic peripherals, such as display panels (DPs) is monitored, and determinations as to reduced periodic activity on a DP are made. Responsive to receiving a high aperiodic bandwidth request, the original refresh rate for the DP is reduced. The newly freed USB4 BW is provided for the aperiodic task. At completion of the aperiodic task, the DD increases the refresh rate to its original value.

Abstract: This disclosure relates matrix operation acceleration for different matrix sparsity patterns. A matrix operation accelerator may be designed to perform matrix operations more efficiently for a first matrix sparsity pattern rather than for a second matrix sparsity pattern. A matrix with the second sparsity pattern may be converted to a matrix with the first sparsity pattern and provided to the matrix operation accelerator. By rearranging the rows and/or columns of the matrix, the sparsity pattern of the matrix may be converted to a sparsity pattern that is suitable for computation with the matrix operation accelerator.

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes an electronic package substrate including a glass core layer and a regulator circuit. A first portion of the circuit components of the regulator circuit is embedded in the glass core layer and a second portion of the circuit components of the regulator circuit is formed on a surface of the glass core layer.

Abstract: This disclosure describes systems, methods, and devices related to performance measurements. A device may decode a service request received from a management service consumer for the 5G system (5GS), wherein the service request may be associated with a performance measurement collection service to be delivered by the service producer to the service consumer related to a network exposure function (NEF). The device may detect performance measurements data received from the NEF. The device may decode from the performance measurements data a measurement label associated with the performance measurements data based on the service request. The device may encode a service response based on the performance measurements data received from the NEF.

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes plurality of metal-insulator-metal capacitor units and a control circuit to dynamically select different amounts of the plurality of metal-insulator-metal capacitor units in correlation to a type of operation in a semiconductor die.

Abstract: A system that includes at least one memory and circuitry coupled to the at least one memory, wherein the circuitry is to access media from the at least one memory, wherein the circuitry is to: select one or more settings to apply to encode the video based on a cost of signaling applicable settings.

Abstract: An apparatus comprising a source or drain of a field effect transistor (FET), a first dielectric between a portion of the source or drain and a FET gate, the first dielectric comprising silicon nitride, and a second dielectric above at least a portion of the first dielectric, the second dielectric comprising silicon oxide doped with at least one of oxygen or carbon, the second dielectric having a dielectric constant lower than the first dielectric.

Abstract: Disclosed herein are optical transceivers with multi-laser modules, as well as related optoelectronic assemblies and methods. In some embodiments, an optical transceiver may include: a first laser and a second laser, an optical output path, wherein an output of the first laser is coupled to the optical output path; and switching circuitry to decouple the output of the first laser from the optical output path and to couple an output of the second laser to the optical output path.

Abstract: Embodiments for a matrix transpose and multiply operation are disclosed. In an embodiment, a processor includes a decoder and execution circuitry. The decoder is to decode an instruction having a format including an opcode field to specify an opcode, a first destination operand field to specify a destination matrix location, a first source operand field to specify a first source matrix location, and a second source operand field to specify a second source matrix location. The execution circuitry is to, in response to the decoded instruction, transpose the first source matrix to generate a transposed first source matrix, perform a matrix multiplication using the transposed first source matrix and the second source matrix to generate a result, and store the result in a destination matrix location.

Abstract: An optical interconnect component for use in transmitting light between a photonic integrated circuit and one or more optical fibres attached to an optical fibre connector ferrule is disclosed. The optical interconnect component comprises a step formed at an edge of the optical interconnect component, the step including a ledge and a facet, one or more optical beam management elements formed in a surface of the optical interconnect component, and a plurality of integrated optical waveguides. Each of two or more of the integrated optical waveguides extends from the facet so as to define a plurality of optical ports at the facet, and each of the one or more optical beam management elements is aligned with, but separated from, an end of a corresponding one of the plurality of integrated optical waveguides.

Abstract: An integrated circuit device comprising a resistor formed on a non-crystalline substrate, the resistor comprising a gate electrode; a gate dielectric in contact with the gate electrode; a source electrode and a drain electrode; and a thin film transistor TFT channel material coupled between the source electrode and the drain electrode.

Abstract: Systems, apparatuses and methods include technology that identifies a model update that originates from a plurality of IoT devices. The technology determines votes from the plurality of IoT devices, where the votes indicate whether the model update will be deployed. The technology deploys the model update to the plurality of IoT devices based on the votes.

Abstract: Bus interface protocols allow users to transmit data from one IP to another. Allowing definition of multiple per-symbol and per-packet user signals allows users to append information with each segment of data or transmit additional information pertaining to the whole packet of data, respectively. This provides finer granularity and control over the information.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to generate a graphics processing unit (GPU) long instruction trace (GLIT). An example apparatus includes at least one memory, and at least one processor to execute instructions to at least identify a first routine based on an identifier of a second routine executed by the GPU, the first routine based on an emulation of the second routine, execute the first routine to determine a first value of a GPU state of the GPU, the first routine having (i) a first argument associated with the second routine and (ii) a second argument corresponding to a second value of the GPU state prior to executing the first routine, and control a workload of the GPU based on the first value of the GPU state.

Abstract: Techniques related to video coding include efficient frame loss recovery using a feedback channel acknowledgement to decode base layer frames.

Abstract: Systems, methods, and computer-readable storage media for measuring one-way delay in multi-access networks (MAMS) are provided. Other embodiments may be described and/or claimed.

Abstract: Embodiments detailed herein relate to matrix (tile) operations. For example, decode circuitry to decode an instruction having fields for an opcode and a memory address; and execution circuitry to execute the decoded instruction to set a tile configuration for the processor to utilize tiles in matrix operations based on a description retrieved from the memory address, wherein a tile a set of 2-dimensional registers are discussed.