Abstract: Various embodiments comprise prioritizing frequency allocations in thermally- or power-constrained computing devices. Computer elements may be assigned ‘weights’ based on their priorities. The computer elements with higher weights may receive higher frequency allocations to assure they receive priority in processing more quickly. The computer elements with lower weights may receive lower frequency allocations and suffer a slowdown in their processing. Elements with the same weight may be grouped together for the purpose of frequency allocation.

Abstract: Techniques related to video encoding are discussed that, for each block of input video, select an individual partitioning and coding mode selection technique from multiple such selection techniques. For a picture, the selection algorithm takes as input scores for individual blocks, costs of the various partitioning and coding mode selection techniques, and various detector outputs. The selection algorithm provides as output a partitioning and coding mode selection technique for each block in picture. The algorithms selection is such that the overall cost of the selected algorithms in the picture is as close as possible to a given picture budget. Furthermore, a partitioning and coding mode selection algorithms, binary depth partitioning (BDP), is discussed. For a block, BDP provides fast convergence to a partitioning and associated coding modes first evaluating intermediate partitioning options and converging on the final partitioning by evaluating either larger of smaller partitions.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate above the quantum well stack, wherein the first gate includes a first gate metal and a first gate dielectric layer; and a second gate above the quantum well stack, wherein the second gate includes a second gate metal and a second gate dielectric layer, and the second gate dielectric layer extends over the first gate.

Abstract: Technologies disclosed herein provide a method for receiving at a device from a remote server, a request for state information from a first processor of the device, obtaining the state information from one or more registers of the first processor based on a request structure indicated by a first instruction of a software program executing on the device, and generating a response structure based, at least in part, on the obtained state information. The method further includes using a cryptographic algorithm and a shared key established between the device and the remote server to generate a signature based, at least in part, on the response structure, and communicating the response structure and the signature to the remote server. In more specific embodiments, both the response structure and the request structure each include a same nonce value.

Abstract: Particular embodiments described herein provide for a system for enabling the communication of a message using a network interface controller (NICs) on a subnet. In an example, the system is applicable to hardware offload NICs such as those implementing the Portals protocol. The system can be configured to determine a NIC in a first subnet to be used to communicate a message, where the NIC is configured to comply with a message passing interface protocol, create a manifest that includes an identifier of the NICs and a subnet ID that identifies the first subnet, and communicate the manifest to the receiver.

Abstract: An apparatus is provided which comprises: a first inverter to receive a clock; a pass-gate coupled to the first inverter; a second inverter coupled to the pass-gate and to provide an output clock; and a device coupled to the second inverter and the pass-gate, wherein the transistor and the pass-gate are controllable by a logic that depends on logic values of at least two signals (e.g., an enable and the clock).

Abstract: An embodiment of a semiconductor apparatus may include technology to identify a group of objects based on a common object structure, and allocate the group of objects to two or more memory channels based on interleave set information. Other embodiments are disclosed and claimed.

Abstract: An embodiment of a graphics apparatus may include a vision characterizer to determine a vision characteristic associated with a user, and a parameter adjuster communicatively coupled to the vision characterizer to adjust a render parameter of a graphics system based on the determined vision characteristic. Other embodiments are disclosed and claimed.

Abstract: A mechanism is described for facilitating automatic tuning of image signal processors using reference images in image processing environments, according to one embodiment. A method of embodiments, as described herein, includes one or more processors to: receive images associated with one or more scenes captured by one or more cameras; access tuning parameters associated with functionalities within an image signal processor (ISP) pipeline; generate reference images based on the tuning parameters, wherein a reference image is associated with an image for each functionality within the ISP pipeline; and automatically tune the ISP pipeline based on selection of one or more of the reference images for one or more of the images for one or more of the functionalities.

Abstract: An embodiment of a semiconductor package apparatus may include technology to acquire vibration information corresponding to a speaker, and identify the speaker based on the vibration information. Other embodiments are disclosed and claimed.

Abstract: The present disclosure is directed to systems and methods for mitigating or eliminating the effectiveness of a side channel attack, such as a Meltdown or Spectre type attack by selectively introducing a variable, but controlled, quantity of uncertainty into the externally accessible system parameters visible and useful to the attacker. The systems and methods described herein provide perturbation circuitry that includes perturbation selector circuitry and perturbation block circuitry. The perturbation selector circuitry detects a potential attack by monitoring the performance/timing data generated by the processor. Upon detecting an attack, the perturbation selector circuitry determines a variable quantity of uncertainty to introduce to the externally accessible system data. The perturbation block circuitry adds the determined uncertainty into the externally accessible system data. The added uncertainty may be based on the frequency or interval of the event occurrences indicative of an attack.

Abstract: Methods and apparatus for a reconfigurable Galois Field (GF) Sbox unit for Camellia, AES, and SM4 hardware accelerator are described. In one embodiment, a modified Substitute box (Sbox) leverages a common field of GF to incorporate a multi-cipher mode of operation. The hybrid Sbox design can reduce area and/or energy consumption. Other embodiments are also described and claimed.

Abstract: Technology for a memory device is described. The memory device can include an array of memory cells and a memory controller. The memory controller can receive a request to program a memory cell within the array of memory cells. The memory controller can select a current magnitude and a duration of the current magnitude for a programming set pulse based on a polarity of access for the memory cell, a number of prior write cycles for the memory cell, and electrical distances between the memory cell and wordline/bitline decoders within the array of memory cells. The memory controller can initiate, in response to the request, the programming set pulse to program the memory cell within the array of memory cells. The selected current magnitude and the selected duration of the current magnitude can be applied during the programming set pulse.

Abstract: In one aspect, an apparatus for detecting fatigue comprises a dry-contact electroencephalogram (EEG) electrode to measure EEG data operably coupled to at least one processor. The at least one processor is to: calculate a frequency domain representation of the EEG data, detect spectral features indicative of fatigue based on the frequency domain representation; and determine whether the brain is fatigued based on the detection. In another aspect, a method for detecting fatigue comprises receiving EEG data from dry-contact EEG electrode, calculating a frequency domain representation of the EEG data, detecting spectral features indicative of fatigue based on the frequency domain representation; and determining whether the brain is fatigued based on the detection.

Abstract: An embodiment of a semiconductor package apparatus may include technology to map a collection of data into two or more mathematical graph representations of the data based on a configurable set of rules that one of preserves or enhances relationships or properties of the data, and organize the two or more graph representations into two or more clusters of data based on graph information entropy and one or more parameters. Other embodiments are disclosed and claimed.

Abstract: The present disclosure relates to providing a wordline bridge between wordlines of adjacent tiles of memory cells to reduce the number wordline staircases in 3D memory arrays. An apparatus may include a memory array having memory cells. The memory array includes a first block of pages of the memory cells in a first tile and a second block of pages of the memory cells in a second tile. The apparatus may also include a polysilicon wordline bridge that couples first wordlines of the first block to second wordlines of the second block to couple the first tile to the second tile. The wordline bridge may be formed by applying a hard mask over the first tile, the second tile, and over a portion of polysilicon that connects the first tile to the second tile.

Abstract: In some embodiments, power may be temporarily removed from a first portion of a computer system (such as a display), and that power redirected to a second portion (such as a processor or System on a Chip), so that extra performance may be obtained from the second portion without exceeding the power budget for the system. If the first portion is a display, the time period of removed power may be short enough that the absence of luminance during that time period will not be noticeable to the human vision system. In a similar embodiment, power may be delivered to the first portion using pulse width modulation, using the time between pulses to redirect power to the other portion.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; a gate above the fin; and a material on side faces of the fin; wherein the fin has a width between its side faces, and the fin is strained in the direction of the width.

Abstract: A mechanism is described for facilitating maximizing efficiency of time-of-flight optical depth sensors in computing environments according to one embodiment. An apparatus of embodiments, as described herein, includes detection and observation logic to facilitate a camera to detect and observe a scene and one or more objects in the scene. The apparatus may further include generation, transmission, and reception (GTR) logic to generate a beam of photons based on a transmitted code stored at a memory device, where the GTR logic to transmit the beam of photons to the one or more objects and capture a beam of photons bouncing back from the one or more objects. The apparatus may further include computation and correlation logic to correlate first values of the transmitted code with second values of a returned signal from the one or more objects as the beam of photons.

Abstract: Particular embodiments described herein provide for a device that can be configured to receive data from a first node in a bi-directional chain of nodes, perform a reduction operation that is part of a collective communication operation using the data from the first node and data on the node to create a first intermediate result, store the first intermediate result in memory, communicate the first intermediate result to a second node, receive second data from the second node, perform the reduction operation that is part of the collective communication operation using the second data from the second node and the data on the node to create a second intermediate result, communicate the second intermediate result to the first node, and perform the collective communication operation using the second data from the second node and the first intermediate collective communication operation result to create a collective communication operation result.

Abstract: Embodiments of the present disclosure relate to quantum circuit assemblies implementing superconducting qubits, e.g., transmons, in which SQUID loops and portions of FBLs configured to magnetically couple to the SQUID loops extend substantially vertically. In contrast to conventional implementations, for a vertical SQUID according to various embodiments of the present disclosure, a line that is perpendicular to the SQUID loop is parallel to the qubit substrate. A corresponding FBL is also provided in a vertical arrangement, in order to achieve efficient magnetic coupling to the vertical SQUID loop, by ensuring that at least a portion of the FBL designed to conduct current responsible for generating magnetic field for tuning qubit frequency is substantially perpendicular to the substrate.

Abstract: An example apparatus for predicting eye fatigue includes an image receiver to receive an image of an eye. The apparatus also includes a fatigue predictor to predict eye fatigue in the eye based on a calculated blood vessel density score of the eye in the image. The apparatus further includes an alert generator to generate an alert in response to predicting the eye fatigue.

Abstract: A phase change memory (PCM) cell can include a PCM layer. A first electrode and a second electrode disposed on opposite sides of the PCM layer. The first electrode, the second electrode, or both includes a metal ceramic composite material layer disposed between an upper barrier layer and a lower barrier layer and wherein the metal ceramic composite material layer provides a corresponding electrode with an electrical resistivity of from 10 mOhm-cm to 1000 mOhm-cm.

Abstract: Components, devices, systems, and methods for monitoring a flowmeter. A transmitter may be configured to transmit a signal through a flowmeter. A sensor may be configured to receive the signal when the signal is unimpeded by a float in the flowmeter. A position of the float within the flowmeter may be determined based on sensor data from the sensor.

Abstract: An apparatus to facilitate video streaming is disclosed. The apparatus includes one or more processors to retrieve a manifest file including a first identifier to indicate a plurality of available video streams for conventional up-sampling, and a second identifier to indicate a plurality of available video streams for Super Resolution (SR), determine whether SR capability is enabled and retrieve one of the plurality video streams for SR, upon a determination that SR capability is enabled and based on the current bandwidth.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate and an adjacent second gate above the quantum well stack; and a gate wall between the first gate and the second gate, wherein the gate wall includes a first dielectric material and a second dielectric material different from the first dielectric material.

Abstract: An embodiment of a semiconductor apparatus may include technology to determine a persistent region and a non-persistent region of a volatile media based on an amount of power available from one or more backup power sources, and periodically backup only the non-persistent region of the volatile media to a non-volatile media. Other embodiments are disclosed and claimed.

Abstract: Embodiments of the present disclosure describe a method of fabricating spin qubit device assemblies that utilize dopant-based spin qubits, i.e. spin qubit devices which operate by including a donor or an acceptor dopant atom in a semiconductor host layer. The method includes, first, providing a pair of gate electrodes over a semiconductor host layer, and then providing a window structure between the first and second gate electrodes, the window structure being a continuous solid material extending between the first and second electrodes and covering the semiconductor host layer except for an opening through which a dopant atom is to be implanted in the semiconductor host layer. By using a defined gate-first process, the method may address the scalability challenges and create a deterministic path for fabricating dopant-based spin qubits in desired locations, promoting wafer-scale integration of dopant-based spin qubit devices for use in quantum computing devices.

Abstract: Techniques are provided for defending against an ultrasonic attack on a speech enabled device. A methodology implementing the techniques according to an embodiment includes detecting voice activity in an audio signal received by the device and generating an ultrasonic jamming signal in response to the detection. The jamming signal is broadcast over a loudspeaker for up to the duration of the detected voice activity to defend against the ultrasonic attack. According to another embodiment, the ultrasonic jamming signal is generated in response to detection of a wake-on-voice key phrase in the received audio signal, and the jamming signal is broadcast over the loudspeaker for a time duration selected to be less than or equal to a time window during which spoken commands are accepted by the device following the wake-on-voice key phrase detection. The jamming signal may include white or colored noise, combinations of tones, and/or a periodic sweep frequency.

Abstract: Techniques and mechanisms for mitigating the effect of signal noise on communication via an interconnect. In an embodiment, a substrate includes an interconnect and a conductor which has a hole formed therein. Portions of the interconnect variously extend over a side of the conductor, wherein another recess portion of the interconnect extends from a plane which includes the side, and further extends at least partially into the hole. The configuration of the recess portion extending within the hole may contribute to an impedance which dampens a transmitter slew rate of the communication. In an embodiment, a total distance along a path formed by the interconnect is equal to or less than 5.5 inches.

Abstract: Particular embodiments described herein provide for an electronic device that can be configured to help with the identification of a no-operation (NOP) sled attack identify. The system can be configured to receive an instruction, increment a value in a total instruction counter, increment a value in a branch instruction counter when the instruction is a branch instruction, increment a value in a memory instruction counter when the instruction is a memory instruction, create a ratio based on the value in the total instruction counter and the value in the branch instruction counter or the value in the memory instruction counter, and trigger an alert when the ratio satisfies a threshold. The ratio can indicate the presence of a NOP sled attack and the alert can be an interrupt that stops execution of the NOP sled.

Abstract: Various embodiments are generally directed to techniques for dynamic resource allocation among cryptographic domains, such as with memory pages in a platform that implements a plurality of cryptographically isolated domains, for instance. Some embodiments are particularly directed to a platform that includes a resource allocation manager (RMGR) that allows for page reassignment among cryptographically isolated virtual machines (VMs) while ensuring functional correctness with respect to integrity. In many embodiments, the RMGR may include hardware and/or software support for a new instruction that enables efficient key reassignment for memory pages.

Abstract: There is disclosed in one example a computing apparatus, including: a cache; a caching agent (CA); an integrated input/output (IIO) block to provide a cache coherent interface to a peripheral device at a first speed; a core configured to poll an address within the cache via the CA, wherein the address is to receive incoming data from the peripheral device via the IIO, and wherein the core is capable of polling the address at a second speed substantially greater than the first speed; and a hardware uncore agent configured to: identify a collision between the core and the IIO including determining that the core is polling the address at a rate that is determined to interfere with access to the address by the IIO; and throttle the core's access to the address.

Abstract: Embodiments of the present disclosure propose quantum circuit assemblies with transmission lines and/or capacitors that include layer-conductors oriented perpendicular to a substrate (i.e. oriented vertically) or a qubit die, with at least portions of the vertical layer-conductors being at least partially buried in the substrate. Such layer-conductors may form ground and signal planes of transmission lines or capacitor plates of capacitors of various quantum circuit assemblies.

Abstract: An embodiment of a semiconductor apparatus may include technology to receive a request for storage-related resources, and demand-query one or more persistent storage media devices for device-determined performance-related information in response to the request, where the device-determined performance-related information is based on dynamically measured performance of persistent storage media of the device itself. Other embodiments are disclosed and claimed.

Abstract: Particular embodiments described herein provide for an electronic device that can be configured to determine that a packet needs a timestamp, determine an initial timestamp for a reference block, communicate the reference block to a monitor engine, receive an asynchronous pulse from the monitor engine after the monitor engine received the reference block, determine a synchronization timestamp for the asynchronous pulse, and determine the timestamp for the packet based on the initial timestamp for the reference block and the synchronization timestamp for the asynchronous pulse.

Abstract: Technology for a memory controller is described. The memory controller can receive a request from a data consumer node in a data center for training data. The training data indicated in the request can correspond to a model identifier (ID) of a model that runs on the data consumer node. The memory controller can identify a data provider node in the data center that stores the training data that is requested by the data consumer node. The data provider node can be identified using a tracking table that is maintained at the memory controller. The memory controller can send an instruction to the data provider node that instructs the data provider node to send the training data to the data consumer node to enable training of the model that runs on the data consumer node.

Abstract: Methods, apparatus, systems, and software for architectures and mechanisms to accelerate tuple-space search with integrated GPUs (Graphic Processor Units). One of the architectures employs GPU-side lookup table sorting, under which local and global hit count histograms are maintained for work groups, and sub-tables containing rules for tuple matching are re-sorted based on the relative hit rates of the different sub-tables. Under a second architecture, two levels of parallelism are implemented: packet-level parallelism and lookup table-parallelism. Under a third architecture, dynamic two-level parallel processing with pre-screen is implemented. Adaptive decision making mechanisms are also disclosed to select which architecture is optimal in view of multiple considerations, including application preferences, offered throughput, and available GPU resources.

Abstract: Embodiments of the present disclosure describe novel qubit device packages, as well as related computing devices and methods. In one embodiment, an exemplary qubit device package includes a qubit die and a package substrate, where the qubit die is coupled to the package substrate using one or more preforms. In particular, a single preform may advantageously be used to replace a plurality of individual contacts, e.g. a plurality of individual solder bumps, electrically coupling the qubit die to the package substrate. Such packages may reduce design complexity and undesired coupling, and enable inclusion of larger numbers of qubits in a single qubit die.

Abstract: A mechanism is described for facilitating hybrid tone mapping in camera systems according to one embodiment. A method of embodiments, as described herein, includes detecting a scene having a sequence of frames, and fusing the sequence of frames into a fused raw frame. The method may further include reconstructing the scene by performing global tone mapping and local tone mapping on the fused raw frame, and outputting an image reflecting the reconstructed scene based on the tone-mapped raw frame.

Abstract: In one aspect, an apparatus comprises a housing forming an internal cavity and a supercritical fluid enclosed in the internal cavity. The housing is configured to thermally couple to a heat-generating component. The supercritical fluid comprises a fluid in a supercritical state. In addition, the supercritical fluid is configured to transfer heat away from the heat-generating component.

Abstract: A method of handling integrated circuit dies with defects is provided. After forming a plurality of dies on one or more silicon wafers, test equipment may be used to identify defects on the dies and to create corresponding defect maps. The defect maps can be combined to form an aggregate defect map. Circuit design tools may create keep-out zones from the aggregate defect map and run learning experiments on each die, while respecting the keep-out zones, to compute design metrics. The circuit design tools may further create larger keep-out zones and run additional learning experiments on each die while respecting the larger keep-out zones to compute additional design metrics. The dies can be binned into different Stock Keeping Units (SKUs) based on one or more of the computed design metrics. Circuit design tools automatically respect the keep-out regions for these dies to program them correctly in the field.

Abstract: A processer is provided that includes on-die memory, a protected memory region, and a memory encryption engine (MEE). The MEE includes logic to: receive a request for data in a particular page in the protected region of memory, and access a pointer in an indirection directory, where the pointer is to point to a particular metadata page stored outside the protected region of memory. The particular metadata page includes a first portion of security metadata for use in securing the data of the particular page. The MEE logic is further to access a second portion of the security metadata associated with the particular page from the protected region of memory, and determine authenticity of the data of the particular page based on the first and second portions of the security metadata.

Abstract: An example apparatus for suppression of key phrase detection includes an audio receiver to receive generated audio from a loopback endpoint and captured audio from a microphone. The apparatus includes a self-trigger detector to detect a key phrase in the generated audio. The apparatus also includes a detection suppressor to suppress detection of the detected key phrase in the captured audio at a second key detector for a predetermined time in response to detecting the key phrase in the generated audio.

Abstract: An embodiment of a semiconductor package apparatus may include technology to determine if one or more co-located radio transmitters and radio receivers are in a tracked area, enable an active tracking mode if one or more of the co-located radio transmitters and radio receivers are determined to be in the tracked area, and periodically transmit identification information from at least one of the radio transmitters if the active tracking mode is enabled. Other embodiments are disclosed and claimed.

Abstract: A system, method, and computer readable medium for measuring limb range of motion. The method includes initializing a scanning area. A classifier trained to recognize limbs is loaded into memory. A frame representing a 3D point cloud having at least one limb of a person in motion is captured. A box fitting algorithm is performed on the captured at least one limb to enable the classifier to identify the at least one limb. One or more boxes generated from the box fitting algorithm are sliced into a plurality of 2D point clouds to measure and record the circumference of each 2D point cloud to obtain limb range of motion parameters. The limb range of motion parameters are a maximum and a minimum size of the at least one limb as a function of soft tissue expansion and contraction of the limb while under pressure, force, and/or motion.

Abstract: Embodiments of the present disclosure propose two methods for integrating vacancy centers (VCs) on semiconductor substrates for forming VC-based spin qubit devices. The first method is based on using a self-assembly process for integrating VC islands on a semiconductor substrate. The second method is based on using a buffer layer of a III-N semiconductor material over a semiconductor substrate, and then integrating VC islands in an insulating carbon-based material such as diamond that is either grown as a layer on the III-N buffer layer or grown in the openings formed in the III-N buffer layer. Integration of VC islands on semiconductor substrates typically used in semiconductor manufacturing according to any of these methods may provide a substantial improvement with respect to conventional approaches to building VC-based spin qubit devices and may promote wafer-scale integration of VC-based spin qubits for use in quantum computing devices.

Abstract: The disclosed embodiments generally relate to methods, systems and apparatuses to authenticate instructions on a memory circuitry. In an exemplary embodiment, the disclosure relates to a computing device (e.g., a memory protection engine) to protect integrity of one or more memory circuitry.

Abstract: A device includes a plurality of ports and a plurality of capability registers that correspond to a respective one of the plurality of ports. The device is to connect to one or more processors of a host device through the plurality of ports, and each of the plurality of ports comprises a respective protocol stack to support a respective link between the corresponding port and the host device according to a particular interconnect protocol. Each of the plurality of capability registers comprises a respective set of fields for use in configuration of the link between its corresponding port and one of the one or more processors of the host device. The fields include a field to indicate an association between the port and a particular processor, a field to indicate a port identifier for the port, and a field to indicate a total number of ports of the device.

Abstract: An embodiment of a semiconductor apparatus may include technology to receive an application-related checkpoint request corresponding to a file of a file system stored on a persistent storage media, and determine one or more checkpoint operations internal to the persistent storage media to perform the application-related checkpoint request. Other embodiments are disclosed and claimed.