Abstract: Aspects of the embodiments are directed to a port comprising hardware to support the multi-lane link, the link comprising a lane that comprises a first differential signal pair and a second differential signal pair. Link configuration logic, implemented at least in part in hardware circuitry, can determine that the port comprises hardware to support one or both of receiving data on the first differential signal pair or transmitting data on the second differential signal pair, and reconfigure the first differential signal pair to receive data with the second differential signal pair or reconfigure the second differential signal pair to transmit data with the first differential signal pair; and wherein the port is to transmit data or receive data based on reconfiguration of one or both the first differential signal pair and the second differential signal pair.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; a first dielectric material around a bottom portion of the fin; and a second dielectric material around a top portion of the fin, wherein the second dielectric material is different from the first dielectric material.

Abstract: An integrated circuit may include a printed circuit board and multiple processor sockets on the printed circuit board. Each of the multiple processor sockets is operable to receive a microprocessor and a programmable device. When a microprocessor is placed in a processor socket, that microprocessor may communicate with memory dual in-line memory modules (DIMMs). When a programmable device is placed in a processor socket, that programmable device may first be configured using a configuration DIMM and may then communicate with memory DIMMs during normal operation. The configuration DIMM may include multiple options for configuring the programmable device and may also provide additional management functions specifically tailored to the programmable device.

Abstract: Methods and apparatus relating to a physics-based approach for attack detection and/or localization in closed-loop controls for autonomous vehicles are described. In an embodiment, multiple state estimators are used to compute a set of residuals to detect, classify, and/or localize attacks. This allows for determination of an attacker's location and the kind of attack being perpetrated. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus to improve shared memory efficiency are described. In an embodiment, a first version of a code to access one or more registers as shared local memory is compiled. A second version of the same code is also compiled to access a cache as the shared local memory. The first version of the code is executed in response to comparison of a work group size of the code with a threshold value. Other embodiments are also disclosed and claimed.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer and a barrier layer; a first gate metal above the quantum well stack, wherein the barrier layer is between the first gate metal and the quantum well layer; and a second gate metal above the quantum well stack, wherein the barrier layer is between the second gate metal and the quantum well layer, and a material structure of the second gate metal is different from a material structure of the first gate metal.

Abstract: Disclosed herein are fabrication techniques for providing metal gates in quantum devices, as well as related quantum devices. For example, in some embodiments, a method of manufacturing a quantum device may include providing a gate dielectric over a qubit device layer, providing over the gate dielectric a pattern of non-metallic elements referred to as “gate support elements,” and depositing a gate metal on sidewalls of the gate support elements to form a plurality of gates of the quantum device.

Abstract: The present disclosure includes systems and methods for securing data direct I/O (DDIO) for a secure accelerator interface, in accordance with various embodiments. Historically, DDIO has enabled performance advantages that have outweighed its security risks. DDIO circuitry may be configured to secure DDIO data by using encryption circuitry that is manufactured for use in communications with main memory along the direct memory access (DMA) path. DDIO circuitry may be configured to secure DDIO data by using DDIO encryption circuitry manufactured for use by or manufactured within the DDIO circuitry. Enabling encryption and decryption in the DDIO path by the DDIO circuitry has the potential to close a security gap in modern data central processor units (CPUs).

Abstract: Embodiments of the present disclosure describe a method of fabricating spin qubit device assemblies that utilize dopant-based spin qubits, i.e. spin qubit devices which operate by including a donor or an acceptor dopant atom in a semiconductor host layer. The method includes, first, providing a pair of gate electrodes over a semiconductor host layer, and then providing a window structure between the first and second gate electrodes, the window structure being a continuous solid material extending between the first and second electrodes and covering the semiconductor host layer except for an opening through which a dopant atom is to be implanted in the semiconductor host layer. By using a defined gate-first process, the method may address the scalability challenges and create a deterministic path for fabricating dopant-based spin qubits in desired locations, promoting wafer-scale integration of dopant-based spin qubit devices for use in quantum computing devices.

Abstract: One embodiment provides a method. The method includes receiving, with a computing system, stylus orientation data representing an orientation of a stylus. The method includes receiving, with a computing system, grip characteristics data representing a grip on the stylus by a user. The method includes identifying, with the computing system, a stylus mode for use by the computing system, at least partially based on the stylus orientation data and the grip characteristics data. The method includes applying the stylus mode to the computing system to interpret interaction data representing interactions of the stylus with the computing system.

Abstract: Systems, apparatuses and methods may provide for technology that identifies a thread and selects a core from a plurality of processor cores in response to the selected core being available while satisfying a least used condition with respect to the plurality of processor cores. The technology may also schedule the thread to be executed on the selected core.

Abstract: A system may include a processor and a memory, the processor having at least one cache as well as memory access monitoring logic. The cache may include a plurality of sets, each set having a plurality of cache lines. Each cache line includes several bits for storing information. During normal operation, the memory access monitoring logic may monitor for a memory access pattern indicative of a side-channel attack (e.g., an abnormally large number of recent CLFLUSH instructions). Upon detecting a possible side-channel attack, the memory access monitoring logic may implement one of several mitigation policies, such as, for example, restricting execution of CLFLUSH operations. Due to the nature of cache-timing side-channel attacks, this prevention of CLFLUSH may prevent attackers utilizing such attacks from gleaning meaningful information.

Abstract: Disclosed herein are superconducting qubit devices with Josephson Junctions utilizing resistive switching materials, i.e., resistive Josephson Junctions (RJJs), as well as related methods and quantum circuit assemblies. In some embodiments, an RJJ may include a bottom electrode, a top electrode, and a resistive switching layer (RSL) disposed between the bottom electrode and the top electrode. Using the RSLs in Josephson Junctions of superconducting qubits may allow fine tuning of junction resistance, which is particularly advantageous for optimizing performance of superconducting qubit devices. In addition, RJJs may be fabricated using methods that could be efficiently used in large-scale manufacturing, providing a substantial improvement with respect to approaches for forming conventional Josephson Junctions, such as e.g. double-angle shadow evaporation approach.

Abstract: Devices, systems, and methods for transferring data between the memory domain and the storage domain are described. Transferring data between domains can comprise changing the validity of the block address of the data from one domain to the other, and updating a memory domain map and a storage domain map to reflect the transfer.

Abstract: Particular embodiments described herein provide for an electronic device that can be configured to receive a request for data, wherein the request is received on a system that regularly stores data in a cache and provide the requested data without causing the data or an address of the data to be cached or for changes to the cache to occur. In an example, the requested data is already in a level 1 cache, level 2 cache, or last level cache and the cache does not change its state. Also, a snoop request can be broadcasted to acquire the requested data and the snoop request is a read request and not a request for ownership of the data. In addition, changes to a translation lookaside buffer when the data was obtained using a linear to physical address translation is prevented.

Abstract: The disclosed embodiments generally relate to detecting malware through detection of micro-architectural changes (morphing events) when executing a code at a hardware level (e.g., CPU). An exemplary embodiment relates to a computer system having: a memory circuitry comprising an executable code; a central processing unit (CPU) in communication with the memory circuitry and configured to execute the code; a performance monitoring unit (PMU) associated with the CPU, the PMU configured to detect and count one or more morphing events associated with execution of the code and to determine if the counted number of morphine events exceed a threshold value; and a co-processor configured to initiate a memory scan of the memory circuitry to identify a malware in the code.

Abstract: An embodiment of a semiconductor apparatus may include technology to define a region for a backed-up portion of a volatile memory, and designate the region as a part of a nonvolatile memory. Other embodiments are disclosed and claimed.

Abstract: An embodiment of a semiconductor package apparatus may include technology to generate a first output from a physically unclonable function (PUF) based on a challenge, modify the challenge based on the first output, and generate a response based on the modified challenge. Some embodiments may additionally or alternatively include technology to change a read sequence of the PUF based on an output of the PUF. Some embodiments may additionally or alternatively include technology to vary a latency of a linear feedback shift register based on an output from the PUF. Other embodiments are disclosed and claimed.

Abstract: Systems, apparatuses and methods may provide for technology to conduct, by a storage device, a state analysis of the storage device based on an assert log associated with a failure condition in the storage device. The technology may also return, by the storage device, the storage device to service if the state analysis indicates that the storage device is operable. Additionally, the technology may remove, by the storage device, the storage device from service if the state analysis indicates that the storage device is inoperable.

Abstract: Various embodiments are generally directed to techniques for determining artificial neural network topologies, such as by utilizing probabilistic graphical models, for instance. Some embodiments are particularly related to determining neural network topologies by bootstrapping a graph, such as a probabilistic graphical model, into a multi-graphical model, or graphical model tree. Various embodiments may include logic to determine a collection of sample sets from a dataset. In various such embodiments, each sample set may be drawn randomly for the dataset with replacement between drawings. In some embodiments, logic may partition a graph into multiple subgraph sets based on each of the sample sets. In several embodiments, the multiple subgraph sets may be scored, such as with Bayesian statistics, and selected amongst as part of determining a topology for a neural network.

Abstract: An embodiment of a semiconductor package apparatus may include technology to identify a field of a data structure as a candidate for a size reduction, perform a runtime analysis on the field, and reduce the size of the field based on the runtime analysis. Other embodiments are disclosed and claimed.

Abstract: An embodiment of a semiconductor package apparatus may include technology to identify a nested loop in a set of executable instructions, and determine at runtime if the nested loop is a candidate for cache blocking. Other embodiments are disclosed and claimed.

Abstract: One aspect of the present disclosure provides a quantum circuit assembly that includes a substrate with one or more qubit devices, and at least one demultiplexer included in a single chip with the qubit device(s). The demultiplexer is configured to receive a combined signal from external electronics, the combined signal including a combination of a plurality of signals in different frequency ranges, and to demultiplex said plurality of signals within the combined signal. The demultiplexer is further configured to apply different demultiplexed signals to different lines of a single qubit device, or/and to different qubit devices. Providing such demultiplexers on-chip with the qubit devices advantageously allows reducing the number of input/output lines coupling the chip with qubit devices and the external electronics.

Abstract: An integrated circuit includes a built-in-self-test circuit that generates output test signals and a circuit tested by the built-in-self-test circuit. The circuit tested by the built-in-self-test circuit generates test results in response to the output test signals during a test. Pipeline register circuits are coupled together to form a signal path for transmitting the output test signals from the built-in-self-test circuit to the circuit tested by the built-in-self-test circuit. A functional circuit block is located in a reserved die area of the integrated circuit. The signal path is routed around the reserved die area to the circuit tested by the built-in-self-test circuit. At least a subset of the pipeline register circuits are located adjacent to at least two sides of the reserved die area.

Abstract: Logic may transform a target code to partition data automatically and/or autonomously based on a memory constraint associated with a resource such as a target device. Logic may identify a tag in the code to identify a task, wherein the task comprises at least one loop, the loop to process data elements in one or more arrays. Logic may automatically generate instructions to determine one or more partitions for the at least one loop to partition data elements, accessed by one or more memory access instructions for the one or more arrays within the at least one loop, based on a memory constraint, the memory constraint to identify an amount of memory available for allocation to process the task. Logic may determine one or more iteration space blocks for the parallel loops, determine memory windows for each block, copy data into and out of constrained memory, and transform array accesses.

Abstract: The present disclosure is directed to systems and methods for mitigating or eliminating the effectiveness of a side channel attack, such as a Spectre type attack, by limiting the ability of a user-level branch prediction inquiry to access system-level branch prediction data. The branch prediction data stored in the BTB may be apportioned into a plurality of BTB data portions. BTB control circuitry identifies the initiator of a received branch prediction inquiry. Based on the identity of the branch prediction inquiry initiator, the BTB control circuitry causes BTB look-up circuitry to selectively search one or more of the plurality of BTB data portions.

Abstract: Particular embodiments described herein provide for a thermal cooling system that is part of a device that includes a hole-in-motherboard configuration. The device can include a substrate, one or more dies on a top portion of the substrate, one or more printed circuit boards below the substrate, where the printed circuit boards are coupled to the substrate with solder balls, and one or more land side capacitors below the substrate. A thermal conducting plate, phase change material, and one or more sponge walls to help insulate the solder balls from the thermal conductive layer can be located in the hole of the hole-in-motherboard configuration and help transfer heat and thermal energy away from the device.

Abstract: The disclosed embodiments generally relate to methods, systems and apparatuses to authenticate instructions on a memory circuitry. In an exemplary embodiment, the disclosure relates to a computing device (e.g., a memory protection engine) to protect integrity of one or more memory circuitry.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a layer of gate dielectric above the quantum well stack; a first gate metal and a second gate metal above the layer of gate dielectric; and a gate wall between the first gate metal and the second gate metal, wherein the gate wall is above the layer of gate dielectric, and the gate wall includes a first dielectric material and a second dielectric material different from the first dielectric material.

Abstract: A shielded SODIMM system for reducing RF emissions of a SODIMM connector is disclosed herein. SODIMM connector RFI presently interferes with connectivity and is also an obstacle for higher speed memory applications. The shielded SODIMM system includes a SODIMM connector that is at least partially housed by a SODIMM connector shield, to partially and/or substantially reduce or block RF emissions from the SODIMM connector. The SODIMM connector shield is at least partially conductive and is coupled to landing pads on a surface of a motherboard printed circuit board (“PCB”). The landing pads of the motherboard PCB that are coupled to the SODIMM connector shield are coupled to ground, which grounds the SODIMM connector shield. Grounding the SODIMM connector shield that at least partially houses the SODIMM connector reduces RF emissions from the SODIMM connector during information transfer operations.

Abstract: One embodiment provides an apparatus. The apparatus includes last level cache circuitry and cache management circuitry. The last level cache circuitry stores cache blocks that at least partially include a subset of cache blocks stored by near memory circuitry. The near memory circuitry is configured in an n-way set associative format that references the cache blocks stored by the near memory circuitry using set identifiers and way identifiers. The cache management circuitry stores way identifiers for the cache blocks of the near memory circuitry within the cache blocks in the last level cache circuitry. Storing way identifiers in the cache blocks of the last level cache enables the cache management circuitry or memory controller circuitry to write back a cache block without reading tags in one or more ways of the near memory circuitry.

Abstract: Techniques and mechanisms for providing packaged circuitry. In an embodiment, first circuit structures are coupled to a release layer on a first side of a substrate, and second circuit structures are coupled to another release layer on a second side of the substrate. Respective portions of mold compound are variously injection molded or otherwise deposited around the first circuit structures and around the second circuit structures. The mold compound portions are cured while the first circuit structures and the second circuit structures are on opposite respective sides of the substrate. In another embodiment, the first circuit structures and the second circuit structures are separated from each other and from the substrate, after curing of the mold compound portions, to form distinct packaged devices.

Abstract: Techniques related to a method and system of robust speaker recognition activation are described herein. Such techniques apply keyphrase detection and speaker recognition to a subsequent phrase after detecting a waking keyphrase.

Abstract: An embodiment of a semiconductor package apparatus may include technology to map a collection of data into two or more mathematical graph representations of the data based on a configurable set of rules that one of preserves or enhances relationships or properties of the data, and organize the two or more graph representations into two or more clusters of data based on graph information entropy and one or more parameters. Other embodiments are disclosed and claimed.

Abstract: In some examples, a robot middleware system including a first robot middleware node, a second robot middleware node, and one or more secure encrypted type-enforced context message between the first robot middleware node and the second robot middleware node.

Abstract: A mechanism is described for facilitating hybrid tone mapping in camera systems according to one embodiment. A method of embodiments, as described herein, includes detecting a scene having a sequence of frames, and fusing the sequence of frames into a fused raw frame. The method may further include reconstructing the scene by performing global tone mapping and local tone mapping on the fused raw frame, and outputting an image reflecting the reconstructed scene based on the tone-mapped raw frame.

Abstract: Various embodiments of the present disclosure present quantum circuit assemblies implementing vertically-stacked parallel-plate capacitors. Such capacitors include first and second capacitor plates which are parallel to one another and separated from one another by a gap measured along a direction perpendicular to the qubit plane, i.e. measured vertically. Fabrication techniques for manufacturing such capacitors are also disclosed. Vertically-stacked parallel-plate capacitors may help increasing coherence times of qubits, facilitate use of three-dimensional and stacked designs for quantum circuit assemblies, and may be particularly advantageous for realizing device scalability and use of 300-millimeter fabrication processes.

Abstract: Particular embodiments described herein provide for an electronic device that can be configured to receive a request for a timestamp associated with a virtual machine, determine a current time from a timestamp counter, and subtract a timing compensation from the current time from the timestamp counter to create the timestamp, where the timing compensation includes an amount of time that execution of the virtual machine was suspended. In an example, a VM_EXIT instruction was used to suspend execution of the virtual machine and the timestamp counter was read before the VM_EXIT instruction was processed by a hypervisor.

Abstract: A multichip package may include at least a package substrate, a main die mounted on the package substrate, a transceiver die mounted on the package substrate, and an optical engine die mounted on the package substrate. The main die may communicate with the transceiver die via a first high-bandwidth interconnect bridge embedded in the package substrate. The transceiver die may communicate with the optical engine die via a second high-bandwidth interconnect bridge embedded in the package substrate. The transceiver die has physical-layer circuits that directly drive the optical engine. An optical cable can be connected directly to the optical engine of the multichip package.

Abstract: Devices for computing the sum of multiple Vector-Vector Dot-Products (VVDP) or multiple partial sums of VVDP can include a resistive memory array and a reduction circuit. The reduction circuit can be configured to determine a sum of a selected one or more of a plurality of bit lines of the resistive memory array. A VVDP reduction can be determined from the sum of the selected one or more of the plurality of bit lines.

Abstract: Techniques are provided for reduction of noise and nonlinear-echo. A methodology implementing the techniques according to an embodiment includes estimating transfer functions (TFs) of echo paths of audio signals received through a microphone array. The audio signals include speech signal, additive noise, and echo, the TF estimation based on the reference signal. The method also includes cancellation of linear components of the echo, based on the echo path TFs. The method further includes estimating an inverse square root of a covariance matrix of the additive noise, whitening the echo cancelled signals, and estimating a speech path RTF associated with the speech signal, based on the whitened echo cancelled signals. The method further includes performing beamforming on the whitened signals (such as weighted MVDR beamforming), based on the echo path TFs, the speech path RTF, and the estimated inverse square root additive noise covariance matrix.

Abstract: The present disclosure is directed to systems and methods that include cache operation storage circuitry that selectively enables/disables the Cache Line Flush (CLFLUSH) operation. The cache operation storage circuitry may also selectively replace the CLFLUSH operation with one or more replacement operations that provide similar functionality but beneficially and advantageously prevent an attacker from placing processor cache circuitry in a known state during a timing-based, side channel attack such as Spectre or Meltdown. The cache operation storage circuitry includes model specific registers (MSRs) that contain information used to determine whether to enable/disable CLFLUSH functionality. The cache operation storage circuitry may include model specific registers (MSRs) that contain information used to select appropriate replacement operations such as Cache Line Demote (CLDEMOTE) and/or Cache Line Write Back (CLWB) to selectively replace CLFLUSH operations.

Abstract: Various embodiments comprise prioritizing frequency allocations in thermally- or power-constrained computing devices. Computer elements may be assigned ‘weights’ based on their priorities. The computer elements with higher weights may receive higher frequency allocations to assure they receive priority in processing more quickly. The computer elements with lower weights may receive lower frequency allocations and suffer a slowdown in their processing. Elements with the same weight may be grouped together for the purpose of frequency allocation.

Abstract: Particular embodiments described herein provide for a system that can be configured to initialize a gateway, assign a range of tunnel endpoint identifiers (TEID) to the gateway, where the range of TEIDs are associated with the gateway, and communicate the range of TEIDs to routers, where each TEID in the range of TEIDs is used to by the router to route packets to the gateway. In an example, the range of TEIDS associated with the gateway are assigned to the gateway when the gateway was initialized and the gateway assigns the TEID for the session.

Abstract: An embodiment of a semiconductor apparatus may include technology to receive an application-related checkpoint request corresponding to a file of a file system stored on a persistent storage media, and determine one or more checkpoint operations internal to the persistent storage media to perform the application-related checkpoint request. Other embodiments are disclosed and claimed.

Abstract: An apparatus is provided which comprises: an input/output (I/O) port; a first circuitry to update an in-band presence detect field, based on communication via an in-band channel; a second circuitry to update an out-of-band presence detect field, based on communication via an out-of-band channel; and a third circuitry to update a presence detect state change field, wherein the third circuitry is to selectively ignore the out-of-band presence detect field and utilize the in-band presence detect field, while the third circuitry is to update the presence detect state change field.

Abstract: An integrated circuit package may include one or more integrated circuit dies and reconfigurable constrained vapor bubble (CVB) heat pipe structures formed on the integrated circuit dies. The reconfigurable CVB heat pipe structures may be adjusted using micro-electro-mechanical systems (MEMS) switches. By turning on a MEMS switch, the corresponding heat pipe structure will exhibit a first heat transfer efficiency. By turning off a MEMS switch, the corresponding heat pipe structure will exhibit a second heat transfer efficiency that is less than the first heat transfer efficiency. The reconfigurable CVB heat pipe structures may be statically programmed and/or dynamically adjusted as hot spot locations within the integrated circuit package migrate over time.

Abstract: An apparatus is provided, where the apparatus includes a plurality of input/output (I/O) ports and a controller. A first port, a second port, and a third port are to be respectively coupled to a first device with a first class type, a second device with a second class type, and a third device with a third class type. The controller is to determine that individual ones of the first and second devices are to perform asynchronous transfer with the apparatus, and that the third device is to perform a transfer that is different from the asynchronous transfer. The controller is to allocate bandwidth to the first and second I/O ports, based at least in part on the first class type and the second class type. The controller is to ignore the third class type, while allocating bandwidth to the third I/O port.

Abstract: Techniques are provided for speech denoising using a denoising neural network (NN) trained with deep feature losses obtained from an audio classifier NN. A methodology implementing the techniques according to an embodiment includes applying the speech denoising NN, to be trained, to a noisy sample of a training speech signal to generate a processed training speech signal. The method further includes applying a trained audio classifier NN to the processed training speech signal to generate a first set of activation features, and applying the trained audio classifier NN to a clean sample of the training speech signal to generate a second set of activation features. The method further includes calculating a loss value based on the first and second sets of activation features, and performing a back-propagation training update of the denoising NN, based on the loss value. The method includes iterating this process to further train the denoising NN.

Abstract: Techniques related to applying computer vision to decompressed video are discussed. Such techniques may include generating a region of interest in an individual video frame by translating spatial indicators of a first detected computer vision result from a reference video frame to the individual video frame and applying a greater threshold within the region of interest than outside of the region of interest for computer vision evaluation in the individual frame.