Abstract: A non-volatile memory device, a method of operating the non-volatile memory device, and a memory system including the non-volatile memory device are provided. A non-volatile memory device includes a memory cell array including a plurality of memory cells configured to be each programmed to one state of a plurality of states, a page buffer circuit including a plurality of page buffers configured to each store received data as state data indicating a target state of a corresponding one of the plurality of memory cells, the page buffer circuit being configured to perform a state data reordering operation of changing a first state data order into a second state data order during performance of a program operation on selected memory cells of the plurality of memory cells, and a reordering control circuit configured to control the page buffer circuit to perform the state data reordering operation simultaneously with the program operation.

Abstract: Provided is a method of fabricating a capacitor. The method of fabricating a capacitor may include forming a first electrode, forming a dielectric layer on the first electrode, forming a second electrode on the dielectric layer, and applying, between the first electrode and the second electrode, a voltage outside an operating voltage range applied during operation or a current outside an operating current range applied during operation.

Abstract: A method of operating a memory system that comprises a memory device including a plurality of memory blocks and a memory controller, includes detecting a first memory block having a degradation count greater than or equal to a first reference value by the memory controller. A first command for the first memory block is transmitted to the memory device by the memory controller. A first voltage is applied to all of a plurality of word lines connected to the first memory block and a second voltage to a bit line connected to the first memory block in response to the first command by the memory device. The first voltage is greater than a voltage applied to turn on memory cells connected to all of the plurality of word lines. The second voltage is greater than a voltage applied to the bit line during program, read or erase operations.

Abstract: A semiconductor device including a well region in a substrate, an impurity region in the well region, a first active fin on the impurity region, a second active fin on the well region, and a connection pattern penetrating the second active fin and connected to the well region may be provided. The substrate and the impurity region include impurities having a first conductivity type. The well region includes impurities having a second conductivity type different from the first conductivity type. The first active fin includes a plurality of first semiconductor patterns that are spaced apart from each other in a direction perpendicular to a top surface of the substrate. The first semiconductor patterns and the impurity region include impurities having the first conductivity type.

Abstract: An accelerator is disclosed. A circuit may process a data to produce a processed data. A first tier storage may include a first capacity and a first latency. A second tier storage may include a second capacity and a second latency. The second capacity may be larger than the first capacity, and the second latency may be slower than the first latency. A bus may be used to transfer at least one of the data or the processed data between the first tier storage and the second tier storage.

Abstract: A nanorod light emitting device, a method of manufacturing the same, and a display apparatus including the nanorod light emitting device are provided. The nanorod light emitting device includes a first semiconductor layer doped with a first conductivity type, a light emitting layer disposed on the first semiconductor layer, and a second semiconductor layer disposed on the light emitting layer and doped with a second conductivity type that is electrically opposite to the first conductivity type, wherein a distance between a lower surface of the first semiconductor layer and an upper surface of the second semiconductor layer is in a range of about 2 ?m to about 10 ?m, wherein a difference between a diameter of the upper surface of the second semiconductor layer and the lower surface of the first semiconductor layer is 10% or less of a diameter of the upper surface of the second semiconductor layer.

Abstract: An optical imaging system includes a first lens, a second lens, a third lens, a fourth lens, a fifth lens, a sixth lens, and a seventh lens sequentially disposed in ascending numerical order along an optical axis from an object side of the optical imaging system toward an imaging plane of an image sensor, wherein TTL/(2*IMG HT)?0.67 is satisfied, where TTL is a distance along the optical axis from an object-side surface of the first lens to the imaging plane of the image sensor, and IMG HT is one half of a diagonal length of the imaging plane of the image sensor, and 15<v1-v3<45 is satisfied, where v1 is an Abbe number of the first lens, and v3 is an Abbe number of the third lens.

Abstract: A capacitor component includes a body, including a dielectric layer and an internal electrode layer, and an external electrode disposed on the body and connected to the internal electrode layer. A region, containing nickel (Ni) and carbon (C), is present between the internal electrode layer and the dielectric layer.

Abstract: A method for operating a memory controller, the method including: receiving a first command from a first host; storing the first command in a queue; when the first command has a higher priority than a second command currently being performed, pausing an operation of the second command and performing a read operation of the first command; and continuing the operation of the second command after completion of the read operation of the first command.

Abstract: A wafer processing method includes supplying a first process gas into a wafer processing apparatus, lowering a temperature of the wafer, generating plasma using the first process gas, supplying a second process gas and mixing the second process gas with the plasma, performing a plasma process on the wafer using the plasma and the second process gas, and performing an annealing process on the wafer on which the plasma process has been performed. The lowering of the temperature of the wafer includes increasing an internal pressure of the wafer processing apparatus.

Abstract: A method for performing a data read-write operation across multiple zoned storage devices includes reading data from at least one zone of a source zoned storage device and sequentially writing the read data to at least one zone of a destination zoned storage device, where the source zoned storage device is different from the destination zoned storage device.

Abstract: A memory device accessed by circuits operating based on a first supply voltage. The memory device includes a cell array electrically connected to a plurality of word lines and a plurality of bit lines; a row driver configured to select one word line of the plurality of word lines based on a row address; a precharge circuit configured to precharge the plurality of bit lines based on the first supply voltage; a column driver configured to select at least one bit line of the plurality of bit lines based on a column address; and a read circuit configured to read data stored in the cell array through the at least one bit line. The cell array, the row driver, the column driver, and the read circuit operate based on a second supply voltage, which is higher than the first supply voltage.

Abstract: A semiconductor memory device includes a test pattern data storage configured to store test write pattern data in response to a register write command and a register address and output test read pattern data in response to a test read command and a test pattern data selection signal during a test operation, a memory cell array including a plurality of memory cells and configured to generate read data, a read path unit configured to generate n read data, by serializing the read data, and a test read data generation unit configured to generate n test read data, by comparing the test read pattern data with each of the n read data, generated at a first data rate, and generate the n test read data, at a second data rate lower than the first data rate, during the test operation.

Abstract: A display device includes a first electrode stem and a second electrode stem extended in a first direction and spaced from each other, a first electrode branch branching off from the first electrode stem and extended in a second direction, a second electrode branch branching off from the second electrode stem and extended in the second direction, a third electrode between the first electrode branch and the second electrode branch and one or more light-emitting elements between the first electrode branch and the third electrode and between the third electrode and the second electrode branch, wherein the third electrode is extended in the second direction, and both ends of the third electrode in the second direction are spaced from the first electrode stem and from the second electrode stem, respectively.

Abstract: A display device, a method of manufacturing the same and a tiled display device including the same are provided. The display device includes a substrate including a first contact hole, a laser absorption layer on the substrate and containing amorphous silicon, a first barrier insulating layer on the laser absorption layer, a fan-out line on the first barrier insulating layer as a first metal layer and including a pad portion in a second contact hole located in the first barrier insulating layer and the laser absorption layer, a display layer on the fan-out line, and a flexible film under the substrate and in the first contact hole and electrically connected to the pad portion.

Abstract: A white light emitting device is provided. The white light emitting device includes a blue light emitting diode configured to emit blue light having a peak wavelength in a first range of 440 nm to 455 nm; a first wavelength conversion material, based on being excited by the blue light, emits first light having a peak wavelength in a second range of 535 nm to 550 nm and a full width at half maximum (FWHM) of 60 nm or less; and a second wavelength conversion material, based on being excited by the blue light, emits second light having a peak wavelength in a third range of 620 nm to 660 nm, wherein a melanopic photopic ratio of white light emitted from the white light emitting device is 0.65 or less, and a color rendering index (CRI) of the white light is 80 or more.

Abstract: The present disclosure relates to a communication technique and a system for integrating IoT technology with a 5G communication system which supports a higher data transfer rate than does a 4G system. The present disclosure can be applied to intelligent services (for example, smart homes, smart buildings, smart cities, smart cars or connected cars, health care, digital education, retail businesses, security and safety related services, etc.) on the basis of 5G communication technology and IoT-related technology.

Abstract: Methods and systems for handling emergency services in a wireless network. A method disclosed herein includes enabling at least one User Equipment (UE) supporting only Closed Access Group (CAG) cell/non-public network (NPN) to camp onto at least one non-CAG cell/public network cell to access the emergency services. The method further includes enabling the at least one UE to switch behavior of a timer from a periodic registration timer with a “Strictly Periodic Registration Timer Indication” to a normal periodic registration timer/pre-release 16 behavior for performing the emergency services.

Abstract: A method of designing a layout of a semiconductor device, includes: preparing a standard cell library including information on standard cells; determining a layout of a common pattern region in consideration of a local layout effect based on the standard cell library; adding the common pattern region having a cell height that is identical to a cell height of each of the standard cells to opposite sides of one or more of the standard cells; and arranging the standard cells to share the common pattern region between at least one pair of adjacent ones of the standard cells.

Abstract: The chuck for supporting a target substrate for a display device, the chuck includes: a base having a first surface to support an object and a second surface opposite the first surface, the first surface including a first area and a second area; and indentations formed in the second area and recessed from the first area in a thickness direction of the base. The indentations include a first indentation extending in a first direction and a second indentation extending in a second direction intersecting the first direction.

Abstract: A multi-bit cell includes: a memory storing a weight resistance corresponding to a multi-bit weight; a current source configured to apply a current to the memory to generate a weight voltage from the weight resistance; a plurality of multiplexers connected to each other in parallel and connected to the memory in series, each of the multiplexers being configured to output one signal of the weight voltage and a first fixed voltage based on a multi-bit input; and a plurality of capacitors connected to the plurality of multiplexers, respectively, each of the capacitors being configured to store a respective weight capacitance, and to generate charge data by performing an operation on the outputted signal and the weight capacitance.

Abstract: Provided is a semiconductor device including a front-end-of-line (FEOL) structure and a back-end-of-line (BEOL) structure connected to the FEOL structure, wherein the FEOL structure includes at least one source/drain region and at least one gate structure, and the BEOL structure includes: a plurality of 1st fine metal lines arranged in a row with a same pitch, each of the plurality of 1st fine metal lines having a same width; and at least one 1st wide metal line formed at a side of the plurality of 1st fine metal lines, the 1st wide metal line having a width greater than the width of the 1st fine metal line, and wherein each of the plurality of 1st fine metal lines includes a material different from a material included in the 1st wide metal line.

Abstract: An electronic device and method are disclosed. The device implements the method, including: receiving an utterance using a microphone, obtaining an image using a camera, transmitting by communication circuitry the utterance and/or the image to a server, receiving from the server operational information based on the transmission, executing a task corresponding to the received operational information, wherein the operational information further causes display of a first screen including first objects at a first size, and a change of the first screen to a second screen, based on a user movement indicated in the first image, the second screen including second objects displayed at a second size different from the first size, and having a count different from a count of the first objects.

Abstract: A device including a first structure and a second structure is provided.

Abstract: The inventive concepts provide a method of providing a stochastic prediction system. The method includes extracting contours of patterns corresponding to a first design layout from a plurality of scanning electron microscope (SEM) images, respectively, generating a first contour histogram image based on the contours, and training a stochastic prediction model by using the first contour histogram image as an output, and by using the first design layout and a first resist image, a first aerial image, a first slope map, a first density map, and/or a first photo map corresponding to the first design layout as inputs, in which the stochastic prediction model comprises a cycle generative adversarial network (GAN).

Abstract: A semiconductor package includes a first semiconductor chip comprising a semiconductor substrate and a redistribution pattern on a top surface of the semiconductor substrate, the redistribution pattern having a hole exposing an inner sidewall of the redistribution pattern, a second semiconductor chip on a top surface of the first semiconductor chip, and a bump structure disposed between the first semiconductor chip and the second semiconductor chip. The bump structure is disposed in the hole and is in contact with the inner sidewall of the redistribution pattern.

Abstract: A method for dynamic calibration correction in multi-frame, multi-exposure capture in a camera system includes receiving an amplified non-reference frame (e.g., with non-standard exposure value EV-4) to which a digital gain was applied and a reference frame (e.g., with standard exposure value EV0). The method includes generating a mask based on the reference frame and the amplified non-reference frame. The method includes estimating a scaling coefficient and an offset coefficient for each of a number of channels in the amplified non-reference frame, based on selected pixel locations in the generated mask. The method includes correcting a calibration of the amplified non-reference frame by applying the scaling coefficients for each of the channels. The method also includes outputting a calibration-corrected amplified non-reference frame to a multi-frame processor.

Abstract: According to various embodiments, an electronic device may comprise a housing, a plate coupled to the housing to reciprocate, a flexible display including a first portion disposed on the plate and a second portion extending from the first portion and exposed to an outside or retracted into an inside of the housing as the plate reciprocates, a motor configured to move the plate, at least one electronic component, a battery, and at least one processor. The at least one processor may be configured to identify an event for triggering a movement of the plate, identify a first power of the battery and a second power for controlling the flexible display and the at least one electronic component, based on the event, identify a third power for controlling the motor, based on the first power and the second power, and provide the motor with a signal corresponding to the third power.

Abstract: A method includes obtaining, using at least one processor, audio/video content. The method also includes processing, using the at least one processor, the audio/video content with a trained attention-based machine learning model to classify the audio/video content. Processing the audio/video content includes, using the trained attention-based machine learning model, generating a global representation of the audio/video content based on the audio/video content, generating a local representation of the audio/video content based on different portions of the audio/video content, and combining the global representation of the audio/video content and the local representation of the audio/video content to generate an output representation of the audio/video content. The audio/video content is classified based on the output representation.

Abstract: A display device includes a display panel including a plurality of first pixels disposed in a first display area and a plurality of second pixels disposed in a second display area adjacent to the first display area, a gate driver disposed in the second display area of the display panel to overlap a portion of the second pixels and driving the first and second pixels, a controller receiving image data and converting the image data to image signals, and a data driver converting the image signals to data signals and outputting the data signals to the first and second pixels. The controller compensates for effective data corresponding to the second pixels and reflects the compensated effective data to the image signals.

Abstract: Systems and methods for predicting a location of a target vehicle are disclosed. A processor receives trajectory information for the target vehicle and determines a trajectory feature based on the trajectory information. The processor further determines a lane feature of a lane within a threshold vicinity of the target vehicle, and determines a probability associated with the lane based on the trajectory feature and the lane feature. The lane that the vehicle may enter is identified based on the probability. The processor may also generate interactive features of interactions between the target vehicle and other vehicles. The processor predicts a location of the target vehicle in an upcoming time period based on the lane feature and the trajectory feature. In some embodiments, the interactive features are also used for the prediction.

Abstract: An electronic device includes: a display panel, a display driving circuit, and at least one processor operatively connected to the display driving circuit. The at least one processor may be configured to: determine a resolution of each of a plurality of applications, and generate a frame image including regions corresponding to execution screens of the plurality of applications and determined resolutions of the plurality of applications, based at least partially on the resolutions of the plurality of applications and/or information on a display region corresponding to the execution screens of the plurality of applications on the display panel, and transmit, to the display driving circuit, the frame image and coordinate information of each of the regions included in the frame image.

Abstract: A display device is disclosed that includes a plurality of pixels and a plurality of code pixels. The pixels include light-emitting elements, which display an image. The code pixels are disposed in the same layer as the pixels and are adjacent to a reference point disposed between the pixels. The code pixels include infrared light-emitting elements, which emit infrared light. At least one of the code pixels, disposed in a particular direction from the reference point, emit the infrared light to provide a code pattern having position information.

Abstract: An organic light-emitting display apparatus including an organic light-emitting diode emitting visible light, a driving thin film transistor driving the organic light-emitting diode, and a compensation thin film transistor. The compensation thin film transistor includes a compensation gate electrode, a compensation semiconductor layer, a compensation source electrode, and a compensation drain electrode. The compensation gate electrode includes a first gate electrode, and a second gate electrode electrically connected to the first gate electrode. The compensation drain electrode is electrically connected to the driving gate electrode of the driving thin film transistor.

Abstract: An electronic device, method, and computer readable medium for an invertible wavelet layer for neural networks are provided. The electronic device includes a memory and at least one processor coupled to the memory. The at least one processor is configured to receive an input to a neural network, apply a wavelet transform to the input at a wavelet layer of the neural network, and generate a plurality of subbands of the input as a result of the wavelet transform.

Abstract: A method and apparatus for authenticating a user based on an utterance input includes obtaining an input audio signal based on the utterance input of the user; obtaining, from the input audio signal, at least one audio signal of an utterance section and at least one audio signal of a non-utterance section; generating environment information indicating an environment in which the utterance input is received, based on the at least one audio signal of the non-utterance section; obtaining a result of a comparison between the generated environment information and registration environment information indicating an environment in which a registration utterance input corresponding to a previously registered registration audio signal corresponding to the user is received; adjusting an authentication criterion for authenticating the user based on the result of the comparison; and authenticating the user based on the adjusted authentication criterion and the input audio signal.

Abstract: An integrated circuit (IC) device includes first and second fin-type semiconductor active regions on a substrate. A plurality of first semiconductor patterns are provided, which are stacked on the first fin-type active region as a first plurality of spaced-apart channel regions of a first FINFET. A plurality of second semiconductor patterns are provided, which are stacked on the second fin-type active region as a second plurality of spaced-apart channel regions of a second FINFET. A first gate structure is provided on the plurality of first semiconductor patterns. This first gate structure includes a first material region, which at least partially fills spaces between the first plurality of spaced-apart channel regions. A second gate structure is also provided on the plurality of second semiconductor patterns. The second gate structure includes second and third material regions, which at least partially fill spaces between the second plurality of spaced-apart channel regions.

Abstract: Provided are a receptacle connector configured to avoid damage to conductors of the receptacle connector. The receptacle connector includes a plurality of connection terminals, a mold structure which comprises a front part exposing each of the connection terminals and a support part disposed on a rear end of the front part and surrounding each of the connection terminals, and a shield which is disposed on the support part and comprises a conductive material, wherein the support part comprises a flat part which includes a surface along which the shield extends and a protruding part which protrudes from the surface of the flat part and is disposed in front of a front end of the shield. The protruding part is configured to avoid damage to conductors of the receptacle when a plug is mated to the receptacle.

Abstract: A micro light emitting display apparatus and a method of manufacturing the micro light emitting display apparatus are disclosed. The micro light emitting display apparatus includes a micro light emitting element, a driving transistor connected to the micro light emitting element, a switching transistor connected to the driving transistor, and a first opening is provided to expose a source region or a drain region of the switching transistor, and a gate electrode of the driving transistor is provided in the first opening and in contact with the source region or the drain region of the switching transistor.

Abstract: A display device relating to a method of operating thereof, including: a display panel having a touch sensing unit to sense an external touch and a display unit including a plurality of pixels; a fingerprint sensing panel to sense a fingerprint disposed on one surface of the display unit, the fingerprint sensing panel having a plurality of fingerprint sensing pixels respectively connected to a plurality of fingerprint scan lines and a plurality of fingerprint sensing lines, and a fingerprint scan driving circuit to drive one or more fingerprint scan lines included in a sensing area; and a read-out circuit to output a selection signal for selecting a sensing area of the fingerprint sensing panel.

Abstract: A semiconductor device includes; an active region extending in a first horizontal direction on a substrate, source/drain regions disposed on the active region, a buried trench formed between the source/drain regions, a buried insulating layer surrounding both side walls of the buried trench in the first horizontal direction between the source/drain regions, a wing trench formed in a lower part of the buried trench and having a width greater than a width of the buried trench, and a gate electrode extending in a second horizontal direction on the active region, and disposed within each of the buried trench and the wing trench.

Abstract: The present disclosure relates to a communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT). The present disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. The present disclosure provides a method and a device for allocating transmission power in a wireless communication system.

Abstract: A semiconductor device includes an active region extending from a substrate in a vertical direction, source/drain regions spaced apart from each other on the active region, a fin structure between the source/drain regions on the active region, the fin structure including a lower semiconductor region on the active region, a stack structure having alternating first and second semiconductor layers on the lower semiconductor region, a side surface of at least one of the first semiconductor layers being recessed, and a semiconductor capping layer on the stack structure, an isolation layer covering a side surface of the active region, a gate structure overlapping the fin structure and covering upper and side surfaces of the fin structure, the semiconductor capping layer being between the gate structure and each of the lower semiconductor region and stack structure, and contact plugs electrically connected to the source/drain regions.

Abstract: A method of performing a random access of a user equipment (UE) in a wireless communication system includes receiving configuration related to the random access from a base station (BS), when the random access is triggered, determining whether to perform a first random access procedure or a second random access procedure, based on the received configuration information related to the random access, and performing, based on a result of the determining, the random access according to the first random access procedure or the second random access procedure.

Abstract: A semiconductor device includes an active pattern which includes a lower pattern, and a sheet pattern that is spaced apart from the lower pattern in a first direction, a gate structure on the lower pattern that includes a gate electrode that surrounds the sheet pattern, the gate electrode extending in a second direction that is perpendicular to the first direction, and a source/drain pattern on the lower pattern and in contact with the sheet pattern. A contact surface between the sheet pattern and the source/drain pattern has a first width in the second direction, and the sheet pattern has a second width in the second direction that is greater than the first width.

Abstract: The present disclosure provides a grant free uplink transmission method, the method is performed at a user equipment side, comprising: determining, according to configuration information for grant free uplink transmission received from a base station, a radio network temporary identifier GF-RNTI for grant free uplink transmission, and transmitting an uplink signal; and monitoring feedback from the base station in a downlink control channel by using the determined GF-RNTI. The present disclosure also provides a user equipment and a base station for grant free uplink transmission.

Abstract: A capacitor component includes a body, including a dielectric layer and an internal electrode layer, and an external electrode disposed on one surface of the body. The external electrode includes a conductive base and a glass disposed in the conductive base, and the glass includes 0.01 wt % or more to 5.8 wt % or less of nitrogen (N) based on a total weight of the glass.

Abstract: An artificial intelligence (AI) upscaling apparatus for upscaling a low-resolution image to a high-resolution image includes: a memory storing one or more instructions; and a processor configured to execute the one or more instructions stored in the memory, wherein the processor is configured to: obtain a second image corresponding to a first image, which is downscaled from an original image by an AI downscaling apparatus by using a first deep neural network (DNN); and obtain a third image by upscaling the second image by using a second DNN corresponding to the first DNN, and wherein the second DNN is trained to minimize a difference between a first restored image, which results from applying no pixel movement to an original training image, and second restored images, which result from downscaling, upscaling, and subsequently retranslating one or more translation images obtained by applying pixel movement to the original training image.

Abstract: A multilayer electronic component according to an exemplary embodiment of the present disclosure may control connectivity of an end of an internal electrode, thereby suppressing occurrence of a short circuit between the internal electrodes, reduced capacitance or lower breakdown voltage. The internal electrode may include a plurality of conductor portions and a plurality of cut-off portions.

Abstract: A method of decoding a motion vector includes: obtaining information indicating a motion vector resolution (MVR) of a current block from a bitstream, selecting one candidate block from among at least one candidate block, based on the MVR of the current block; and obtaining a motion vector of the current block corresponding to the MVR, by using a motion vector of the determined one candidate block as a prediction motion vector of the current block.