Abstract: A display panel, a display driving method and a display pixel driving circuit therefor are provided. In the display driving method, the light emitting signal includes multiple pulse signals, and the variation trend of the pulse-off durations of the pulse signals is consistent with the variation trend of the light emitting brightness of the light emitting element during the light emitting period, that is, the pulse-off durations decreases sequentially with the decrease of the light emitting brightness of the light emitting element, or sequentially increases with the increase of the light emitting brightness of the light emitting element. Therefore, the flicker problem in the display panel when emitting light can be solved, and improving the image display quality.

Abstract: A chip packaging method begins by fixing a chip to the top side of a substrate. The chip is then encapsulated in an encapsulant. After that, the encapsulant is drilled from its top side in order to have a through hole adjacent to the chip. Lastly, an area extending between the chip and the through hole and the hole wall of the through hole are plated with an electrically conductive metal to enable electrical connection between the chip and the substrate through the electrically conductive metal. The chip packaging method solves the problems of the conventional wire bonding method, simplifies the packaging process, and provides the packaged chips with high transmission efficiency.

Abstract: A natural human-computer interaction system based on multi-sensing data fusion comprises a MEMS anti tracking device, a visual tracking device, a force feedback device and a PC terminal. The MEMS arm tracking device is composed of three sets of independent MEMS sensors for collecting arm joint angle information and measuring an arm motion trajectory. The visual tracking device is composed of a binocular camera for collecting image information and measuring a finger motion trajectory. The force feedback device is mounted in a palm of an operator for providing a feedback force to the finger. The PC terminal comprises a data display module, an arm motion calculating module, an image processing module, a mechanics calculating module and a virtual scene rendering module. The system tracks the arm motion trajectory and the finger motion trajectory of the operator and provides force feedback interaction to the finger of the operator.

Abstract: An interconnect structure is provided. The interconnect structure includes a first metal line. The first metal line includes a first conductive material disposed within a first dielectric layer over a substrate and a second conductive material disposed within the first dielectric layer and directly over a top of the first conductive material. The second conductive material is different from the first conductive material. A second dielectric layer is disposed over the first dielectric layer. A first via comprising a third conductive material is disposed within the second dielectric layer and on a top of the second conductive material. The second conductive material and the third conductive material have lower diffusion coefficients than the first conductive material.

Abstract: Stacked finFET structures including a fin having at least a first layer of semiconductor material stacked over or under a second layer of semiconductor material. The first and second layers may include a Group IV semiconductor material layer and a Group III-V semiconductor material layer, for example. A stacked finFET may include an N-type finFET stacked over or under a P-type finFET, the two finFETs may have channel portions within the different semiconductor material layers. Channel portions of the first and second layers of semiconductor material may be coupled to separate gate electrodes that are vertically aligned. Channel portions of the first and second layers of semiconductor material may be vertically separated by subfin portions of the first and second layers. Different layers of dielectric material adjacent to the subfin portions may improve electrical isolation between the channel portions, for example as a source of fixed charge or impurity dopants.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The method includes: preparing a semiconductor substrate; sequentially forming an oxide layer and a sacrificial layer on the semiconductor substrate, the thickness of the oxide layer is a first thickness; forming a plurality of trenches in the semiconductor substrate, wherein the trenches extending from the sacrificial layer into the semiconductor substrate; forming an isolation dielectric layer on the plurality of trenches and the sacrificial layer, and removing the isolation dielectric layer on the sacrificial layer to form a plurality of isolation structures; forming a well region in the semiconductor substrate; processing the oxide layer by an etching process, so that the thickness of the oxide layer is equal to a second thickness, the first thickness is greater than the second thickness; and forming a polysilicon gate on the etched oxide layer.

Abstract: The invention relates to a display for an electronic measurement device, wherein the display is configured to display a graphical user interface, wherein the display is configured to detect a first and a second user input on the graphical user interface, wherein the display is configured to determine a change of a numeric value of the electronic measurement device based on the first user input, and wherein the display is configured to determine a resolution and/or a value range for the change of the numerical value based on the second user input.

Abstract: A method and an apparatus for sending a VR image, to improve accuracy of an image compression ratio determined when a VR image is sent. The method includes: receiving, by a VR host, first motion information sent by a VR device, where the first motion information is used to indicate a current motion status of the VR device; determining, by the VR host, a first image compression ratio based on the motion information; compressing, by the VR host, a to-be-sent VR image based on the first image compression ratio; and sending, by the VR host, the compressed VR image to the VR device.

Abstract: Semiconductor-on-insulator (SOI) field effect transistors (FETs) including body regions having different thicknesses may be formed on an SOI substrate by selectively thinning a region of a top semiconductor layer while preventing thinning of an additional region of the top semiconductor layer. An oxidation process or an etch process may be used to thin the region of the top semiconductor layer, and a patterned oxidation barrier mask or an etch mask may be used to prevent oxidation or etching of the additional portion of the top semiconductor layer. Shallow trench isolation structures may be formed prior to, or after, the selective thinning processing steps. FETs having different depletion region configurations may be formed using the multiple thicknesses of the patterned portions of the top semiconductor layer. For example, partially depleted SOI FETs and fully depleted SOI FETs may be provided.

Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device includes an insulating layer, a semiconductor layer, a plurality of isolation structures, a transistor, a first contact, a plurality of silicide layers, and a protective layer. The semiconductor layer is disposed on a front side of the insulating layer. The plurality of isolation structures are disposed in the semiconductor layer. The transistor is disposed on the semiconductor layer. The first contact is disposed beside the transistor and passes through one of the plurality of isolation structures and the insulating layer therebelow. The plurality of silicide layers are respectively disposed on a bottom surface of the first contact and disposed on a source, a drain, and a gate of the transistor. The protective layer is disposed between the first contact and the insulating layer.

Abstract: The present disclosure provides a package device and a manufacturing method thereof. The package device includes a redistribution layer which includes a first dielectric layer, a conductive layer and a second dielectric layer. The conductive layer is disposed between the first dielectric layer and the second dielectric layer. The redistribution layer has a test pattern that includes a first conductive pattern, and the first conductive pattern is formed of the conductive layer.

Abstract: Provided is a method for manufacturing a 14 nm-node BEOL 32 nm-width metal. A semiconductor structure for manufacturing BEOL wire is provided, wherein the semiconductor structure at least comprises a carbon coating and intermediate layer on it; forming a photoresist layer on the intermediate layer and exposing the photoresist layer according to a layout; developing the exposed photoresist layer by using a developing solution, and causing the developed photoresist to react with the intermediate layer in a contact region of the developed photoresist to form a peg groove; and etching by using the groove in the semiconductor structure to form a 14 nm-node BEOL 32 nm-width metal. This application can reducing the longitudinal shrink of the metal wire, achieving the improvement of the lateral and longitudinal shrink uniformity, reducing defects caused by misalignment of the through hole and the metal wire, and increasing the effective usable area of a chip.

Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming source/drain regions over the fin on opposing sides of the gate structure; forming a first dielectric layer and a second dielectric layer successively over the source/drain regions; performing a first etching process to form an opening in the first dielectric layer and in the second dielectric layer, where the opening exposes an underlying electrically conductive feature; after performing the first etching process, performing a second etching process to enlarge a lower portion of the opening proximate to the substrate; and forming a contact plug in the opening after the second etching process.

Abstract: A device includes an active region, a gate structure, an epitaxial structure, an epitaxial layer, a metal alloy layer, a contact, and a contact etch stop layer. The gate structure is across the active region. The epitaxial structure is above the active region and adjacent the gate structure. The epitaxial layer is above the epitaxial structure. The metal alloy layer is above the epitaxial layer. The contact is above the metal alloy layer. The contact etch stop layer lines sidewalls of the epitaxial structure. The metal alloy layer is spaced apart from the contact etch stop layer.

Abstract: An organic light emitting display panel and a display device are provided. The organic light emitting display panel includes: an anode power wire, the anode power wire including a first extension segment and a second extension segment, a head end of the first extension segment being electrically connected to the driving power supply, a tail end of the first extension segment being electrically connected to a head end of the second extension segment; each sub-pixel includes a light emitting device and two pixel driving circuits, anode connection terminals of the two pixel driving circuits are electrically connected to an anode of the light emitting device; anode power wire connection terminals of the two pixel driving circuits are electrically connected to the first extension segment and the second extension segment, respectively.

Abstract: Approaches for foil-based metallization of solar cells and the resulting solar cells are described. For example, a method of fabricating a solar cell involves locating a metal foil above a plurality of alternating N-type and P-type semiconductor regions disposed in or above a substrate. The method also involves laser welding the metal foil to the alternating N-type and P-type semiconductor regions. The method also involves patterning the metal foil by laser ablating through at least a portion of the metal foil at regions in alignment with locations between the alternating N-type and P-type semiconductor regions. The laser welding and the patterning are performed at the same time.

Abstract: A display device includes a plurality of sub-pixels. Each sub-pixel includes a light-emitting element, a write transistor connected to a data signal line, and a drive transistor that controls a current that flows through the light-emitting element. The plurality of sub-pixels arranged along a first data signal line include adjacent sub-pixels that emit different colors of light, and each include the write transistor having a conduction terminal electrically connected to the first data signal line. The plurality of sub-pixels arranged along a second data signal line include adjacent sub-pixels that emit different colors of light, and each include the write transistor having a conduction terminal electrically connected to the second data signal line.

Abstract: A method for manufacturing a semiconductor device is provided. The method comprises the steps of providing a semiconductor body, forming a trench in the semiconductor body in a vertical direction which is perpendicular to the main plane of extension of the semiconductor body, and coating inner walls of the trench with an isolation layer. The method further comprises the steps of coating the isolation layer at the inner walls with a metallization layer, coating a top side of the semiconductor body, at which the trench is formed, at least partially with an electrically conductive contact layer, where the contact layer is electrically connected with the metallization layer, coating the top side of the semiconductor body at least partially and the trench with a capping layer, and forming a contact pad at the top side of the semiconductor body by removing the contact layer and the capping layer at least partially. Furthermore, a semiconductor device is provided.

Abstract: A light emitting display panel and a light emitting display apparatus using the same are disclosed, in which a gate driver is built in a display area and a low voltage supply line is provided in a non-display area. Each pixel in the display area includes a light emitting diode and a pixel driving circuit for driving the light emitting diode. The light emitting diode is connected with a high voltage line to which a first driving voltage is supplied, and is connected with a display area low voltage supply line to which a second driving voltage is supplied.

Abstract: A device includes a gate stack; a gate spacer on a sidewall of the gate stack; a source/drain region adjacent the gate stack; a silicide; and a source/drain contact electrically connected to the source/drain region through the silicide. The silicide includes a conformal first portion in the source/drain region, the conformal first portion comprising a metal and silicon; and a conformal second portion over the conformal first portion, the conformal second portion further disposed on a sidewall of the gate spacer, the conformal second portion comprising the metal, silicon, and nitrogen.