Abstract: A display device includes a display panel, a controller, and a data driver. The display panel includes a plurality of pixels. The controller detects a logo region including a logo in image data, determines a correction gain based on a first average gray level of the logo region and a second average gray level of a peripheral region adjacent to the logo region, and generates corrected image data by correcting the image data based on the correction gain. The data driver provides data signals to the plurality of pixels based on the corrected image data.

Abstract: An electronic device includes display driver and a sensor driver. The display driver drives a display layer and provide a grayscale voltage to a data lines. The sensor driver is synchronized with the display driver to drive a sensor layer, and operates in a first sensing mode and a second sensing mode. In the first sensing mode, the sensor driver senses an input through the sensor layer based on a first timing. In the second sensing mode, the sensor driver senses an input through the sensor layer based on a second timing different from the first timing.

Abstract: An embodiment is a semiconductor device including a first channel region over a semiconductor substrate, a second channel region over the first channel region, a first gate stack over the semiconductor substrate and surrounding the first channel region and the second channel region, a first inner spacer extending from the first channel region to the second channel region and along a sidewall of the first gate stack, a second inner spacer extending from the first channel region to the second channel region and along a sidewall of the first inner spacer, the second inner spacer having a different material composition than the first inner spacer, and a first source/drain region adjacent the first channel region, the second channel region, and the second inner spacer, the first and second inner spacers being between the first gate stack and the first source/drain region.

Abstract: To achieve simplification in configuration and reduction in cost of a tactile reproduction system that reproduces tactile information. The signal generation device according to the present technology includes a signal generation unit that generates a tactile signal on the basis of a detection value of a motion detection unit that is provided in an imaging device and detects motion of the imaging device. This eliminates the need to provide a separate motion detection unit other than the motion detection unit provided in the imaging device in order to realize a system that reproduces tactile information together with visual information.

Abstract: A semiconductor structure and a forming method thereof are provided.

Abstract: A vibrator, a manufacturing method thereof, a haptical sensation reproduction apparatus and a vibration waveform detection method, and relates to the technical field of display. The vibrator comprises a substrate, and a piezoelectric component and a light-emitting component located on the substrate, wherein the piezoelectric component comprises an inverse piezoelectric unit, the light-emitting component comprises a direct piezoelectric unit and a light-emitting unit, and the inverse piezoelectric unit is in contact and connected with the direct piezoelectric unit. The vibrator of this solution may be disposed in a touch-control reproduction screen, the inverse piezoelectric unit in the vibrator is driven to deform to generate vibrations, and the direct piezoelectric unit in contact and connection therewith is driven to deform to generate a current to drive the light-emitting unit to emit light.

Abstract: For a display device having a plurality of subpixels disposed in an active area of a display panel, a method for processing a compensation data of the display device may include reconfiguring an order of unit patches having the compensation data so that the unit patches having similar reference values are positioned adjacent to each other when the compensation data are compressed. The disclosed method can improve the compression process efficiency where a compression loss can be reduced, and an effect of an image quality improvement using the compensation data can be enhanced.

Abstract: A substrate treatment device is provided, including a substrate holding unit holding a substrate and rotating the substrate; plural nozzles each having a discharge port and discharging a treatment liquid from the discharge port at a treatment position; a camera imaging an imaging region from an imaging position to acquire captured images, the imaging region containing the treatment liquid discharged from the discharge port of each nozzle positioned at the treatment position, and the imaging position being above the substrate held on the substrate holding unit and in a plan view, the imaging position being positioned at a central side of the substrate with respect to the nozzles and at an upstream side in a rotation direction of the substrate holding unit with respect to the nozzles; and an image processing unit determining a discharge state of the treatment liquid based on the captured images.

Abstract: Semiconductor devices having recessed edges with plated structures, semiconductor assemblies formed therefrom, and associated systems and methods are disclosed herein. In one embodiment, a semiconductor assembly includes a first semiconductor device and a second semiconductor device. The first semiconductor device can include an upper surface and a first dielectric layer over the upper surface, the second semiconductor device can include a lower surface and a second dielectric layer over the lower surface, and the first and second dielectric layers can be bonded to couple the first and second semiconductor devices. The first and second dielectric layers can each include a plurality of inwardly extending recesses exposing a plurality of metal structures on the respective upper and lower surfaces, and the upper surface recesses and metal structures can correspond to the lower surface recesses and metal structures. The metal structures can be electrically coupled by plated structures positioned in the recesses.

Abstract: A semiconductor structure and the manufacturing method thereof are disclosed. An exemplary semiconductor structure includes a first source/drain contact and a second source/drain contact spaced apart by a gate structure, an etch stop layer (ESL) over the first source/drain contact and the second source/drain contact, a conductive feature disposed in the etch stop layer and in direct contact with the first source/drain contact and the second source/drain contact, a dielectric layer over the etch stop layer, and a contact via extending through the dielectric layer and electrically connected to the conductive feature. By providing the conductive feature, a number of metal lines in an interconnect structure of the semiconductor structure may be advantageously reduced.

Abstract: A semiconductor chip includes; an intermetal dielectric (IMD) layer on a substrate, an uppermost insulation layer on the IMD layer, the uppermost insulation layer having a dielectric constant different from a dielectric constant of the IMD layer, a metal wiring in the IMD layer, the metal wiring including a via contact and a metal pattern, a metal pad in the uppermost insulation layer, the metal pad being electrically connected to the metal wiring, and a bump pad on the metal pad. An interface portion between the IMD layer and the uppermost insulation layer is disposed at a height of a portion between an upper surface and a lower surface of an uppermost metal pattern in the IMD layer.

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure including conductive layers stacked on the substrate. Moreover, the semiconductor device includes a dummy structure penetrating a stepped region of the stack structure. A portion of the dummy structure includes a first segment and a second segment. The first segment extends in a first direction in a plane parallel to an upper surface of the substrate. The second segment protrudes from the first segment in a second direction, in the plane, that intersects the first direction.

Abstract: A deep trench is formed in a substrate, and a layer stack including at least three metallic electrode plates interlaced with at least two node dielectric layers is formed in, and over, the deep trench. A contact-level dielectric material layer over the layer stack, and contact via cavities are formed therethrough. The depths of the contact via cavities are differentiated by selectively increasing the depth of a respective subset of the contact via cavities by performing at least twice a combination of processing steps that includes an etch mask formation process and an etch process. A combination of a dielectric contact via liner and a plate contact via structure can be formed within each of the contact via cavities. Plate contact via structures that extend through any metallic electrode plate can be electrically isolated from such a metallic electrode plate by a respective dielectric contact via liner.

Abstract: A display device includes a display panel including a plurality of pixels, an image data corrector configured to generate a corrected image data by adjusting an image data and a data driver providing data signals to the plurality of pixels based on the corrected image data. The image data corrector divides the display panel into a plurality of unit areas, and adjust the image data for a unit area among the plurality of unit areas by using a full image load for the entire display panel, a first image load for the unit area, and a second image load for peripheral unit areas surrounding the unit area among the plurality of unit areas.

Abstract: The present disclosure provides an interconnect structure and a method for forming an interconnect structure. The method for forming an interconnect structure includes forming a first interlayer dielectric (ILD) layer over a substrate, forming a contact in the first ILD layer, forming a second ILD layer over the first ILD layer, forming a first opening in the second ILD layer and obtaining an exposed side surface of the second ILD layer over the contact, forming a densified dielectric layer at the exposed side surface of the second ILD layer, including oxidizing the exposed side surface of the second ILD layer by irradiating a microwave on the second ILD layer, and forming a via in contact with the densified dielectric layer.

Abstract: The present disclosure describes a method for forming a barrier structure between liner-free conductive structures and underlying conductive structures. The method includes forming openings in a dielectric layer disposed on a contact layer, where the openings expose conductive structures in the contact layer. A first metal layer is deposited in the openings and is grown thicker on top surfaces of the conductive structures and thinner on sidewall surfaces of the openings. The method further includes exposing the first metal layer to ammonia to form a bilayer with the first metal layer and a nitride of the first metal layer, and subsequently exposing the nitride to an oxygen plasma to convert a portion of the nitride of the first metal layer to an oxide layer. The method also includes removing the oxide layer and forming a semiconductor-containing layer on the nitride of the first metal layer.

Abstract: Scalable device designs for FINFET technology are provided. In one aspect, a method of forming a FINFET device includes: patterning fins in a substrate which include a first fin(s) corresponding to a first FINFET device and a second fin(s) corresponding to a second FINFET device; depositing a conformal gate dielectric over the fins; depositing a conformal sacrificial layer over the gate dielectric; depositing a sacrificial gate material over the sacrificial layer; replacing the sacrificial layer with a first workfunction-setting metal(s) over the first fin(s) and a second workfunction-setting metal(s) over the second fin(s); removing the sacrificial gate material; forming dielectric gates over the first workfunction-setting metal(s), the second workfunction-setting metal(s) and the gate dielectric forming gate stacks; and forming source and drains in the fins between the gate stacks, wherein the source and drains are separated from the gate stacks by inner spacers. A FINFET device is also provided.

Abstract: A wireless input output apparatus is disclosed. The wireless input output apparatus includes a first housing mechanically coupled to the wireless input output apparatus panel. The first housing is configured to house a plurality of input keys. Each of the plurality of input keys corresponds to one of a character, a letter, a number, a function, and a command. The wireless input output apparatus also includes a second housing mechanically coupled adjacent to the first housing and over the wireless input output apparatus panel. The second housing is configured to house a capacitive touch screen display for rendering visual information. The wireless input output apparatus may be tethered to computer, phone, laptop, tablet, and the like without interrupting workflow when receiving calls, texts, “DMs”, emails and the like.

Abstract: A method for producing a plurality of chips each comprising an individualisation region, each chip comprising at least: a first and a second level of the electrical tracks, and an interconnections level comprising vias. The method includes producing on the dielectric layer covering the first level a mask having openings located in line with the electrical tracks and making the dielectric layer accessible. The method includes producing, in a region of the chip comprising the individualisation region, patterns conformed so that: first openings of the hard mask are not masked by the patterns, and second openings of the hard mask are masked by the patterns. The method includes producing via openings in the dielectric layer in line solely with the first openings. The method further includes filling in the via openings with an electrically conductive material, and producing the second level of the electrical tracks on the vias.

Abstract: An interconnection element of an interconnection structure of an integrated circuit is manufactures by a method where a cavity is etched in an insulating layer. A silicon nitride layer is then deposited on walls and a bottom of the cavity. The nitrogen atom concentration in the silicon nitride layer increasing as a distance from an exposed surface of the silicon nitride layer increases. A copper layer is deposited on the silicon nitride layer. The cavity is further filled with copper. A heating process is performed after the deposition of the copper layer, to convert the copper layer and the silicon nitride layer to form a copper silicide layer which has a nitrogen atom concentration gradient corresponding to the gradient of the silicon nitride layer.