Patents Examined by A. M. Thompson
  • Patent number: 10272744
    Abstract: A vehicle includes a heating, ventilation and air conditioning (HVAC) system for heating and cooling a passenger compartment. The HVAC system includes a refrigerant loop operable in a cooling mode and a heating mode, and an auxiliary coolant loop for heating and cooling at least a portion of the passenger compartment. The auxiliary coolant loop includes a pump for moving a coolant, within the auxiliary coolant loop, through a first heat exchanger coupled to the refrigerant loop via an expansion device in the cooling mode, a second heat exchanger positioned within the passenger compartment, and a third heat exchanger coupled to the refrigerant loop, and a flow control valve. The temperature of the coolant within the auxiliary coolant loop is controlled utilizing the flow control valve and the pump. The first and third heat exchangers may be in parallel for controlling the movement of coolant therebetween to control temperature.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: April 30, 2019
    Assignee: Ford Global Technologies, LLC
    Inventors: Robert Steven Sawyer, Manfred Koberstein
  • Patent number: 9477799
    Abstract: A method of determining a metric of a System-on-Chip (SoC), the method comprising: receiving a model dependency graph representing the SoC, the model dependency graph having a plurality of nodes representing components of the SoC and their models, and a plurality of directed edges between the nodes representing variables passed between the nodes of the model dependency graph; modifying the model dependency graph by clustering a plurality of strongly connected nodes in the model dependency graph into a single clustered node to form a clustered model dependency graph; determining an execution schedule according to a direction of an edge in the clustered model dependency graph; and executing models in the clustered model dependency graph according to the execution schedule to determine metrics of the SoC.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: October 25, 2016
    Inventors: Yusuke Yachide, Haris Javaid, Sridevan Parameswaran
  • Patent number: 9465897
    Abstract: Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: October 11, 2016
    Assignee: SYNOPSYS, INC.
    Inventors: Victor Moroz, Dipankar Pramanik
  • Patent number: 9448470
    Abstract: A method for making a mask includes receiving an integrated circuit (IC) design layout and identifying at least one targeted-feature-surrounding-location (TFSL) in the IC design layout, wherein TFSL is identified by a model-based approach. The method further includes inserting at least one phase bar (PB) in the IC design layout and performing an optical proximity correction (OPC) to the IC design layout having the at least one PB to form a modified IC design layout. A mask is then fabricated based on the modified IC design layout.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: September 20, 2016
    Inventors: Ru-Gun Liu, Shou-Yen Chou, Hoi-Tou Ng, Ken-Hsien Hsieh, Yi-Yin Chen
  • Patent number: 9451723
    Abstract: In some embodiments, a cooling system for an inductive charger includes a thermal conditioning assembly in fluid communication with an inductive charging assembly. The inductive charging assembly can include a dock and an inductive charging module. The dock can be configured to receive a portable electronic device, such as a cell phone, that is configured to accept inductive charging from the inductive charging module. The thermal conditioning assembly can include a fluid transfer device and a thermal conditioning module, such as a thermoelectric device. In various embodiments, heat (e.g., heat produced during inductive charging) can be transferred from the inductive charging assembly to the thermal conditioning module and/or to a fluid flow produced by the fluid transfer device, thereby cooling the inductive charging assembly and/or the portable electronic device.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: September 20, 2016
    Assignee: Gentherm Incorporated
    Inventors: John Lofy, David Marquette
  • Patent number: 9449132
    Abstract: A method of preparing a programmable integrated circuit device for configuration using a high-level language includes compiling a plurality of virtual programmable devices from descriptions in said high-level language. the compiling includes compiling configurations of configurable routing resources from programmable resources of said programmable integrated circuit device, and compiling configurations of a plurality of complex function blocks from programmable resources of said programmable integrated circuit device. A machine-readable data storage medium may be encoded with a library of such compiled configurations. A virtual programmable device may include a stall signal network and routing switches of the virtual programmable device may include stall signal inputs and outputs.
    Type: Grant
    Filed: January 6, 2015
    Date of Patent: September 20, 2016
    Assignee: Altera Corporation
    Inventors: Doris Tzu-Lang Chen, Deshanand Singh
  • Patent number: 9444276
    Abstract: A mobile terminal capable of being charged in a wired or wireless manner is disclosed. Some embodiments of the disclosed mobile terminal include a terminal body having a battery, a contact unit formed at one side of the terminal body and coupled to an adaptor, and a plurality of conductive lines configured to connect the contact unit with the battery, where a first conductive line passes through a first charging unit configured to charge the battery with power received wirelessly from a wireless power transmitter, where a second conductive line passes through the second charging unit, and the first conductive line and the second conductive line diverge at a first point and converge at a second point between the contact unit and the battery.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: September 13, 2016
    Inventors: Byoungyong Hong, Kyungsoon Park, Mansoo Sin, Jeewoo Lee
  • Patent number: 9443050
    Abstract: Electronic design automation (EDA) technologies are disclosed that analyze a circuit design for candidate low-voltage swing (LVS) modifications, report the impact of the candidate LVS modifications on circuit characteristics (such as area, timing and energy) and implement selected LVS modifications based on their impact on the circuit characteristics. Candidate LVS modifications comprise replacing existing standard low-voltage swing drivers and receivers, or inserting low-voltage swing drivers and receivers.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: September 13, 2016
    Assignee: Oregon State University
    Inventors: Jacob Postman, Patrick Yin Chiang
  • Patent number: 9436787
    Abstract: The present disclosure provides a method that includes receiving an IC design layout having main features and generating a plurality of space block layers to the IC design layout. The method also includes calculating main pattern density PD0 and dummy pattern density PDs of the IC design layout and calculating a least variation block dummy density ratio (LVBDDR) of the IC design layout for each of the space block layers according to the main pattern density and the dummy pattern density. The method further includes choosing an optimized space block layer and an optimized block dummy density ratio according to the LVBDDR and generating a modified IC design layout from the IC design layout according to the optimized space block layer and the optimized block dummy density ratio. Additionally, the method includes forming a tape-out data of the modified IC design layout for IC fabrication.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: September 6, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jyuh-Fuh Lin, Pei-Yi Liu, Cheng-Hung Chen, Wen-Chuan Wang, Shy-Jay Lin, Burn Jeng Lin
  • Patent number: 9424372
    Abstract: A system and method for mask data preparation (MDP) uses pixel processing algorithms running on parallel processing platforms such as central processing units (CPUs) and graphical processing units (GPUs). Proximity effects correlation, dose, and bias corrections are performed on a pixel basis. In some embodiments, striping of a decorated database in parallel using multiple graphic processors is performed. While performing a first light path simulation for a first stripe for a mask, a second light path simulation is performed for a second stripe for the mask. Using a result of the striping and first and second light path simulations, dose adjustment during a mask processing on a pixel of the mask is performed.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: August 23, 2016
    Assignee: D2S, Inc.
    Inventors: Ilhami H. Torunoglu, Ahmet Karakas
  • Patent number: 9418905
    Abstract: An adaptive patterning method and system for fabricating panel based package structures is described. Misalignment for individual device units in a panel or reticulated wafer may be adjusted for by measuring the position of each individual device unit and forming a unit-specific pattern over each of the respective device units.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: August 16, 2016
    Assignee: DECA Technologies Inc.
    Inventors: Timothy L. Olson, Christopher M. Scanlan
  • Patent number: 9418191
    Abstract: A method for writing a design to a material using an electron beam includes assigning a first dosage to a first polygonal shape. The first polygonal shape occupies a first virtual layer and includes a first set of pixels. The method also includes simulating a first write operation using the first polygonal shape to create the design, discerning an error in the simulated first write operation, and assigning a second dosage to a second polygonal shape to reduce the error. The second polygonal shape occupies a second virtual layer. The method further includes creating a data structure that includes the first and second polygonal shapes and saving the data structure to a non-transitory computer-readable medium.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: August 16, 2016
    Inventors: Hung-Chun Wang, Jeng-Horng Chen, Shy-Jay Lin, Chia-Ping Chiang, Cheng Kun Tsai, Wen-Chun Huang, Ru-Gun Liu
  • Patent number: 9407099
    Abstract: In a two-way direct balance circuit for series cells, a control unit activates a pulse generator to transmit high frequency switch control signals, and a flyback converter is utilized to perform electromagnetic transition between the cells that rapidly conveys power from the cells with high relative state of capacity (RSOC) to the flyback converter and to the cells with low RSOC. The direct energy transfer between cells provides fast and highly efficient performance.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: August 2, 2016
    Assignee: Simplo Technology Co., Ltd.
    Inventors: Ya-Mei Chang, Cherng-Huei Liang
  • Patent number: 9384309
    Abstract: Some embodiments of the present invention provide techniques and systems for determining and using margin values. An arrival time at an output pin of a logic gate can be determined. Next, required times at the output pin of the logic gate can be determined. Each required time can be associated with a timing end-point in a path-group, affected by that pin. The system can then determine a first set of slack values at the output pin of the logic gate by computing a difference between the required times and the arrival time. Next, the system can determine a set of margin values at the output pin of the logic gate by computing a difference between the first set of slack values and a second set of slack values at the timing end-points in the path-groups. Next, the system can use the set of margin values to optimize the logic gate.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: July 5, 2016
    Assignee: SYNOPSYS, INC.
    Inventors: Mahesh A. Iyer, Amir H. Mottaez, Rajnish K. Prasad
  • Patent number: 9372949
    Abstract: A model checking tool, which is used to test a circuit design, attempts to reach a target state from an initial state in the state-space of the circuit design using one or more intermediate states. Through an iterative process, the tool identifies intermediate states in the state-space of the circuit design that are used to generate starting states for subsequent iterations of the process. The intermediate states help to restrict the scope of the state-space search to reduce the time and memory requirements needed to reach the target state. The model checking tool also explores the state-space in parallel from a subset of computed restart states, which reduces the possibility of bypassing any essential intermediate or target states.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: June 21, 2016
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ziyad Hanna, Craig Franklin Deaton, Kathryn Drews Kranen, Björn Håkan Hjort, Lars Lundgren
  • Patent number: 9355206
    Abstract: A new approach is proposed that contemplates a system and method to support automated functional coverage generation and management for an IC design protocol. The proposed approach takes advantage of table-based high-level (e.g., transaction-level) specifications of the IC design protocol, wherein the state tables are readable and easily manageable (e.g., in ASCII format) in order to automatically generate functional coverage for the IC design protocol, which include but are not limited to, coverage points, protocol transitions, and/or transaction coverage. The automatically generated functional coverage is then verified via formal verification and simulated at the register-transfer level (RTL) during the coverage generation and management process. The coverage data from the formal verification and the simulation runs are then analyzed and used to guide and revise the IC design protocol in a coverage-based closed-loop IC design process.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: May 31, 2016
    Assignee: CAVIUM, INC.
    Inventors: Shahid Ikram, Isam Akkawi, John Perveiler, David Asher, James Ellis
  • Patent number: 9340118
    Abstract: When detecting an abnormality, an in-vehicle wireless instrument in a plug-in vehicle sends an abnormality occurrence notification to a mobile terminal via an information center. The mobile terminal performs a notification to notify a user of the abnormality having occurred in the plug-in vehicle. When the user performs a charging forbiddance manipulation based on the notification, the mobile terminal sends a charging forbidding command to a power management ECU in the vehicle via the information center and the in-vehicle wireless instrument. When receiving the charging forbidding command, the power management ECU stops charging a battery using an external power source, and sends a setting completion notification to the mobile terminal via the in-vehicle wireless instrument and the information center. When receiving the setting completion notification, the mobile terminal notifies the user that the charging is stopped.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: May 17, 2016
    Inventor: Kazuhiko Endo
  • Patent number: 9330216
    Abstract: An updated integrated circuit (IC) design is generated by applying a histogram-based algorithm to an invalid, current IC design. The histogram-based algorithm includes worst negative slack (WNS) optimization followed by total negative slack (TNS) optimization. WNS optimization uses the slack histogram for the current IC design to generate an invalid, but improved, intermediate IC design. TNS optimization uses the slack histogram of the intermediate IC design to generate the updated IC design.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: May 3, 2016
    Inventors: Mohit Parnami, Sorabh Sachdeva
  • Patent number: 9317641
    Abstract: A processing device can identify gates of an integrated circuit design having a slack value less than a predefined slack threshold. The processing device can further, for each of the identified gates, determine (i) a number of nodes of the integrated circuit design that experience a timing slack improvement if the gate is swapped with an alternative implementation having a reduced delay or (ii) a sum of timing slack improvements experienced by nodes of the integrated circuit design if the gate is swapped with the alternative implementation having a reduced delay. The processing device can still further swap the gate with the alternative implementation having the reduced delay if the determined number or sum is greater than a corresponding predetermined threshold.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: April 19, 2016
    Assignee: Oracle International Corporation
    Inventors: Salim U. Chowdhury, Georgios Konstadinidis
  • Patent number: 9298871
    Abstract: Disclosed is a method and system for translating parameterized cells (pcells) that are created using different programming languages. The pcell source code created in a first programming language undergoes a translation process to translate that source code to a second programming language. A validation process is also provided to ensure the correctness of the translations.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: March 29, 2016
    Assignee: Cadence Design Systems, Inc.
    Inventor: Elias L. Fallon