Abstract: A data processing apparatus includes two data transmission paths formed likewise in a loop fashion. These data transmission paths include a plurality of latch registers connected in a cascade fashion respectively and are constituted as a so-called self-running type shift register wherein each data word constituting a data packet is shifted in sequence provided that a pre-stage register is vacant. Data packets are transmitted in the directions reverse to each other on the two loop-shaped data transmission paths an identification data included in each data packet being transmitted is detected in a section defined as a data packet pair detecting section. The detected identification data are compared in a comparing circuit and, one new data packet is produced from the two data packets in a manner that a data packet is joined from one data transmission path to the other data transmission path.

Abstract: A method for the recovery of proteins which method includes providing a source of protein in an insoluble form, a source of at least one cationic surfactant; treating the insoluble protein with the at least one cationic surfactant in an amount sufficient to effect solubilization without substantial modification to the structural backbone of the protein.

Abstract: A new sulfur-containing polypeptide antibiotic produced by the hydrolysis of thiosporamicin (CP-46,192) is useful for the improving feed utilization efficiency in poultry and swine.

Abstract: A virtual memory system is used to control access to I/O device address space in accordance with a preferred embodiment of the present invention. In a virtual memory system, access to pages within a processor's address space are assigned to each application program. Each I/O device is assigned two pages of address space. One page is considered to be privileged, and the other unprivileged. Each I/O device register is associated with an address in each of the two pages of its I/O device address space. Address space is global. What is meant by global is that physical memory locations map to the same virtual memory space regardless of what process is running on the processor. Access codes accompanied by a write disable bit are used to control process access to various addresses.

Abstract: A data processing system is provided which includes ALU data busses, temporary operand storage registers, an accumulator, and a set of latches for temporarily storing data to be supplied to the input of the ALU. Output multiplexer is provided which can select the output of one of the latches or that of the ALU which is sent to the accumulator. A detector is also provided for determining whether the smaller or larger one of two data elements is stored in said latches according to the status of the ALU and a new MIN/MAX instruction and the selected data element is returned to a predetermined temporary storage register via the output multiplexer. A controller operates in cooperation with the system instruction decoder to effect this operation with a single machine instruction.

Abstract: A memory access control system for an information processing apparatus having a buffer memory and a main memory wherein when a store or access request is generated, in the case where the data block in the address to be accessed does not exist in the buffer memory, the store requested data from a data register is written into the buffer memory before the first data in the data block read out from the main memory is written into the buffer memory, and the data register is released to receive the next request.

Abstract: A format-changing data processing system is capable of storing successive input records (data words) in a random access memory and of retrieving the data words from the memory in accordance with predetermined instructions to produce the data words at the output of the system in a sequence having a changed sequential format as compared with the sequence of the input words. In a preferred embodiment of the system the instructions are stored in a second memory, and the data words flow into and out of the system simultaneously, and into and out of first and third memories, with the output words having a sequential format which is different from the sequence of input words, as established by the instructions in the second memory.

Abstract: A circuit arrangement for synchronizing source data from a source system with a clock and/or clocks from a sink system. The circuit arrangement includes a source counter, a buffer, a sink counter and a controller. The source data is placed in consecutive buffer positions under the control of the source counter. The sink counter is made to "follow" the source counter and identifies the location in the buffer whereat output data is to be extracted. The controller monitors the counters and generates control signals representative of the state of the buffer.

Abstract: A simulation security device for a data entry keyboard of a computer is operative with an input-output unit and a keyboard of the computer. The device includes plural memories and a switching assembly which are operatively coupled to row and column signals generated by the keyboard. One memory stores coded call instructions of a working program, and a second memory stores call instructions of the working program and addresses of these instructions, there being an address counter associated with the second memory. The memories are connected via the input-output unit and the switching assembly for responding to row and column signals of the keyboard to permit the transmission of call instructions to the computer so as to prevent any transmission of coded instructions of the keyboard during an initialization and a transmission of call instructions.

Abstract: A data processing system has a plurality of peripheral devices and a main memory, a direct memory access controller for controlling the transfer of data between the main memory and the peripheral devices including a local memory connected to the peripheral devices for storing data written to and read from the peripheral devices, a sequencer for controlling the transfer of data between the main memory and the local memory, a local address register connected to the sequencer for providing the local memory address for memory operations of the local memory, a system address register connected to the sequencer for providing the main memory address for memory operations of the main memory, and a data register for holding data transferred between the main memory and the local memory.