Abstract: A duplex memory control apparatus having a first control unit containing a first memory and a second control unit containing second memory, a first control unit and a second control unit connected to each other through a bus.

Abstract: A device for ATM cell switching having failure tolerance. The device is divided into two types of equipment modules. The first type includes connecting modules while the second type includes two branching and managing modules, one operating in an active mode while the other operates in a passive mode. An accessing device is implanted in each connector. Devices to execute the ATM layer function are almost identically implanted in each connector and in each of the two branching and managing modules. A supervision bus connects both types of modules to ensure quick and automatic reconfiguration of the device in case of failure in one of its components. The supervising bus is of simple configuration and only serves to carry, under the control of the managing module, signals indicative of the master and slave managing means as well as a signal indicative of the active branching module.

Abstract: To provide all ATM exchange wherein more supple collective routing than VP routing is enabled without waste of VPI/VCI resources, an ATM exchange comprises: a VPI/VCI converter (1) for retrieving a logic value, which is predetermined for each of individual connections to be dealt with individually and groups of connections to be dealt with collectively, according to an input VPI/VCI value; a mask-bit generator (2) for generating a mask-bit pattern, a number of lower bits of the mask-bit pattern having logic ‘1’ and other upper bits thereof having logic ‘0’ when the mask-bit pattern concerns one of the groups of connections; and a VPI/VCI bit selector (3) for generating an output VPI/VCI value to be written in the VPI/VCI field of the cell, by selecting logic of each bit of the output VPI/VCI value to have the same logic with a corresponding bit of the logic value outputted from the VPI/VCI converter (1) when a corresponding bit of the mask-bit pattern has logic ‘0’, and to

Abstract: Transmission power in a frequency-hopping radio system that transmits packets from a sending radio unit to a receiving radio unit, wherein each packet includes an address designating the receiving radio unit, is controlled by measuring received signal strength of packets whose addresses were successfully received in the receiving radio unit, regardless of whether other portions of the respective packets were successfully received. An average signal strength value is generated from the received signal strength measurements. The mathematical difference between the average signal strength value and a target value associated with the receiving radio unit is then determined and used as a basis for deciding whether to send a power control message from the receiving radio unit to the sending radio unit.

Abstract: A transmission path interface apparatus compatible with a CSMA mode capable of responding to a fault occurring in a transmission path flexibly and at a high speed, including a transmission unit for holding serial transmission information and transmitting a frame modulated by both of the transmission information and a preamble to a CSMA mode transmission path; a reception unit for taking out a loopback frame transmitted by an opposing node in accordance with that frame, restoring the transmission information contained in this, and holding the same; a collision decision unit for determining a correlation between transmission information held by the transmission unit and the reception unit and notifying a result of this to an information source of transmission information; and a collision decision acceleration unit for comparing an elapsed time from a timing when the information source gave the transmission information to the transmission unit to a timing when the transmission information contained in the loopba

Abstract: A communications system, which can be used within a conferencing communication system, is provided. The communications system includes at least one communications network, a plurality of communicators connectable to the at least one communications network, each of the communicators being operative to transmit, via the network, audio streams bound from any of the plurality of communicators, a plurality of mixers. Each of the mixer output associated with one of the communicators is operative to receive from the plurality of communicators a plurality of incoming streams bound from the communicators to the mixer and transmit any mixed combination of the incoming streams to the communicator associated with the mixer. The system also includes means for controlling any of the mixers to independently control a volume level of any of the incoming streams being mixed at any of the mixers to create the required mixed combination of the incoming streams.

Abstract: An inband signaling modem communicates digital data over a voice channel of a wireless telecommunications network. An input receives digital data. An encoder converts the digital data into audio tones that synthesize frequency characteristics of human speech. The digital data is also encoded to prevent voice encoding circuitry in the telecommunications network from corrupting the synthesized audio tones representing the digital data. An output then outputs the synthesized audio tones to a voice channel of a digital wireless telecommunications network.

Abstract: Systems and methods are described for multi-link segmentation and reassembly for bonging multiple virtual circuits in an inverse multiplexing arrangement. A method includes: generating a plurality of multilink segmentation and reassembly sublayer cells at a first location; distributing the plurality of multilink segmentation and reassembly sublayer cells across a plurality of virtual circuits; transmitting the plurality of multilink segmentation and reassembly sublayer cells to a second location via the plurality of virtual circuits; and receiving the plurality of multilink segmentation and reassembly sublayer cells at the second location. An apparatus includes a multilink segmentation and reassembly sublayer transmitter, including: a source buffer; a multilink controller coupled to the source buffer; and a plurality of virtual circuits coupled to the multilink controller.

Abstract: This invention discloses an improved address table apparatus that includes an address bus for receiving input data packets and for hashing a designated bucket number and extracting a key from each of the data packets. The address table apparatus further includes a plurality of memory banks connected to the address bus wherein each memory bank includes a plurality of memory buckets for storing a designation address (DA) and a port number in each of the buckets. The address table apparatus further includes a comparand bus connected to the address bus for receiving the key therefrom. The address table apparatus further includes a plurality of comparators each corresponding to one of the memory banks for receiving the designation address (DA) and the port number from the designated bucket from a corresponding memory bank. The comparators further connected to the comparand bus for receiving and comparing the key to the address from the designated bucket in each of the memory banks.

Abstract: A communication system using GPS-based time for synchronizing communication data packets and symbols. The communication system includes a transmit apparatus for transmitting and a receive apparatus for receiving a communication data signal. The transmit apparatus includes a transmit station GPS receiver for providing GPS-based time, a transmit framer for using the GPS-based time for framing packets of communication data symbols, and a transmit symbol timer for synchronizing the communication data symbols to the GPS-based time. The receive apparatus includes a GPS receiver for providing the GPS-based time, a receive framer for using the GPS-based time for receiving the packets of the communication data signal, and a receive symbol timer for synchronizing the reception of the communication data symbols to the GPS-based time.

Abstract: A node in a packet network such as an ATM network receives a plurality of traffic classes and outputs them to an output link. The invention relates to a technique of scheduling the traffic classes in a time linked fashion at the node based on the bandwidth allocated to each traffic class. Traffic scheduling based strictly on priority may not satisfy delay and loss guarantees of traffic classes when there are many classes with many different priority levels. The rate based scheduling in a time-linked fashion solves these problems by limiting the bandwidth to which each class is accessible. According to one embodiment, the invention uses timeslot values and a linked list of the traffic classes.

Abstract: In coded representation of audio, video and system bitstreams, it is common to insert start codes to facilitate synchronization points. The start codes are usually unique patterns that cannot be duplicated within the bitstream. In the decoding process it is necessary to detect these start codes in order to begin the decoding of the bitstream in a synchronized way. In typical cases, it is normal for the start code to be byte aligned and have the first few bytes comprising of the same pattern. The present invention is a method and apparatus that exploit this feature to reduce the number of comparisons required. A specific order is used in comparing the input bitstream to the start code pattern. Using this order the decoder only need to compare a subset of the bytes during the start code detection process.

Abstract: In a synchronous code division multiple access (SCDMA) time division duplex (TDD) communication system, a remote terminal uses both open loop and closed loop techniques for synchronization with a base station. The timing of reception of information by tile remote terminal is performed with an open loop technique, while the timing of transmissions from the terminal is performed with a closed loop technique. Furthermore, a clock locked loop in the terminal compensates for differences between clocks of the terminal and the base station. The clock locked loop responds to signals from both the aforesaid open loop and closed loop techniques.

Abstract: A PHS data communication terminal adapter which can perform data communication with a data communication terminal on the side of a PHS (Personal Handy-phone System) via a digital network by executing protocol conversion and switching the data transmission bit rate between a high data transmission bit rate (64 kbps) and a low data transmission bit rate(32 kbps) is provided, without needing large signal processing scale and device scale of the PHS data communication terminal adapter, and without deteriorating data communication efficiency. In the PHS data communication terminal adapter, B-channel transmission data composed of 8 bits which have been sent from the data communication terminal on the side of the PHS is received by an S reference point interface section, and the rear 4 bits of the 8-bit B-channel transmission data are separated by a rear part separation section, and the number of “1”s in the rear 4 bits is counted by a rear part counter section.

Abstract: A looping detection apparatus used in a frame-relay communications system and capable of detecting looping without fail through confirmation of link completeness according to a two-way PVC status confirmation procedure. A status enquiry message transmitting unit transmits a status enquiry message with a first identification code carried at a predetermined position of a signal by means of which the status enquiry message is transmitted. On receiving the status enquiry message, a status response message returning unit creates a status response message based on the status enquiry message and sends the status response message back to a first node with a second identification code carried at the predetermined position.

Abstract: The invention relates to a circuit architecture for processing multi-channel frames of broadband synchronous digital signals, in particular signals of the SONET/SDH standard. The circuit includes an input portion and an output portion. It also contains at least one modular component adapted to process frames comprising a single channel and connectable modularly to N further identical components corresponding to the number of frame channels.

Abstract: A method and apparatus for discovering, identifying and graphically representing network devices on a network. The devices are discovered by obtaining the gateway address of the management workstations and then reading the internet protocol address table and the ARP cache from each gateway via SNMP. Each address read is compared with existing IP addresses, and if new, device IDs are created and assigned. Select attributes are then assigned to each device and then the devices are then identified. The devices are identified by making a DNS request on the corresponding IP address to determine the network name of the device. The SNMP then obtains the system name and object ID (OID) for each of the devices. The OID is then compared and matched with known OIDs to identify the device. the devices are graphically connected and laid out by creating a submap based on the IP address and mask pairs for each device. The routers connected, the bridges are then connected and finally the repeaters are connected.

Abstract: The present invention relates to a method for co-ordination of uplink scrambling codes between different radio network controllers (21) and the assignment of such codes to radio connections (27) of user equipments (26) in a code division multiple access (CDMA) communication system. The invention also relates to methods for creating a starting vector used to generate said scrambling codes. According to the invention, a unique subset of scrambling codes is dedicated to each radio network controller (21) by assigning an offset vector (212). Initial starting vectors (215) are composed by concatenating the offset vector (212) and the binary representation of a determining value (216) within the size range of the dedicated code subset. An idle starting vector is selected, e.g., by using a one-dimensional array (217) containing a status bit for each scrambling code and by using the array index (213) as determining value (216).

Abstract: A method for processing a service and protocol without changing a protocol even though a mobile network service type is changed while a mobile network system implements a service using an International Telecommunication Union-Telecommunication Standardization Section Transaction Capabilities Application Part (ITU-T TCAP) or an American National Standards Institute Transaction Capabilities Application Part (ANSI TCAP).

Abstract: A method and apparatus for utilizing an Internet web server to direct the processing of operator assistance type calls. A Telephony web browser is connected to a switch to receive customer signals over a voice channel and switch signals over a data channel. Responsive to receipt of inputs over the voice and data channels, the telephony web browser generates a request comprising a uniform resource locator (URL) segment which is transmitted to a web server. The web server responds with a Hypertext Markup Language (HTML) page which the telephony web browser converts into a request to the switch to establish the call connection. The telephony web browser can also control visual display to an operator work station for calls wherein the work station controls the call.