Abstract: A wafer processing method for carrying out processing by applying a laser beam along streets formed on a wafer, comprising a step of applying a laser beam at an incident angle of a predetermined inclination angle to the normal line of a processing surface of the wafer while the wafer is processing-fed along a street from one end to the other end on the side of the laser beam application at an acute angle to the processing surface of the wafer.

Abstract: Ball grid array packages for semiconductor die include a thermally conductive container and a substrate that substantially enclose a semiconductor die. The die is positioned with respect to the container by thermally conductive supports formed in the container or attached to the container. The die contacts the supports so that the die and the container form a cavity that is at least partially filled with a thermally conductive material such as a conductive epoxy to promote thermal conduction between the die and the container. The die electrically connects to the substrate with bond wires that extend through an aperture in the substrate and attach to bond pads provided on the substrate. The aperture is typically filled with a protective layer of resin, epoxy, or other material that also encapsulates the bond wires.

Abstract: A technique is provided that allows the formation of contact etch stop layers having different intrinsic stress for different transistors, while substantially avoiding any device degradation owing to the partial removal of the contact etch stop layer. Hereby, an additional thin etch stop layer is provided prior to the formation of the contact etch stop layers, thereby substantially maintaining the integrity of metal silicide regions, when a portion of an initially deposited contact etch stop layer is removed.

Abstract: A high-resistance silicon wafer is manufactured in which a gettering ability, mechanical strength, and economical efficiency are excellent and an oxygen thermal donor is effectively prevented from being generated in a heat treatment for forming a circuit, which is implemented on the side of a device maker. A heat treatment for forming an oxygen precipitate nucleus is performed at 500 to 900° C. for 5 hours or more in a non-oxidizing atmosphere and a heat treatment for growing an oxygen precipitate is performed at 950 to 1050° C. for 10 hours or more on a high-oxygen and carbon-doped high-resistance silicon wafer in which resistivity is 100 ?cm or more, an oxygen concentration is 14×1017 atoms/cm3 (ASTM F-121, 1979) or more and a carbon concentration is 0.5×1016 atoms/cm3 or more. By these heat treatments, a remaining oxygen concentration in the wafer is controlled to be 12×1017 atoms/cm3 (ASTM F-121, 1979) or less.

Abstract: Some embodiments provide a microdisplay integrated circuit (IC), a substantially transparent protective cover coupled to the microdisplay IC, and a base coupled to the microdisplay IC. Thermal expansion characteristics of the base may be substantially similar to thermal expansion characteristics of the protective cover. According to some embodiments, at least one set of imaging elements is fabricated on an upper surface of a semiconductor substrate, and a base is affixed to a lower surface of the semiconductor substrate to generate substantially negligible mechanical stress between the semiconductor substrate and the base.

Abstract: After forming a resist film including a hygroscopic compound, pattern exposure is performed by selectively irradiating the resist film with exposing light while supplying water onto the resist film. After the pattern exposure, the resist film is developed so as to form a resist pattern.

Abstract: The present invention relates to a two-wavelength semiconductor laser device, more particularly, to a fabrication method of a multi-wavelength semiconductor laser device. In this method, a substrate having an upper surface separated into at least first and second areas is provided. Then, a first dielectric mask on the substrate is formed to expose only the first area. Then, epitaxial layers for a first semiconductor laser are grown on the first area of the substrate. Then, a second dielectric mask on the substrate is formed to expose only the second area. Then, epitaxial layers for a second semiconductor laser are grown on the second area of the substrate.

Abstract: The present invention provides a method for manufacturing a microlens in a semiconductor substrate having a first surface and a second surface, comprising the steps of preparing the semiconductor substrate, forming a first resist layer approximately cylindrical in form on the first surface of the semiconductor substrate, reflowing the first resist layer by heat treatment while holding the semiconductor substrate in such a manner that the first surface is normal to a vertical line and placed below the second surface, thereby to deform the first resist layer into a second resist layer approximately hemispherical in form, and simultaneously etching the second resist layer and the semiconductor substrate by means of anisotropic etching to form the corresponding lens in the semiconductor substrate.

Abstract: An SOI wafer is constructed from a carrier wafer and a monocrystalline silicon layer having a thickness of less than 500 nm, an excess of interstitial silicon atoms prevailing in the entire volume of the silicon layer. The SOI wafers may be prepared by Czochralski silicon single crystal growth, the condition v/G<(v/G)crit=1.3×10?3 cm2/(K·min) being fulfilled at the crystallization front over the entire crystal cross section, with the result that an excess of interstitial silicon atoms prevails in the silicon single crystal produced; separation of at least one donor wafer from this silicon single crystal, bonding of the donor wafer to a carrier wafer, and reduction of the thickness of the donor wafer, with the result that a silicon layer having a thickness of less than 500 nm bonded to the carrier wafer remains.

Abstract: A backside method for fabricating a semiconductor component with a conductive interconnect includes the step of providing a semiconductor substrate having a circuit side, a backside, and a substrate contact on the circuit side. The method also includes the steps of forming a substrate opening from the backside to the substrate contact, and then bonding the conductive interconnect to an inner surface of the substrate contact. A system for performing the method includes the semiconductor substrate, a thinning system for thinning the semiconductor substrate, an etching system for forming the substrate opening, and a bonding system for bonding the conductive interconnect to the substrate contact. The semiconductor component can be used to form module components, underfilled components, stacked components, and image sensor semiconductor components.

Abstract: Layers of epitaxial silicon are used to protect the tunnel dielectric layer of a floating-gate memory cell from excessive oxidation or removal during the formation of shallow trench isolation (STI) regions. Following trench formation, the layers of epitaxial silicon are grown from silicon-containing layers on opposing sides of the tunnel dielectric layer, thereby permitting their thickness to be limited to approximately one-half of the thickness of the tunnel dielectric layer. The epitaxial silicon may be oxidized prior to filling the trench with a dielectric material or a dielectric fill may occur prior to oxidizing at least the epitaxial silicon covering the ends of the tunnel dielectric layer.

Abstract: A temperature sustaining flip chip process in which ILD cracking and delamination are lessened. A sequence of substrate prebake, underfill dispense, chip placement, solder reflow and underfill cure operative stages introduces lower thermal-mechanical stress during flip chip packaging.

Abstract: A method for through-plating field effect transistors with a self-assembled monolayer of an organic compound as gate dielectric includes through-plating by patterning a gate electrode material, and bringing an organic compound having dielectric properties into contact with the contact hole material and the gate electrode material. A contact hole material and the gate electrode material are at least partially uncovered. The contact hole is material not identical to the gate electrode material. A self-assembled monolayer of the organic compound is formed above the gate electrode material. The method also includes depositing and patterning the source and drain contacts without removing the self-assembled monolayer of the organic compound, and depositing a semiconductor material.

Abstract: A light emitting diode and the method of the same are provided. The light emitting diode includes a substrate, a thermal spreading layer, a connecting layer and an epitaxial structure. The substrate is selected from a transparent substrate or a non-transparent substrate, which corresponds to different materials of the connecting layers respectively. The thermal spreading layer, configured to improve the thermal conduction of the light emitting diode, is selected from diamond, impurity-doped diamond or diamond-like materials.

Abstract: Devices, such as light-emitting devices (e.g., LEDs), and methods associated with such devices are provided. A light-emitting device may include an interface through which emitted light passes therethrough. The interface having a dielectric function that varies spatially according to a pattern, wherein the pattern is arranged to provide light emission that has a substantially isotropic emission pattern and is more collimated than a Lambertian distribution of light.

Abstract: A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate. A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.

Abstract: The present invention relates to a semiconductor device that contains a trench metal-insulator-metal (MIM) capacitor and a field effect transistor (FET). The trench MIM capacitor comprises a first metallic electrode layer located over interior walls of a trench in a substrate, a dielectric layer located in the trench over the first metallic electrode layer, and a second metallic electrode layer located in the trench over the dielectric layer. The FET comprises a source region, a drain region, a channel region between the source and drain regions, and a gate electrode over the channel region. The trench MIM capacitor is connected to the FET by a metallic strap. The semiconductor device of the present invention can be fabricated by a process in which the trench MIM capacitor is formed after the FET source/drain region but before the FET source/drain metal silicide contacts, for minimizing metal contamination in the FET.

Abstract: Devices, such as light-emitting devices (e.g., LEDs), and methods associated with such devices are provided. A light-emitting device may include an interface including a first region and a second region. The first region having a dielectric function that varies spatially according to a first pattern, and the second region having a dielectric function that varies spatially according to a second pattern, wherein the second pattern is a rotation of the first pattern. A method of forming a light-emitting device is provided. The method comprises forming an interface comprising a first region and a second region. The first region having a dielectric function that varies spatially according to a first pattern, and the second region having a dielectric function that varies spatially according to a second pattern, wherein the second pattern is a rotation of the first pattern.

Abstract: A PbTiO3/SiO2-gated ISFET device comprising a PbTiO3 thin film as H+-sensing film, and a method of forming the same. The PbTiO3 thin film is formed through a sol-gel process which offers many advantages, such as, low processing temperature, easy control of the composition of the film and easy coating over a large substrate. The PbTiO3/SiO2 gated ISFET device of the present invention is highly sensitive in aqueous solution, and particularly in acidic aqueous solution. The sensitivity of the present ISFET ranges from 50 to 58 mV/pH. In addition, the disclosed ISFET has high linearity. Accordingly, the disclosed ISFET can be used to detect effluent.

Abstract: A method of providing a gate conductor on a semiconductor is provided. The method includes defining an organic polymer plating mandrel on the semiconductor, activating one or more sites of the organic polymer plating mandrel, binding a seed layer to the activated sites, and plating the dummy gate on the seed layer. The dummy gate defines a location for the gate conductor. Semiconductor devices having a dummy gate plated thereon to a width of between about 10 to about 70 nanometers are also provided.