Abstract: An encryption protocol is provided that can be implemented within a single clock cycle of an integrated circuit chip while still providing unbreakable encryption. The protocol of the present invention is so small that it can co-exist on any integrated circuit chip with other functions, including a general purpose central processing unit, general processing unit, or application specific integrated circuits with other communication related functionality.
Abstract: Systems and methods are disclosed to implement a network data interpretation pipeline to recognize machine operations (MOs) and machine activities (MAs) from network traffic data observed in a monitored network. In embodiments, a MO recognition engine is implemented in the network to recognize MOs from network sensor events (NSEs) based on defined recognition patterns. The MOs and any unrecognized NSEs are uploaded to a network monitoring system, where they are further analyzed by a MA recognition engine to recognize higher-level machine activities performed by machines. The NSEs, MOs, and MAs are used by the network monitoring system to implement a variety of security threat detection processes. Advantageously, the pipeline may be used to add rich contextual information about the raw network data to facilitate security threat detection processes.
Abstract: An optical isolation material may be applied to walls of a first cavity and a second cavity in a wafer mesh. A wavelength converting layer may be deposited into the first cavity to create a first segment and into the second cavity to create a second segment. The first segment may be attached to a first light emitting device to create a first pixel and the second segment to a second light emitting device to create a second pixel. The wafer mesh may be removed.
Type:
Grant
Filed:
September 4, 2020
Date of Patent:
April 30, 2024
Assignee:
Lumileds LLC
Inventors:
Danielle Russell Chamberlin, Erik Maria Roeling, Sumit Gangwal, Niek Van Leth, Oleg Shchekin
Abstract: Systems and methods for failure characterization of secure programmable logic devices (PLDs) are disclosed. An example system includes a secure PLD including programmable logic blocks (PLBs) arranged in PLD fabric of the secure PLD, and a configuration engine configured to program the PLD fabric according to a configuration image stored in non-volatile memory (NVM) of the secure PLD and/or coupled through a configuration input/output (I/O) of the secure PLD. The secure PLD is configured to receive a failure characterization (FC) command from the PLD fabric or an external system coupled to the secure PLD through the configuration I/O, and to execute the FC command to, at least in part, erase and/or nullify portions of the NVM. The secure PLD may also be configured to boot a debug configuration for the PLD fabric that identifies and/or characterizes operational failures of the secure PLD.
Type:
Grant
Filed:
November 9, 2020
Date of Patent:
April 30, 2024
Assignee:
Lattice Semiconductor Corporation
Inventors:
Fulong Zhang, Srirama Chandra, Sreepada Hegade, Joel Coplen, Wei Han, Yu Sun
Abstract: A system includes an upper section, having a first lateral end. The upper section has upper production tubing configured to be a conduit for production fluids, an upper electrical cable configured to transmit electricity, and a sub-surface safety valve fixed to the upper production tubing. The system further includes a lower section having a second lateral end, lower production tubing configured to be a conduit for the production fluids, a lower electrical cable configured to transmit electricity, an electric submersible pump assembly, and an anchor configured to hold the lower section within the casing string. A stinger assembly is fixed to the first lateral end of the upper section, and a stinger receptacle is fixed to the second lateral end of the lower section. The stinger receptacle is configured to receive the stinger assembly and create an electrical connection between the upper section and the lower section.
Abstract: A wavelength converting layer may have a glass or a silicon porous support structure. The wavelength converting layer may also have a cured portion of wavelength converting particles and a binder laminated onto the porous glass or silicon support structure.
Abstract: A service providing apparatus includes a first management unit that manages items of device identification information for identifying devices used by users and items of character identification information for identifying characters of the devices, in such a manner that the items of device identification information are associated with the items of character identification information; a second management unit that manages, for each of the users, one or more items of service identification information for identifying services corresponding to an item of character identification information; and a service providing unit that provides, using an item of service identification information, a service in accordance with a character of a device to a user who uses the device.
Abstract: An insulation system for an appliance includes a first vacuum insulated structure having a first set of sidewalls that define a first refrigerating compartment, a second vacuum insulated structure having a second set of sidewalls that define a second refrigerating compartment and a medial insulation structure having a rigid perimeter wall. The rigid perimeter wall includes a front portion that defines at least one hinge support adapted to support an appliance door. The rigid perimeter wall defines an insulating cavity that is filled with an insulating material. The first vacuum insulated structure engages a first edge of the perimeter wall and the second vacuum insulated structure engages a second edge of the perimeter wall.
Abstract: An adjustable shelf support includes a fastener, a stationary support, and a slidable support. The stationary support includes a first body, a first aperture formed through the first body, and a first plurality of ledges that protrude outward away from the first body. The slidable support includes a second body, a second aperture formed through the second body, and a second plurality of ledges that protrude outward away from the second body. A ledge of the second plurality of ledges is positioned on a ledge of the first plurality of ledges. The fastener is inserted through the second aperture and the first aperture to further mount the slidable support to the stationary support.
Type:
Grant
Filed:
May 17, 2022
Date of Patent:
April 30, 2024
Assignee:
Sub-Zero Group, Inc.
Inventors:
Brant David Springer, Michelle Flachs Croce
Abstract: A circuit for monitoring usage of an active field effect transistor (FET) includes the active FET and a reference FET, formed in a same structure as the active FET. The active FET and the reference FET both are pFET or both are nFET, and are stacked on each other at a common gate. The circuit also includes a differential current sense circuit (DCSC) and a plurality of switches for connecting terminals of the FETs to logic voltage, ground voltage, and/or the DCSC. The DCSC is configured to measure and compare currents through each of the active and reference FETs when a threshold voltage is applied to the common gate.
Type:
Grant
Filed:
November 7, 2021
Date of Patent:
April 16, 2024
Assignee:
International Business Machines Corporation
Inventors:
Jody Akana, Molly Anderson, Bartley K. Andre, Shota Aoyagi, Anthony Michael Ashcroft, Marine C. Bataille, Jeremy Bataillou, Abidur Rahman Chowdhury, Clara Geneviève Marine Courtaigne, Markus Diebel, Jonathan Gomez Garcia, M. Evans Hankey, Richard P. Howarth, Jonathan P. Ive, Julian Jaede, Duncan Robert Kerr, Peter Russell-Clarke, Benjamin Andrew Shaffer, Joe Sung-Ho Tan, Clement Tissandier, Eugene Antony Whang